powerpc fixes for 4.17 #6
Just three commits. The two cxl ones are not fixes per se, but they modify code that was added this cycle so that it will work with a recent firmware change. And then a fix for a recent commit that added sleeps in the NVRAM code, which needs to be more careful and not sleep if eg. we're called in the panic() path. Thanks to: Nicholas Piggin, Philippe Bergheaud, Christophe Lombard. -----BEGIN PGP SIGNATURE----- iQIwBAABCAAaBQJa/tZPExxtcGVAZWxsZXJtYW4uaWQuYXUACgkQUevqPMjhpYAZ 1xAAtFpiF0YzTigwxSJBrDHjj+JkkPrHZ0OtItIFI6V3FaerbL6ZFJyn2/wfM7N7 v5wluFucSq4I96pMMecLJx7KGMFMBg1GoMbToEM9dqY2mDxK6pvrXX8RJ3dafMql N+NsaJptdGm8hu4HB//P752nvjH9G2xARIc4twMPdXdBTyINtCXhTPFOtZQN0c4V IStGkchwkyJPdzQHy1T+T1crKrgL1hqcTX0ubC7iedX8L1H+pdxm58GUo4zQTVKF 5ZOWYPYScawdPQJSi/KEaZqYW9nPiJiE0zd5B5tjGwFQlcZtzIz3PfokdD6vY75g SEbvbOJxdWFiihwCsZPrQyUe7P4RRboLxl5n0YWeK7SYh1eEQ38YeOTkEIy8KKEV tQUR3c3XeWBD8WOpMXuxmwla5HsNgcYhDmSIx96jVX/VVOzKFbpdeYxfbOZDkVK6 puX0Bwm8WVI9wbLtqTdMDtdencn9qOuwX7Pzot0p/XhJGOvwmgS3+rPhzcfU1Ftw 0Y2y5MH+wthj6glxLYro0qSwkUQYnT6KHzY8S1pheN2DgzWVkSWOnIqrWkvcvm3R 10bqg/wBrAQYylTO4jkYKKMBYMgSE3x2nIC08I7nfJ37xQFSwTI5K8WbhSYG8MKo TZxwhgZX/ip4Ylxuk3P0nMx1Tt/DmkvcguuYqgfBKMNMO+U= =yrZc -----END PGP SIGNATURE----- Merge tag 'powerpc-4.17-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: "Just three commits. The two cxl ones are not fixes per se, but they modify code that was added this cycle so that it will work with a recent firmware change. And then a fix for a recent commit that added sleeps in the NVRAM code, which needs to be more careful and not sleep if eg. we're called in the panic() path. Thanks to Nicholas Piggin, Philippe Bergheaud, Christophe Lombard" * tag 'powerpc-4.17-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/powernv: Fix NVRAM sleep in invalid context when crashing cxl: Report the tunneled operations status cxl: Set the PBCQ Tunnel BAR register when enabling capi mode
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commit
2c71d338be
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@ -244,3 +244,11 @@ Description: read only
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Returns 1 if the psl timebase register is synchronized
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with the core timebase register, 0 otherwise.
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Users: https://github.com/ibm-capi/libcxl
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What: /sys/class/cxl/<card>/tunneled_ops_supported
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Date: May 2018
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Contact: linuxppc-dev@lists.ozlabs.org
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Description: read only
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Returns 1 if tunneled operations are supported in capi mode,
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0 otherwise.
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Users: https://github.com/ibm-capi/libcxl
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@ -44,6 +44,10 @@ static ssize_t opal_nvram_read(char *buf, size_t count, loff_t *index)
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return count;
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}
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/*
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* This can be called in the panic path with interrupts off, so use
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* mdelay in that case.
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*/
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static ssize_t opal_nvram_write(char *buf, size_t count, loff_t *index)
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{
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s64 rc = OPAL_BUSY;
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@ -58,10 +62,16 @@ static ssize_t opal_nvram_write(char *buf, size_t count, loff_t *index)
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while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
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rc = opal_write_nvram(__pa(buf), count, off);
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if (rc == OPAL_BUSY_EVENT) {
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msleep(OPAL_BUSY_DELAY_MS);
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if (in_interrupt() || irqs_disabled())
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mdelay(OPAL_BUSY_DELAY_MS);
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else
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msleep(OPAL_BUSY_DELAY_MS);
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opal_poll_events(NULL);
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} else if (rc == OPAL_BUSY) {
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msleep(OPAL_BUSY_DELAY_MS);
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if (in_interrupt() || irqs_disabled())
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mdelay(OPAL_BUSY_DELAY_MS);
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else
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msleep(OPAL_BUSY_DELAY_MS);
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}
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}
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@ -717,6 +717,7 @@ struct cxl {
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bool perst_select_user;
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bool perst_same_image;
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bool psl_timebase_synced;
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bool tunneled_ops_supported;
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/*
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* number of contexts mapped on to this card. Possible values are:
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@ -1742,6 +1742,15 @@ static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
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/* Required for devices using CAPP DMA mode, harmless for others */
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pci_set_master(dev);
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adapter->tunneled_ops_supported = false;
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if (cxl_is_power9()) {
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if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
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dev_info(&dev->dev, "Tunneled operations unsupported\n");
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else
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adapter->tunneled_ops_supported = true;
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}
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if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
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goto err;
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@ -1768,6 +1777,9 @@ static void cxl_deconfigure_adapter(struct cxl *adapter)
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{
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struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
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if (cxl_is_power9())
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pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
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cxl_native_release_psl_err_irq(adapter);
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cxl_unmap_adapter_regs(adapter);
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@ -78,6 +78,15 @@ static ssize_t psl_timebase_synced_show(struct device *device,
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return scnprintf(buf, PAGE_SIZE, "%i\n", adapter->psl_timebase_synced);
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}
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static ssize_t tunneled_ops_supported_show(struct device *device,
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struct device_attribute *attr,
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char *buf)
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{
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struct cxl *adapter = to_cxl_adapter(device);
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return scnprintf(buf, PAGE_SIZE, "%i\n", adapter->tunneled_ops_supported);
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}
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static ssize_t reset_adapter_store(struct device *device,
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struct device_attribute *attr,
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const char *buf, size_t count)
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@ -183,6 +192,7 @@ static struct device_attribute adapter_attrs[] = {
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__ATTR_RO(base_image),
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__ATTR_RO(image_loaded),
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__ATTR_RO(psl_timebase_synced),
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__ATTR_RO(tunneled_ops_supported),
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__ATTR_RW(load_image_on_perst),
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__ATTR_RW(perst_reloads_same_image),
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__ATTR(reset, S_IWUSR, NULL, reset_adapter_store),
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