qlcnic: remove unused definitions from header file
Signed-off-by: Shahed Shaikh <shahed.shaikh@qlogic.com> Signed-off-by: Sony Chacko <sony.chacko@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shahed Shaikh
David S. Miller
parent
7e38d04bcb
commit
2c6196d262
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@ -569,43 +569,6 @@ struct qlcnic_recv_context {
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* the crb QLCNIC_CDRP_CRB_OFFSET.
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*/
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#define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
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#define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
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#define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
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#define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
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#define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
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#define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
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#define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
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#define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
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#define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
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#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
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#define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
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#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
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#define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011
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#define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
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#define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
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#define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
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#define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
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#define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
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#define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
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#define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
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#define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
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#define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
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#define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
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#define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
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#define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
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#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
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#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
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#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
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#define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
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#define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
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#define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
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#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
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#define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
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#define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
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#define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
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#define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037
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#define QLCNIC_RCODE_SUCCESS 0
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#define QLCNIC_RCODE_INVALID_ARGS 6
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@ -1086,7 +1049,6 @@ struct qlcnic_info {
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u16 switch_mode;
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u32 capabilities;
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u8 max_mac_filters;
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u8 reserved1;
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u16 max_mtu;
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u16 max_tx_ques;
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u16 max_rx_ques;
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@ -174,11 +174,9 @@ static int qlcnic_dev_statistics_len(struct qlcnic_adapter *adapter)
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#define QLCNIC_MAX_EEPROM_LEN 1024
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static const u32 diag_registers[] = {
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CRB_CMDPEG_STATE,
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CRB_RCVPEG_STATE,
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CRB_XG_STATE_P3P,
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CRB_FW_CAPABILITIES_1,
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ISR_INT_STATE_REG,
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QLCNIC_CMDPEG_STATE,
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QLCNIC_RCVPEG_STATE,
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QLCNIC_FW_CAPABILITIES,
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QLCNIC_CRB_DRV_ACTIVE,
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QLCNIC_CRB_DEV_STATE,
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QLCNIC_CRB_DRV_STATE,
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@ -191,6 +189,7 @@ static const u32 diag_registers[] = {
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-1
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};
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static const u32 ext_diag_registers[] = {
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CRB_XG_STATE_P3P,
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ISR_INT_STATE_REG,
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@ -389,9 +389,6 @@ enum {
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#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
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#define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
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/* Lock IDs for ROM lock */
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#define ROM_LOCK_DRIVER 0x0d417340
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/******************************************************************************
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*
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* Definitions specific to M25P flash
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@ -451,13 +448,10 @@ enum {
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#define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
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#define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
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#define QLCNIC_PCI_MN_2M (0)
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#define QLCNIC_PCI_MS_2M (0x80000)
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#define QLCNIC_PCI_OCM0_2M (0x000c0000UL)
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#define QLCNIC_PCI_CRBSPACE (0x06000000UL)
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#define QLCNIC_PCI_CAMQM (0x04800000UL)
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#define QLCNIC_PCI_CAMQM_END (0x04800800UL)
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#define QLCNIC_PCI_2MB_SIZE (0x00200000UL)
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#define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL)
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#define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
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@ -501,44 +495,6 @@ enum {
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#define TA_CTL_WRITE BIT_2
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#define TA_CTL_BUSY BIT_3
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/*
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* Register offsets for MN
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*/
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#define MIU_TEST_AGT_BASE (0x90)
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#define MIU_TEST_AGT_ADDR_LO (0x04)
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#define MIU_TEST_AGT_ADDR_HI (0x08)
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#define MIU_TEST_AGT_WRDATA_LO (0x10)
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#define MIU_TEST_AGT_WRDATA_HI (0x14)
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#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20)
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#define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24)
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#define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1)))
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#define MIU_TEST_AGT_RDDATA_LO (0x18)
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#define MIU_TEST_AGT_RDDATA_HI (0x1c)
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#define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28)
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#define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c)
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#define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1)))
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#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
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#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
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/*
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* Register offsets for MS
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*/
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#define SIU_TEST_AGT_BASE (0x60)
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#define SIU_TEST_AGT_ADDR_LO (0x04)
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#define SIU_TEST_AGT_ADDR_HI (0x18)
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#define SIU_TEST_AGT_WRDATA_LO (0x08)
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#define SIU_TEST_AGT_WRDATA_HI (0x0c)
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#define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
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#define SIU_TEST_AGT_RDDATA_LO (0x10)
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#define SIU_TEST_AGT_RDDATA_HI (0x14)
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#define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
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#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
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#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
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/* XG Link status */
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#define XG_LINK_UP 0x10
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#define XG_LINK_DOWN 0x20
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@ -558,9 +514,6 @@ enum {
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#define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000)
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#define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg))
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#define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150))
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#define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154))
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#define QLCNIC_FW_VERSION_SUB (QLCNIC_CAM_RAM(0x158))
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#define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100))
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#define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120))
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#define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124))
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@ -574,27 +527,13 @@ enum {
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#define QLCNIC_CDRP_ARG(i) (QLCNIC_REG(0x18 + ((i) * 4)))
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#define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18))
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#define QLCNIC_ARG1_CRB_OFFSET (QLCNIC_REG(0x1c))
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#define QLCNIC_ARG2_CRB_OFFSET (QLCNIC_REG(0x20))
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#define QLCNIC_ARG3_CRB_OFFSET (QLCNIC_REG(0x24))
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#define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28))
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#define CRB_CMDPEG_STATE (QLCNIC_REG(0x50))
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#define CRB_RCVPEG_STATE (QLCNIC_REG(0x13c))
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#define CRB_XG_STATE_P3P (QLCNIC_REG(0x98))
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#define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8))
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#define CRB_PF_LINK_SPEED_2 (QLCNIC_REG(0xec))
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#define CRB_TEMP_STATE (QLCNIC_REG(0x1b4))
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#define CRB_V2P_0 (QLCNIC_REG(0x290))
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#define CRB_V2P(port) (CRB_V2P_0+((port)*4))
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#define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0))
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#define CRB_FW_CAPABILITIES_1 (QLCNIC_CAM_RAM(0x128))
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#define CRB_FW_CAPABILITIES_2 (QLCNIC_CAM_RAM(0x12c))
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#define CRB_MAC_BLOCK_START (QLCNIC_CAM_RAM(0x1c0))
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/*
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* CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
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@ -621,11 +560,6 @@ enum {
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/* Lock IDs for PHY lock */
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#define PHY_LOCK_DRIVER 0x44524956
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/* Used for PS PCI Memory access */
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#define PCIX_PS_OP_ADDR_LO (0x10000)
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/* via CRB (PS side only) */
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#define PCIX_PS_OP_ADDR_HI (0x10004)
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#define PCIX_INT_VECTOR (0x10100)
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#define PCIX_INT_MASK (0x10104)
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@ -687,17 +621,6 @@ enum {
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#define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c))
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#define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14))
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#define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0))
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#define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8))
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#define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac))
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#define QLCNIC_CRB_DRV_ACTIVE (QLCNIC_CAM_RAM(0x138))
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#define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140))
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#define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144))
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#define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148))
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#define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c))
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#define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x174))
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#define QLCNIC_CRB_DEV_NPAR_STATE (QLCNIC_CAM_RAM(0x19c))
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#define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c)
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#define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860)
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@ -716,7 +639,6 @@ enum {
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#define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */
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#define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */
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#define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) & (1 << (FN * 4)))
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#define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4)))
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#define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4)))
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#define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4)))
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@ -774,26 +696,13 @@ struct qlcnic_legacy_intr_set {
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u32 pci_int_reg;
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};
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#define QLCNIC_FW_API 0x1b216c
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#define QLCNIC_DRV_OP_MODE 0x1b2170
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#define QLCNIC_MSIX_BASE 0x132110
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#define QLCNIC_MAX_PCI_FUNC 8
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#define QLCNIC_MAX_VLAN_FILTERS 64
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/* FW dump defines */
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#define MIU_TEST_CTR 0x41000090
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#define MIU_TEST_ADDR_LO 0x41000094
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#define MIU_TEST_ADDR_HI 0x41000098
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#define FLASH_ROM_WINDOW 0x42110030
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#define FLASH_ROM_DATA 0x42150000
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static const u32 FW_DUMP_LEVELS[] = {
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0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff };
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static const u32 MIU_TEST_READ_DATA[] = {
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0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC, };
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#define QLCNIC_FW_DUMP_REG1 0x00130060
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#define QLCNIC_FW_DUMP_REG2 0x001e0000
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#define QLCNIC_FLASH_SEM2_LK 0x0013C010
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