EDAC/amd64: Adjust address translation for Hygon family 18h model 4h
Add Hygon family 18h model 4h processor support for DramOffset and HiAddrOffset, and get the socket interleaving number from DramBase- Address(D18F0x110). Update intlv_num_chan and num_intlv_bits support for Hygon family 18h model 4h processor. Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Jinliang Zheng <alexjlzheng@tencent.com> Reviewed-by: Bin Lai <robinlai@tencent.com> Signed-off-by: Jinliang Zheng <alexjlzheng@tencent.com> Reviewed-by: caelli <caelli@tencent.com> Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
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@ -713,13 +713,21 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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u8 cs_mask, cs_id = 0;
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bool hash_enabled = false;
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/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
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if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
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/* Read DramOffset, check if base 1 is used. */
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if (hygon_f18h_m4h() &&
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amd_df_indirect_read(nid, 0, 0x214, umc, &tmp))
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goto out_err;
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else if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
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goto out_err;
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/* Remove HiAddrOffset from normalized address, if enabled: */
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if (tmp & BIT(0)) {
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u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
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u64 hi_addr_offset;
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if (hygon_f18h_m4h())
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hi_addr_offset = (tmp & GENMASK_ULL(31, 18)) << 8;
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else
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hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
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if (norm_addr >= hi_addr_offset) {
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ret_addr -= hi_addr_offset;
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@ -738,6 +746,9 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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goto out_err;
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}
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intlv_num_sockets = 0;
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if (hygon_f18h_m4h())
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intlv_num_sockets = (tmp >> 2) & 0x3;
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lgcy_mmio_hole_en = tmp & BIT(1);
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intlv_num_chan = (tmp >> 4) & 0xF;
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intlv_addr_sel = (tmp >> 8) & 0x7;
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@ -754,6 +765,7 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
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goto out_err;
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if (!hygon_f18h_m4h())
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intlv_num_sockets = (tmp >> 8) & 0x1;
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intlv_num_dies = (tmp >> 10) & 0x3;
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dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
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@ -764,6 +776,10 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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switch (intlv_num_chan) {
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case 0: intlv_num_chan = 0; break;
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case 1: intlv_num_chan = 1; break;
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case 2:
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if (hygon_f18h_m4h())
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intlv_num_chan = 2;
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break;
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case 3: intlv_num_chan = 2; break;
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case 5: intlv_num_chan = 3; break;
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case 7: intlv_num_chan = 4; break;
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@ -790,8 +806,9 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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/* Add a bit if sockets are interleaved. */
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num_intlv_bits += intlv_num_sockets;
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/* Assert num_intlv_bits <= 4 */
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if (num_intlv_bits > 4) {
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/* Assert num_intlv_bits in the correct range. */
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if ((hygon_f18h_m4h() && num_intlv_bits > 7) ||
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(!hygon_f18h_m4h() && num_intlv_bits > 4)) {
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pr_err("%s: Invalid interleave bits %d.\n",
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__func__, num_intlv_bits);
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goto out_err;
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@ -810,6 +827,9 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
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goto out_err;
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if (hygon_f18h_m4h())
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cs_fabric_id = (tmp >> 8) & 0x7FF;
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else
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cs_fabric_id = (tmp >> 8) & 0xFF;
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die_id_bit = 0;
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@ -830,8 +850,13 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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/* If interleaved over more than 1 die. */
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if (intlv_num_dies) {
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sock_id_bit = die_id_bit + intlv_num_dies;
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if (hygon_f18h_m4h()) {
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die_id_shift = (tmp >> 12) & 0xF;
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die_id_mask = tmp & 0x7FF;
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} else {
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die_id_shift = (tmp >> 24) & 0xF;
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die_id_mask = (tmp >> 8) & 0xFF;
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}
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cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
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}
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@ -839,6 +864,9 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
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/* If interleaved over more than 1 socket. */
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if (intlv_num_sockets) {
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socket_id_shift = (tmp >> 28) & 0xF;
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if (hygon_f18h_m4h())
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socket_id_mask = (tmp >> 16) & 0x7FF;
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else
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socket_id_mask = (tmp >> 16) & 0xFF;
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cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
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