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Merge branch 'next-samsung-clkdev-fix' into next-samsung-devel

This commit is contained in:
Kukjin Kim 2011-07-21 17:28:23 +09:00
parent 2d21237e38 e480559995
commit 2c0b687100
32 changed files with 302 additions and 738 deletions
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6
arch/arm/Kconfig
View File

@ -682,6 +682,7 @@ config ARCH_S3C2410
select GENERIC_GPIO select GENERIC_GPIO
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_I2C if I2C
help help
@ -699,6 +700,7 @@ config ARCH_S3C64XX
select CPU_V6 select CPU_V6
select ARM_VIC select ARM_VIC
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select NO_IOPORT select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
@ -723,6 +725,7 @@ config ARCH_S5P64X0
select CPU_V6 select CPU_V6
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK select HAVE_SCHED_CLOCK
@ -736,6 +739,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100" bool "Samsung S5PC100"
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select CPU_V7 select CPU_V7
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET select ARCH_USES_GETTIMEOFFSET
@ -751,6 +755,7 @@ config ARCH_S5PV210
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
@ -767,6 +772,7 @@ config ARCH_EXYNOS4
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C_RTC if RTC_CLASS

177
arch/arm/mach-exynos4/clock.c
View File

@ -27,24 +27,20 @@
static struct clk clk_sclk_hdmi27m = { static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m", .name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_hdmiphy = { static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy", .name = "sclk_hdmiphy",
.id = -1,
}; };
static struct clk clk_sclk_usbphy0 = { static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0", .name = "sclk_usbphy0",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_usbphy1 = { static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1", .name = "sclk_usbphy1",
.id = -1,
}; };
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.sources = &clk_src_apll, .sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_sclk_apll = { static struct clksrc_clk clk_sclk_apll = {
.clk = { .clk = {
.name = "sclk_apll", .name = "sclk_apll",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.sources = &clk_src_epll, .sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
static struct clksrc_clk clk_moutcore = { static struct clksrc_clk clk_moutcore = {
.clk = { .clk = {
.name = "moutcore", .name = "moutcore",
.id = -1,
}, },
.sources = &clkset_moutcore, .sources = &clkset_moutcore,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
static struct clksrc_clk clk_coreclk = { static struct clksrc_clk clk_coreclk = {
.clk = { .clk = {
.name = "core_clk", .name = "core_clk",
.id = -1,
.parent = &clk_moutcore.clk, .parent = &clk_moutcore.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_armclk = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
}; };
@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_aclk_corem0 = { static struct clksrc_clk clk_aclk_corem0 = {
.clk = { .clk = {
.name = "aclk_corem0", .name = "aclk_corem0",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
static struct clksrc_clk clk_aclk_cores = { static struct clksrc_clk clk_aclk_cores = {
.clk = { .clk = {
.name = "aclk_cores", .name = "aclk_cores",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
static struct clksrc_clk clk_aclk_corem1 = { static struct clksrc_clk clk_aclk_corem1 = {
.clk = { .clk = {
.name = "aclk_corem1", .name = "aclk_corem1",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
static struct clksrc_clk clk_periphclk = { static struct clksrc_clk clk_periphclk = {
.clk = { .clk = {
.name = "periphclk", .name = "periphclk",
.id = -1,
.parent = &clk_coreclk.clk, .parent = &clk_coreclk.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
static struct clksrc_clk clk_mout_corebus = { static struct clksrc_clk clk_mout_corebus = {
.clk = { .clk = {
.name = "mout_corebus", .name = "mout_corebus",
.id = -1,
}, },
.sources = &clkset_mout_corebus, .sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
static struct clksrc_clk clk_sclk_dmc = { static struct clksrc_clk clk_sclk_dmc = {
.clk = { .clk = {
.name = "sclk_dmc", .name = "sclk_dmc",
.id = -1,
.parent = &clk_mout_corebus.clk, .parent = &clk_mout_corebus.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clksrc_clk clk_aclk_cored = { static struct clksrc_clk clk_aclk_cored = {
.clk = { .clk = {
.name = "aclk_cored", .name = "aclk_cored",
.id = -1,
.parent = &clk_sclk_dmc.clk, .parent = &clk_sclk_dmc.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
static struct clksrc_clk clk_aclk_corep = { static struct clksrc_clk clk_aclk_corep = {
.clk = { .clk = {
.name = "aclk_corep", .name = "aclk_corep",
.id = -1,
.parent = &clk_aclk_cored.clk, .parent = &clk_aclk_cored.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
static struct clksrc_clk clk_aclk_acp = { static struct clksrc_clk clk_aclk_acp = {
.clk = { .clk = {
.name = "aclk_acp", .name = "aclk_acp",
.id = -1,
.parent = &clk_mout_corebus.clk, .parent = &clk_mout_corebus.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
static struct clksrc_clk clk_pclk_acp = { static struct clksrc_clk clk_pclk_acp = {
.clk = { .clk = {
.name = "pclk_acp", .name = "pclk_acp",
.id = -1,
.parent = &clk_aclk_acp.clk, .parent = &clk_aclk_acp.clk,
}, },
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
static struct clksrc_clk clk_aclk_200 = { static struct clksrc_clk clk_aclk_200 = {
.clk = { .clk = {
.name = "aclk_200", .name = "aclk_200",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
static struct clksrc_clk clk_aclk_100 = { static struct clksrc_clk clk_aclk_100 = {
.clk = { .clk = {
.name = "aclk_100", .name = "aclk_100",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
static struct clksrc_clk clk_aclk_160 = { static struct clksrc_clk clk_aclk_160 = {
.clk = { .clk = {
.name = "aclk_160", .name = "aclk_160",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
static struct clksrc_clk clk_aclk_133 = { static struct clksrc_clk clk_aclk_133 = {
.clk = { .clk = {
.name = "aclk_133", .name = "aclk_133",
.id = -1,
}, },
.sources = &clkset_aclk, .sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = { static struct clksrc_clk clk_vpllsrc = {
.clk = { .clk = {
.name = "vpll_src", .name = "vpll_src",
.id = -1,
.enable = exynos4_clksrc_mask_top_ctrl, .enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = {
.clk = { .clk = {
.name = "sclk_vpll", .name = "sclk_vpll",
.id = -1,
}, },
.sources = &clkset_sclk_vpll, .sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24), .ctrlbit = (1<<24),
}, { }, {
.name = "csis", .name = "csis",
.id = 0, .devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "csis", .name = "csis",
.id = 1, .devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 2, .devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 3, .devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "fimd", .name = "fimd",
.id = 0, .devname = "s5pv310-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl, .enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "fimd", .name = "fimd",
.id = 1, .devname = "s5pv310-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl, .enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "sataphy", .name = "sataphy",
.id = -1,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "hsmmc", .name = "dwmmc",
.id = 4,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "sata", .name = "sata",
.id = -1,
.parent = &clk_aclk_133.clk, .parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 0, .devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 1, .devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "keypad", .name = "keypad",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl, .enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
}, { }, {
.name = "usbhost", .name = "usbhost",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl , .enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "spi", .name = "spi",
.id = 2, .devname = "s3c64xx-spi.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
}, { }, {
.name = "fimg2d", .name = "fimg2d",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 2, .devname = "s3c2440-i2c.2",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 3, .devname = "s3c2440-i2c.3",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 4, .devname = "s3c2440-i2c.4",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 5, .devname = "s3c2440-i2c.5",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 6, .devname = "s3c2440-i2c.6",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 7, .devname = "s3c2440-i2c.7",
.parent = &clk_aclk_100.clk, .parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "SYSMMU_MDMA", .name = "SYSMMU_MDMA",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "SYSMMU_FIMC0", .name = "SYSMMU_FIMC0",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "SYSMMU_FIMC1", .name = "SYSMMU_FIMC1",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "SYSMMU_FIMC2", .name = "SYSMMU_FIMC2",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "SYSMMU_FIMC3", .name = "SYSMMU_FIMC3",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "SYSMMU_JPEG", .name = "SYSMMU_JPEG",
.id = -1,
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, { }, {
.name = "SYSMMU_FIMD0", .name = "SYSMMU_FIMD0",
.id = -1,
.enable = exynos4_clk_ip_lcd0_ctrl, .enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_FIMD1", .name = "SYSMMU_FIMD1",
.id = -1,
.enable = exynos4_clk_ip_lcd1_ctrl, .enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_PCIe", .name = "SYSMMU_PCIe",
.id = -1,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "SYSMMU_G2D", .name = "SYSMMU_G2D",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "SYSMMU_ROTATOR", .name = "SYSMMU_ROTATOR",
.id = -1,
.enable = exynos4_clk_ip_image_ctrl, .enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_TV", .name = "SYSMMU_TV",
.id = -1,
.enable = exynos4_clk_ip_tv_ctrl, .enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "SYSMMU_MFC_L", .name = "SYSMMU_MFC_L",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl, .enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "SYSMMU_MFC_R", .name = "SYSMMU_MFC_R",
.id = -1,
.enable = exynos4_clk_ip_mfc_ctrl, .enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
} }
@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "uart", .name = "uart",
.id = 0, .devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "uart", .name = "uart",
.id = 4, .devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "uart", .name = "uart",
.id = 5, .devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl, .enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
} }
@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
static struct clksrc_clk clk_mout_g2d0 = { static struct clksrc_clk clk_mout_g2d0 = {
.clk = { .clk = {
.name = "mout_g2d0", .name = "mout_g2d0",
.id = -1,
}, },
.sources = &clkset_mout_g2d0, .sources = &clkset_mout_g2d0,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
static struct clksrc_clk clk_mout_g2d1 = { static struct clksrc_clk clk_mout_g2d1 = {
.clk = { .clk = {
.name = "mout_g2d1", .name = "mout_g2d1",
.id = -1,
}, },
.sources = &clkset_mout_g2d1, .sources = &clkset_mout_g2d1,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = {
static struct clksrc_clk clk_dout_mmc0 = { static struct clksrc_clk clk_dout_mmc0 = {
.clk = { .clk = {
.name = "dout_mmc0", .name = "dout_mmc0",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
static struct clksrc_clk clk_dout_mmc1 = { static struct clksrc_clk clk_dout_mmc1 = {
.clk = { .clk = {
.name = "dout_mmc1", .name = "dout_mmc1",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
static struct clksrc_clk clk_dout_mmc2 = { static struct clksrc_clk clk_dout_mmc2 = {
.clk = { .clk = {
.name = "dout_mmc2", .name = "dout_mmc2",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
static struct clksrc_clk clk_dout_mmc3 = { static struct clksrc_clk clk_dout_mmc3 = {
.clk = { .clk = {
.name = "dout_mmc3", .name = "dout_mmc3",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
static struct clksrc_clk clk_dout_mmc4 = { static struct clksrc_clk clk_dout_mmc4 = {
.clk = { .clk = {
.name = "dout_mmc4", .name = "dout_mmc4",
.id = -1,
}, },
.sources = &clkset_group, .sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 0, .devname = "s5pv210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 1, .devname = "s5pv210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 2, .devname = "s5pv210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 3, .devname = "s5pv210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwm", .name = "sclk_pwm",
.id = -1,
.enable = exynos4_clksrc_mask_peril0_ctrl, .enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = 0, .devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = 1, .devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28), .ctrlbit = (1 << 28),
}, },
@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, },
@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 0, .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 1, .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 2, .devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 3, .devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl, .enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = 0, .devname = "s5pv310-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl, .enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = 1, .devname = "s5pv310-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl, .enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_sata", .name = "sclk_sata",
.id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, },
@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 2, .devname = "s3c64xx-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl, .enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimg2d", .name = "sclk_fimg2d",
.id = -1,
}, },
.sources = &clkset_mout_g2d, .sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_dout_mmc0.clk, .parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_dout_mmc1.clk, .parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_dout_mmc2.clk, .parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_dout_mmc3.clk, .parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_dwmmc",
.id = 4,
.parent = &clk_dout_mmc4.clk, .parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),

7
arch/arm/mach-exynos4/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

36
arch/arm/mach-s3c2412/clock.c
View File

@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
static struct clk clk_erefclk = { static struct clk clk_erefclk = {
.name = "erefclk", .name = "erefclk",
.id = -1,
}; };
static struct clk clk_urefclk = { static struct clk clk_urefclk = {
.name = "urefclk", .name = "urefclk",
.id = -1,
}; };
static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
static struct clk clk_usysclk = { static struct clk clk_usysclk = {
.name = "usysclk", .name = "usysclk",
.id = -1,
.parent = &clk_xtal, .parent = &clk_xtal,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_usysclk, .set_parent = s3c2412_setparent_usysclk,
@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
static struct clk clk_mrefclk = { static struct clk clk_mrefclk = {
.name = "mrefclk", .name = "mrefclk",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}; };
static struct clk clk_mdivclk = { static struct clk clk_mdivclk = {
.name = "mdivclk", .name = "mdivclk",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}; };
static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = { static struct clk clk_usbsrc = {
.name = "usbsrc", .name = "usbsrc",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_usbsrc, .get_rate = s3c2412_getrate_usbsrc,
.set_rate = s3c2412_setrate_usbsrc, .set_rate = s3c2412_setrate_usbsrc,
@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = { static struct clk clk_msysclk = {
.name = "msysclk", .name = "msysclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_msysclk, .set_parent = s3c2412_setparent_msysclk,
}, },
@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_armclk = { static struct clk clk_armclk = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_msysclk, .parent = &clk_msysclk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_armclk, .set_parent = s3c2412_setparent_armclk,
@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = { static struct clk clk_uart = {
.name = "uartclk", .name = "uartclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_uart, .get_rate = s3c2412_getrate_uart,
.set_rate = s3c2412_setrate_uart, .set_rate = s3c2412_setrate_uart,
@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = { static struct clk clk_i2s = {
.name = "i2sclk", .name = "i2sclk",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_i2s, .get_rate = s3c2412_getrate_i2s,
.set_rate = s3c2412_setrate_i2s, .set_rate = s3c2412_setrate_i2s,
@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = { static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */ .name = "camif-upll", /* same as 2440 name */
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_cam, .get_rate = s3c2412_getrate_cam,
.set_rate = s3c2412_setrate_cam, .set_rate = s3c2412_setrate_cam,
@ -463,37 +452,31 @@ static struct clk clk_cam = {
static struct clk init_clocks_disable[] = { static struct clk init_clocks_disable[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_NAND, .ctrlbit = S3C2412_CLKCON_NAND,
}, { }, {
.name = "sdi", .name = "sdi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SDI, .ctrlbit = S3C2412_CLKCON_SDI,
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_ADC, .ctrlbit = S3C2412_CLKCON_ADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIC, .ctrlbit = S3C2412_CLKCON_IIC,
}, { }, {
.name = "iis", .name = "iis",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIS, .ctrlbit = S3C2412_CLKCON_IIS,
}, { }, {
.name = "spi", .name = "spi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SPI, .ctrlbit = S3C2412_CLKCON_SPI,
@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "dma", .name = "dma",
.id = 0,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0, .ctrlbit = S3C2412_CLKCON_DMA0,
}, { }, {
.name = "dma", .name = "dma",
.id = 1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1, .ctrlbit = S3C2412_CLKCON_DMA1,
}, { }, {
.name = "dma", .name = "dma",
.id = 2,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2, .ctrlbit = S3C2412_CLKCON_DMA2,
}, { }, {
.name = "dma", .name = "dma",
.id = 3,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3, .ctrlbit = S3C2412_CLKCON_DMA3,
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_LCDC, .ctrlbit = S3C2412_CLKCON_LCDC,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_GPIO, .ctrlbit = S3C2412_CLKCON_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBH, .ctrlbit = S3C2412_CLKCON_USBH,
}, { }, {
.name = "usb-device", .name = "usb-device",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBD, .ctrlbit = S3C2412_CLKCON_USBD,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_PWMT, .ctrlbit = S3C2412_CLKCON_PWMT,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c2412-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0, .ctrlbit = S3C2412_CLKCON_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c2412-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1, .ctrlbit = S3C2412_CLKCON_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c2412-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART2, .ctrlbit = S3C2412_CLKCON_UART2,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_RTC, .ctrlbit = S3C2412_CLKCON_RTC,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = 0, .ctrlbit = 0,
}, { }, {
.name = "usb-bus-gadget", .name = "usb-bus-gadget",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_DEV48, .ctrlbit = S3C2412_CLKCON_USB_DEV48,
}, { }, {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable, .enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_HOST48, .ctrlbit = S3C2412_CLKCON_USB_HOST48,

10
arch/arm/mach-s3c2416/clock.c
View File

@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = { [0] = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = { [1] = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
static struct clksrc_clk hsmmc_mux[] = { static struct clksrc_clk hsmmc_mux[] = {
[0] = { [0] = {
.clk = { .clk = {
.id = 0,
.name = "hsmmc-if", .name = "hsmmc-if",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
}, },
@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
}, },
[1] = { [1] = {
.clk = { .clk = {
.id = 1,
.name = "hsmmc-if", .name = "hsmmc-if",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
}, },
@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = { static struct clk hsmmc0_clk = {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2416_HCLKCON_HSMMC0, .ctrlbit = S3C2416_HCLKCON_HSMMC0,

3
arch/arm/mach-s3c2440/clock.c
View File

@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
static struct clk s3c2440_clk_cam = { static struct clk s3c2440_clk_cam = {
.name = "camif", .name = "camif",
.id = -1,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA, .ctrlbit = S3C2440_CLKCON_CAMERA,
}; };
static struct clk s3c2440_clk_cam_upll = { static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll", .name = "camif-upll",
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.set_rate = s3c2440_camif_upll_setrate, .set_rate = s3c2440_camif_upll_setrate,
.round_rate = s3c2440_camif_upll_round, .round_rate = s3c2440_camif_upll_round,
@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
static struct clk s3c2440_clk_ac97 = { static struct clk s3c2440_clk_ac97 = {
.name = "ac97", .name = "ac97",
.id = -1,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA, .ctrlbit = S3C2440_CLKCON_CAMERA,
}; };

16
arch/arm/mach-s3c2443/clock.c
View File

@ -59,7 +59,6 @@
static struct clk clk_i2s_ext = { static struct clk clk_i2s_ext = {
.name = "i2s-ext", .name = "i2s-ext",
.id = -1,
}; };
/* armdiv /* armdiv
@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
static struct clk clk_armdiv = { static struct clk clk_armdiv = {
.name = "armdiv", .name = "armdiv",
.id = -1,
.parent = &clk_msysclk.clk, .parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.round_rate = s3c2443_armclk_roundrate, .round_rate = s3c2443_armclk_roundrate,
@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
static struct clksrc_clk clk_arm = { static struct clksrc_clk clk_arm = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
}, },
.sources = &(struct clksrc_sources) { .sources = &(struct clksrc_sources) {
.sources = clk_arm_sources, .sources = clk_arm_sources,
@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = { static struct clksrc_clk clk_hsspi = {
.clk = { .clk = {
.name = "hsspi", .name = "hsspi",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK, .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = { static struct clksrc_clk clk_hsmmc_div = {
.clk = { .clk = {
.name = "hsmmc-div", .name = "hsmmc-div",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = { static struct clk clk_hsmmc = {
.name = "hsmmc-if", .name = "hsmmc-if",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hsmmc_div.clk, .parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc, .enable = s3c2443_enable_hsmmc,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
static struct clksrc_clk clk_i2s_eplldiv = { static struct clksrc_clk clk_i2s_eplldiv = {
.clk = { .clk = {
.name = "i2s-eplldiv", .name = "i2s-eplldiv",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
static struct clksrc_clk clk_i2s = { static struct clksrc_clk clk_i2s = {
.clk = { .clk = {
.name = "i2s-if", .name = "i2s-if",
.id = -1,
.ctrlbit = S3C2443_SCLKCON_I2SCLK, .ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "sdi", .name = "sdi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI, .ctrlbit = S3C2443_PCLKCON_SDI,
}, { }, {
.name = "iis", .name = "iis",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS, .ctrlbit = S3C2443_PCLKCON_IIS,
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c2410-spi.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0, .ctrlbit = S3C2443_PCLKCON_SPI0,
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c2410-spi.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI1, .ctrlbit = S3C2443_PCLKCON_SPI1,

86
arch/arm/mach-s3c64xx/clock.c
View File

@ -39,7 +39,6 @@
static struct clk clk_ext_xtal_mux = { static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal", .name = "ext_xtal",
.id = -1,
}; };
#define clk_fin_apll clk_ext_xtal_mux #define clk_fin_apll clk_ext_xtal_mux
@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
struct clk clk_h2 = { struct clk clk_h2 = {
.name = "hclk2", .name = "hclk2",
.id = -1,
.rate = 0, .rate = 0,
}; };
struct clk clk_27m = { struct clk clk_27m = {
.name = "clk_27m", .name = "clk_27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
struct clk clk_48m = { struct clk clk_48m = {
.name = "clk_48m", .name = "clk_48m",
.id = -1,
.rate = 48000000, .rate = 48000000,
.enable = clk_48m_ctrl, .enable = clk_48m_ctrl,
}; };
struct clk clk_xusbxti = { struct clk clk_xusbxti = {
.name = "xusbxti", .name = "xusbxti",
.id = -1,
.rate = 48000000, .rate = 48000000,
}; };
@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC, .ctrlbit = S3C_CLKCON_PCLK_RTC,
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC, .ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC, .ctrlbit = S3C_CLKCON_PCLK_IIC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1, .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0, .ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1, .ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, { }, {
#ifdef CONFIG_CPU_S3C6410 #ifdef CONFIG_CPU_S3C6410
.name = "iis", .name = "iis",
.id = -1, /* There's only one IISv4 port */
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2, .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, { }, {
#endif #endif
.name = "keypad", .name = "keypad",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD, .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0, .ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1, .ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48, .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48, .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48, .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48, .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, { }, {
.name = "48m", .name = "48m",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48, .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, { }, {
.name = "dma0", .name = "dma0",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0, .ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, { }, {
.name = "dma1", .name = "dma1",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1, .ctrlbit = S3C_CLKCON_HCLK_DMA1,
@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD, .ctrlbit = S3C_CLKCON_HCLK_LCD,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO, .ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST, .ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0, .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1, .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2, .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB, .ctrlbit = S3C_CLKCON_HCLK_USB,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM, .ctrlbit = S3C_CLKCON_PCLK_PWM,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c6400-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0, .ctrlbit = S3C_CLKCON_PCLK_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c6400-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1, .ctrlbit = S3C_CLKCON_PCLK_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c6400-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2, .ctrlbit = S3C_CLKCON_PCLK_UART2,
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c6400-uart.3",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c64xx_pclk_ctrl, .enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3, .ctrlbit = S3C_CLKCON_PCLK_UART3,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT, .ctrlbit = S3C_CLKCON_PCLK_WDT,
}, { }, {
.name = "ac97", .name = "ac97",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97, .ctrlbit = S3C_CLKCON_PCLK_AC97,
}, { }, {
.name = "cfcon", .name = "cfcon",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST, .ctrlbit = S3C_CLKCON_HCLK_IHOST,
@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
static struct clk clk_fout_apll = { static struct clk clk_fout_apll = {
.name = "fout_apll", .name = "fout_apll",
.id = -1,
}; };
static struct clk *clk_src_apll_list[] = { static struct clk *clk_src_apll_list[] = {
@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll, .sources = &clk_src_apll,
@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll, .sources = &clk_src_epll,
@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
static struct clk clk_arm = { static struct clk clk_arm = {
.name = "armclk", .name = "armclk",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate, .get_rate = s3c64xx_clk_arm_get_rate,
@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
static struct clk clk_dout_mpll = { static struct clk clk_dout_mpll = {
.name = "dout_mpll", .name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk, .parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops, .ops = &clk_dout_ops,
}; };
@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
static struct clk clk_iis_cd0 = { static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0", .name = "iis_cdclk0",
.id = -1,
}; };
static struct clk clk_iis_cd1 = { static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1", .name = "iis_cdclk1",
.id = -1,
}; };
static struct clk clk_iisv4_cd = { static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4", .name = "iis_cdclk_v4",
.id = -1,
}; };
static struct clk clk_pcm_cd = { static struct clk clk_pcm_cd = {
.name = "pcm_cdclk", .name = "pcm_cdclk",
.id = -1,
}; };
static struct clk *clkset_audio0_list[] = { static struct clk *clkset_audio0_list[] = {
@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 0, .devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0, .ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 1, .devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1, .ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "mmc_bus", .name = "mmc_bus",
.id = 2, .devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2, .ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST, .ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART, .ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */ /* Where does UCLK0 come from? */
.clk = { .clk = {
.name = "spi-bus", .name = "spi-bus",
.id = 0, .devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0, .ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "spi-bus", .name = "spi-bus",
.id = 1, .devname = "s3c64xx-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 0, .devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0, .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 1, .devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1, .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = 2, .devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "irda-bus", .name = "irda-bus",
.id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA, .ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },
@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "camera", .name = "camera",
.id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM, .ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl, .enable = s3c64xx_sclk_ctrl,
}, },

7
arch/arm/mach-s3c64xx/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

74
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
static struct clksrc_clk clk_hclk = { static struct clksrc_clk clk_hclk = {
.clk = { .clk = {
.name = "clk_hclk", .name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk, .parent = &clk_armclk.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = { static struct clksrc_clk clk_pclk = {
.clk = { .clk = {
.name = "clk_pclk", .name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_hclk_low = { static struct clksrc_clk clk_hclk_low = {
.clk = { .clk = {
.name = "clk_hclk_low", .name = "clk_hclk_low",
.id = -1,
}, },
.sources = &clkset_hclk_low, .sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = { static struct clksrc_clk clk_pclk_low = {
.clk = { .clk = {
.name = "clk_pclk_low", .name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_mem_ctrl, .enable = s5p64x0_mem_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "post", .name = "post",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 5) .ctrlbit = (1 << 5)
}, { }, {
.name = "2d", .name = "2d",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "pdma", .name = "pdma",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20) .ctrlbit = (1 << 20)
}, { }, {
.name = "irom", .name = "irom",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl, .enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "hclk_fimgvg", .name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk1_ctrl, .enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "tsi", .name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl, .enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "pcm", .name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22), .ctrlbit = (1 << 22),
}, { }, {
.name = "gps", .name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, { }, {
.name = "dsim", .name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 28), .ctrlbit = (1 << 28),
}, { }, {
.name = "etm", .name = "etm",
.id = -1,
.parent = &clk_pclk.clk, .parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 29), .ctrlbit = (1 << 29),
}, { }, {
.name = "dmc0", .name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk, .parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30), .ctrlbit = (1 << 30),
}, { }, {
.name = "pclk_fimgvg", .name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk, .parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31), .ctrlbit = (1 << 31),
}, { }, {
.name = "sclk_spi_48", .name = "sclk_spi_48",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22), .ctrlbit = (1 << 22),
}, { }, {
.name = "sclk_spi_48", .name = "sclk_spi_48",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23), .ctrlbit = (1 << 23),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28), .ctrlbit = (1 << 28),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_48m, .parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 29), .ctrlbit = (1 << 29),
@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "intc", .name = "intc",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "mem", .name = "mem",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
static struct clk clk_iis_cd_v40 = { static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40", .name = "iis_cdclk_v40",
.id = -1,
}; };
static struct clk clk_pcm_cd = { static struct clk clk_pcm_cd = {
.name = "pcm_cdclk", .name = "pcm_cdclk",
.id = -1,
}; };
static struct clk *clkset_group1_list[] = { static struct clk *clkset_group1_list[] = {
@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_post", .name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_dispcon", .name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl, .enable = s5p64x0_sclk1_ctrl,
}, },
@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimgvg", .name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl, .enable = s5p64x0_sclk1_ctrl,
}, },
@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_audio2", .name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },

68
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -36,7 +36,6 @@
static struct clksrc_clk clk_mout_dpll = { static struct clksrc_clk clk_mout_dpll = {
.clk = { .clk = {
.name = "mout_dpll", .name = "mout_dpll",
.id = -1,
}, },
.sources = &clk_src_dpll, .sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
static struct clksrc_clk clk_dout_epll = { static struct clksrc_clk clk_dout_epll = {
.clk = { .clk = {
.name = "dout_epll", .name = "dout_epll",
.id = -1,
.parent = &clk_mout_epll.clk, .parent = &clk_mout_epll.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
static struct clksrc_clk clk_mout_hclk_sel = { static struct clksrc_clk clk_mout_hclk_sel = {
.clk = { .clk = {
.name = "mout_hclk_sel", .name = "mout_hclk_sel",
.id = -1,
}, },
.sources = &clkset_hclk_low, .sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
static struct clksrc_clk clk_hclk = { static struct clksrc_clk clk_hclk = {
.clk = { .clk = {
.name = "clk_hclk", .name = "clk_hclk",
.id = -1,
}, },
.sources = &clkset_hclk, .sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = { static struct clksrc_clk clk_pclk = {
.clk = { .clk = {
.name = "clk_pclk", .name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_dout_pwm_ratio0 = { static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = { .clk = {
.name = "clk_dout_pwm_ratio0", .name = "clk_dout_pwm_ratio0",
.id = -1,
.parent = &clk_mout_hclk_sel.clk, .parent = &clk_mout_hclk_sel.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
static struct clksrc_clk clk_pclk_to_wdt_pwm = { static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = { .clk = {
.name = "clk_pclk_to_wdt_pwm", .name = "clk_pclk_to_wdt_pwm",
.id = -1,
.parent = &clk_dout_pwm_ratio0.clk, .parent = &clk_dout_pwm_ratio0.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
static struct clksrc_clk clk_hclk_low = { static struct clksrc_clk clk_hclk_low = {
.clk = { .clk = {
.name = "clk_hclk_low", .name = "clk_hclk_low",
.id = -1,
}, },
.sources = &clkset_hclk_low, .sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = { static struct clksrc_clk clk_pclk_low = {
.clk = { .clk = {
.name = "clk_pclk_low", .name = "clk_pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
}, },
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "usbhost", .name = "usbhost",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "pdma", .name = "pdma",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "usbotg", .name = "usbotg",
.id = -1,
.parent = &clk_hclk_low.clk, .parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl, .enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22), .ctrlbit = (1 << 22),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
}, { }, {
.name = "dmc0", .name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk, .parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30), .ctrlbit = (1 << 30),
@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "intc", .name = "intc",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "mem", .name = "mem",
.id = -1,
.parent = &clk_hclk.clk, .parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl, .enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk, .parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_pclk_low.clk, .parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl, .enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = {
.clk = { .clk = {
.name = "audio-bus", .name = "audio-bus",
.id = -1,
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk, .parent = &clk_dout_epll.clk,
@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = -1,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21), .ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = -1,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "aclk_mali", .name = "aclk_mali",
.id = -1,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl, .enable = s5p64x0_sclk1_ctrl,
}, },
@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_2d", .name = "sclk_2d",
.id = -1,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_usi", .name = "sclk_usi",
.id = -1,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_camif", .name = "sclk_camif",
.id = -1,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },
@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_dispcon", .name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl, .enable = s5p64x0_sclk1_ctrl,
}, },
@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_hsmmc44", .name = "sclk_hsmmc44",
.id = -1,
.ctrlbit = (1 << 30), .ctrlbit = (1 << 30),
.enable = s5p64x0_sclk_ctrl, .enable = s5p64x0_sclk_ctrl,
}, },

7
arch/arm/mach-s5p64x0/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

163
arch/arm/mach-s5pc100/clock.c
View File

@ -31,7 +31,6 @@
static struct clk s5p_clk_otgphy = { static struct clk s5p_clk_otgphy = {
.name = "otg_phy", .name = "otg_phy",
.id = -1,
}; };
static struct clk *clk_src_mout_href_list[] = { static struct clk *clk_src_mout_href_list[] = {
@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
static struct clksrc_clk clk_mout_href = { static struct clksrc_clk clk_mout_href = {
.clk = { .clk = {
.name = "mout_href", .name = "mout_href",
.id = -1,
}, },
.sources = &clk_src_mout_href, .sources = &clk_src_mout_href,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
static struct clksrc_clk clk_mout_48m = { static struct clksrc_clk clk_mout_48m = {
.clk = { .clk = {
.name = "mout_48m", .name = "mout_48m",
.id = -1,
}, },
.sources = &clk_src_mout_48m, .sources = &clk_src_mout_48m,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.sources = &clk_src_apll, .sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.sources = &clk_src_epll, .sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
static struct clksrc_clk clk_mout_hpll = { static struct clksrc_clk clk_mout_hpll = {
.clk = { .clk = {
.name = "mout_hpll", .name = "mout_hpll",
.id = -1,
}, },
.sources = &clk_src_mout_hpll, .sources = &clk_src_mout_hpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
static struct clksrc_clk clk_div_apll = { static struct clksrc_clk clk_div_apll = {
.clk = { .clk = {
.name = "div_apll", .name = "div_apll",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
static struct clksrc_clk clk_div_arm = { static struct clksrc_clk clk_div_arm = {
.clk = { .clk = {
.name = "div_arm", .name = "div_arm",
.id = -1,
.parent = &clk_div_apll.clk, .parent = &clk_div_apll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
static struct clksrc_clk clk_div_d0_bus = { static struct clksrc_clk clk_div_d0_bus = {
.clk = { .clk = {
.name = "div_d0_bus", .name = "div_d0_bus",
.id = -1,
.parent = &clk_div_arm.clk, .parent = &clk_div_arm.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
static struct clksrc_clk clk_div_pclkd0 = { static struct clksrc_clk clk_div_pclkd0 = {
.clk = { .clk = {
.name = "div_pclkd0", .name = "div_pclkd0",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
static struct clksrc_clk clk_div_secss = { static struct clksrc_clk clk_div_secss = {
.clk = { .clk = {
.name = "div_secss", .name = "div_secss",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
static struct clksrc_clk clk_div_apll2 = { static struct clksrc_clk clk_div_apll2 = {
.clk = { .clk = {
.name = "div_apll2", .name = "div_apll2",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
static struct clksrc_clk clk_mout_am = { static struct clksrc_clk clk_mout_am = {
.clk = { .clk = {
.name = "mout_am", .name = "mout_am",
.id = -1,
}, },
.sources = &clk_src_mout_am, .sources = &clk_src_mout_am,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
static struct clksrc_clk clk_div_d1_bus = { static struct clksrc_clk clk_div_d1_bus = {
.clk = { .clk = {
.name = "div_d1_bus", .name = "div_d1_bus",
.id = -1,
.parent = &clk_mout_am.clk, .parent = &clk_mout_am.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
static struct clksrc_clk clk_div_mpll2 = { static struct clksrc_clk clk_div_mpll2 = {
.clk = { .clk = {
.name = "div_mpll2", .name = "div_mpll2",
.id = -1,
.parent = &clk_mout_am.clk, .parent = &clk_mout_am.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
static struct clksrc_clk clk_div_mpll = { static struct clksrc_clk clk_div_mpll = {
.clk = { .clk = {
.name = "div_mpll", .name = "div_mpll",
.id = -1,
.parent = &clk_mout_am.clk, .parent = &clk_mout_am.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
static struct clksrc_clk clk_mout_onenand = { static struct clksrc_clk clk_mout_onenand = {
.clk = { .clk = {
.name = "mout_onenand", .name = "mout_onenand",
.id = -1,
}, },
.sources = &clk_src_mout_onenand, .sources = &clk_src_mout_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
static struct clksrc_clk clk_div_onenand = { static struct clksrc_clk clk_div_onenand = {
.clk = { .clk = {
.name = "div_onenand", .name = "div_onenand",
.id = -1,
.parent = &clk_mout_onenand.clk, .parent = &clk_mout_onenand.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
static struct clksrc_clk clk_div_pclkd1 = { static struct clksrc_clk clk_div_pclkd1 = {
.clk = { .clk = {
.name = "div_pclkd1", .name = "div_pclkd1",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
static struct clksrc_clk clk_div_cam = { static struct clksrc_clk clk_div_cam = {
.clk = { .clk = {
.name = "div_cam", .name = "div_cam",
.id = -1,
.parent = &clk_div_mpll2.clk, .parent = &clk_div_mpll2.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
static struct clksrc_clk clk_div_hdmi = { static struct clksrc_clk clk_div_hdmi = {
.clk = { .clk = {
.name = "div_hdmi", .name = "div_hdmi",
.id = -1,
.parent = &clk_mout_hpll.clk, .parent = &clk_mout_hpll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "cssys", .name = "cssys",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "secss", .name = "secss",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "g2d", .name = "g2d",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "mdma", .name = "mdma",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "cfcon", .name = "cfcon",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "nfcon", .name = "nfcon",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "onenandc", .name = "onenandc",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "sdm", .name = "sdm",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl, .enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "seckey", .name = "seckey",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl, .enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "modemif", .name = "modemif",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "usbhost", .name = "usbhost",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 1, .devname = "s3c-pl330.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 0, .devname = "s3c-pl330.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "rotator", .name = "rotator",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 0, .devname = "s5p-fimc.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 1, .devname = "s5p-fimc.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 2, .devname = "s5p-fimc.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "jpeg", .name = "jpeg",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "mipi-dsim", .name = "mipi-dsim",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "mipi-csis", .name = "mipi-csis",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl, .enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "g3d", .name = "g3d",
.id = 0,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl, .enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "tv", .name = "tv",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl, .enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "vp", .name = "vp",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl, .enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "mixer", .name = "mixer",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl, .enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "hdmi", .name = "hdmi",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl, .enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "mfc", .name = "mfc",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl, .enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "apc", .name = "apc",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "iec", .name = "iec",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "systimer", .name = "systimer",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "spi", .name = "spi",
.id = 2, .devname = "s3c64xx-spi.2",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "irda", .name = "irda",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "ccan", .name = "ccan",
.id = 0,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "ccan", .name = "ccan",
.id = 1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, { }, {
.name = "hsitx", .name = "hsitx",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "hsirx", .name = "hsirx",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "ac97", .name = "ac97",
.id = -1,
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "pcm", .name = "pcm",
.id = 0, .devname = "samsung-pcm.0",
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "pcm", .name = "pcm",
.id = 1, .devname = "samsung-pcm.1",
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "spdif", .name = "spdif",
.id = -1,
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "keypad", .name = "keypad",
.id = -1,
.parent = &clk_div_pclkd1.clk, .parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl, .enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, { }, {
.name = "spi_48m", .name = "spi_48m",
.id = 2, .devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, { }, {
.name = "mmc_48m", .name = "mmc_48m",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_mout_48m.clk, .parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
static struct clk clk_vclk54m = { static struct clk clk_vclk54m = {
.name = "vclk_54m", .name = "vclk_54m",
.id = -1,
.rate = 54000000, .rate = 54000000,
}; };
static struct clk clk_i2scdclk0 = { static struct clk clk_i2scdclk0 = {
.name = "i2s_cdclk0", .name = "i2s_cdclk0",
.id = -1,
}; };
static struct clk clk_i2scdclk1 = { static struct clk clk_i2scdclk1 = {
.name = "i2s_cdclk1", .name = "i2s_cdclk1",
.id = -1,
}; };
static struct clk clk_i2scdclk2 = { static struct clk clk_i2scdclk2 = {
.name = "i2s_cdclk2", .name = "i2s_cdclk2",
.id = -1,
}; };
static struct clk clk_pcmcdclk0 = { static struct clk clk_pcmcdclk0 = {
.name = "pcm_cdclk0", .name = "pcm_cdclk0",
.id = -1,
}; };
static struct clk clk_pcmcdclk1 = { static struct clk clk_pcmcdclk1 = {
.name = "pcm_cdclk1", .name = "pcm_cdclk1",
.id = -1,
}; };
static struct clk *clk_src_group1_list[] = { static struct clk *clk_src_group1_list[] = {
@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
static struct clksrc_clk clk_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 0, .devname = "samsung-pcm.0",
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
}, },
@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
static struct clksrc_clk clk_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 1, .devname = "samsung-pcm.1",
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
}, },
@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
static struct clksrc_clk clk_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 2, .devname = "samsung-pcm.2",
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
}, },
@ -1014,7 +948,6 @@ static struct clk_ops s5pc100_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = { static struct clksrc_clk clk_sclk_spdif = {
.clk = { .clk = {
.name = "sclk_spdif", .name = "sclk_spdif",
.id = -1,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
.ops = &s5pc100_sclk_spdif_ops, .ops = &s5pc100_sclk_spdif_ops,
@ -1027,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1038,7 +971,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1049,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 2, .devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1060,7 +993,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = -1,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1071,7 +1003,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mixer", .name = "sclk_mixer",
.id = -1,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1081,7 +1012,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_lcd", .name = "sclk_lcd",
.id = -1,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1092,7 +1022,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 0, .devname = "s5p-fimc.0",
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1103,7 +1033,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 1, .devname = "s5p-fimc.1",
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1114,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 2, .devname = "s5p-fimc.2",
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1125,7 +1055,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1136,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1147,7 +1077,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
.enable = s5pc100_sclk1_ctrl, .enable = s5pc100_sclk1_ctrl,
@ -1158,7 +1088,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_irda", .name = "sclk_irda",
.id = 2,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1169,7 +1098,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_irda", .name = "sclk_irda",
.id = -1,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1180,7 +1108,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwi", .name = "sclk_pwi",
.id = -1,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1191,7 +1118,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_uhost", .name = "sclk_uhost",
.id = -1,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
.enable = s5pc100_sclk0_ctrl, .enable = s5pc100_sclk0_ctrl,
@ -1291,79 +1217,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "tzic", .name = "tzic",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "intc", .name = "intc",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl, .enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "ebi", .name = "ebi",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "intmem", .name = "intmem",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "sromc", .name = "sromc",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "dmc", .name = "dmc",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "chipid", .name = "chipid",
.id = -1,
.parent = &clk_div_d0_bus.clk, .parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl, .enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c6400-uart.0",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c6400-uart.1",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c6400-uart.2",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c6400-uart.3",
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl, .enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_div_d1_bus.clk, .parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl, .enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),

7
arch/arm/mach-s5pc100/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

130
arch/arm/mach-s5pv210/clock.c
View File

@ -36,7 +36,6 @@ static unsigned long xtal;
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.sources = &clk_src_apll, .sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.sources = &clk_src_epll, .sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_armclk = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
}, },
.sources = &clkset_armclk, .sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_hclk_msys = { static struct clksrc_clk clk_hclk_msys = {
.clk = { .clk = {
.name = "hclk_msys", .name = "hclk_msys",
.id = -1,
.parent = &clk_armclk.clk, .parent = &clk_armclk.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
static struct clksrc_clk clk_pclk_msys = { static struct clksrc_clk clk_pclk_msys = {
.clk = { .clk = {
.name = "pclk_msys", .name = "pclk_msys",
.id = -1,
.parent = &clk_hclk_msys.clk, .parent = &clk_hclk_msys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
static struct clksrc_clk clk_sclk_a2m = { static struct clksrc_clk clk_sclk_a2m = {
.clk = { .clk = {
.name = "sclk_a2m", .name = "sclk_a2m",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
static struct clksrc_clk clk_hclk_dsys = { static struct clksrc_clk clk_hclk_dsys = {
.clk = { .clk = {
.name = "hclk_dsys", .name = "hclk_dsys",
.id = -1,
}, },
.sources = &clkset_hclk_sys, .sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
static struct clksrc_clk clk_pclk_dsys = { static struct clksrc_clk clk_pclk_dsys = {
.clk = { .clk = {
.name = "pclk_dsys", .name = "pclk_dsys",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
static struct clksrc_clk clk_hclk_psys = { static struct clksrc_clk clk_hclk_psys = {
.clk = { .clk = {
.name = "hclk_psys", .name = "hclk_psys",
.id = -1,
}, },
.sources = &clkset_hclk_sys, .sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
static struct clksrc_clk clk_pclk_psys = { static struct clksrc_clk clk_pclk_psys = {
.clk = { .clk = {
.name = "pclk_psys", .name = "pclk_psys",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
static struct clk clk_sclk_hdmi27m = { static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m", .name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_hdmiphy = { static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy", .name = "sclk_hdmiphy",
.id = -1,
}; };
static struct clk clk_sclk_usbphy0 = { static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0", .name = "sclk_usbphy0",
.id = -1,
}; };
static struct clk clk_sclk_usbphy1 = { static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1", .name = "sclk_usbphy1",
.id = -1,
}; };
static struct clk clk_pcmcdclk0 = { static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk clk_pcmcdclk1 = { static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk clk_pcmcdclk2 = { static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk *clkset_vpllsrc_list[] = { static struct clk *clkset_vpllsrc_list[] = {
@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = { static struct clksrc_clk clk_vpllsrc = {
.clk = { .clk = {
.name = "vpll_src", .name = "vpll_src",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, },
@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = {
.clk = { .clk = {
.name = "sclk_vpll", .name = "sclk_vpll",
.id = -1,
}, },
.sources = &clkset_sclk_vpll, .sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
static struct clksrc_clk clk_mout_dmc0 = { static struct clksrc_clk clk_mout_dmc0 = {
.clk = { .clk = {
.name = "mout_dmc0", .name = "mout_dmc0",
.id = -1,
}, },
.sources = &clkset_moutdmc0src, .sources = &clkset_moutdmc0src,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
static struct clksrc_clk clk_sclk_dmc0 = { static struct clksrc_clk clk_sclk_dmc0 = {
.clk = { .clk = {
.name = "sclk_dmc0", .name = "sclk_dmc0",
.id = -1,
.parent = &clk_mout_dmc0.clk, .parent = &clk_mout_dmc0.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "pdma", .name = "pdma",
.id = 0, .devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 1, .devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "rot", .name = "rot",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29), .ctrlbit = (1<<29),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 0, .devname = "s5pv210-fimc.0",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 1, .devname = "s5pv210-fimc.1",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 2, .devname = "s5pv210-fimc.2",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17), .ctrlbit = (1<<17),
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0), .ctrlbit = (1<<0),
}, { }, {
.name = "cfcon", .name = "cfcon",
.id = 0,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25), .ctrlbit = (1<<25),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17), .ctrlbit = (1<<17),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18), .ctrlbit = (1<<18),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19), .ctrlbit = (1<<19),
}, { }, {
.name = "systimer", .name = "systimer",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22), .ctrlbit = (1<<22),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15), .ctrlbit = (1<<15),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7), .ctrlbit = (1<<7),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 2, .devname = "s3c2440-i2c.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9), .ctrlbit = (1<<9),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12), .ctrlbit = (1<<12),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13), .ctrlbit = (1<<13),
}, { }, {
.name = "spi", .name = "spi",
.id = 2, .devname = "s3c64xx-spi.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14), .ctrlbit = (1<<14),
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23), .ctrlbit = (1<<23),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24), .ctrlbit = (1<<24),
}, { }, {
.name = "keypad", .name = "keypad",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21), .ctrlbit = (1<<21),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4), .ctrlbit = (1<<4),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "spdif", .name = "spdif",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "hclk_imem", .name = "hclk_imem",
.id = -1,
.parent = &clk_hclk_msys.clk, .parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops, .ops = &clk_hclk_imem_ops,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s5pv210-uart.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s5pv210-uart.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s5pv210-uart.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s5pv210-uart.3",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "sromc", .name = "sromc",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
static struct clksrc_clk clk_sclk_dac = { static struct clksrc_clk clk_sclk_dac = {
.clk = { .clk = {
.name = "sclk_dac", .name = "sclk_dac",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, },
@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
static struct clksrc_clk clk_sclk_pixel = { static struct clksrc_clk clk_sclk_pixel = {
.clk = { .clk = {
.name = "sclk_pixel", .name = "sclk_pixel",
.id = -1,
.parent = &clk_sclk_vpll.clk, .parent = &clk_sclk_vpll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
static struct clksrc_clk clk_sclk_hdmi = { static struct clksrc_clk clk_sclk_hdmi = {
.clk = { .clk = {
.name = "sclk_hdmi", .name = "sclk_hdmi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 0, .devname = "soc-audio.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 1, .devname = "soc-audio.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, },
@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 2, .devname = "soc-audio.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, },
@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = { static struct clksrc_clk clk_sclk_spdif = {
.clk = { .clk = {
.name = "sclk_spdif", .name = "sclk_spdif",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
.ops = &s5pv210_sclk_spdif_ops, .ops = &s5pv210_sclk_spdif_ops,
@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "sclk_dmc", .name = "sclk_dmc",
.id = -1,
}, },
.sources = &clkset_group1, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_onenand", .name = "sclk_onenand",
.id = -1,
}, },
.sources = &clkset_sclk_onenand, .sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 0, .devname = "s5pv210-uart.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 1, .devname = "s5pv210-uart.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, },
@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 2, .devname = "s5pv210-uart.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
}, },
@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 3, .devname = "s5pv210-uart.3",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, },
@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mixer", .name = "sclk_mixer",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, },
@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 0, .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, },
@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 1, .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, },
@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 2, .devname = "s5pv210-fimc.2",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 0, .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, },
@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 1, .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, },
@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, },
@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, },
@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 3, .devname = "s3c-sdhci.3",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, },
@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mfc", .name = "sclk_mfc",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_g2d", .name = "sclk_g2d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_g3d", .name = "sclk_g3d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, },
@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, },
@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwi", .name = "sclk_pwi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29), .ctrlbit = (1 << 29),
}, },
@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwm", .name = "sclk_pwm",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, },

7
arch/arm/mach-s5pv210/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

4
arch/arm/plat-s3c24xx/clock-dclk.c
View File

@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
struct clk s3c24xx_dclk0 = { struct clk s3c24xx_dclk0 = {
.name = "dclk0", .name = "dclk0",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN, .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable, .enable = s3c24xx_dclk_enable,
.ops = &dclk_ops, .ops = &dclk_ops,
@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = { struct clk s3c24xx_dclk1 = {
.name = "dclk1", .name = "dclk1",
.id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN, .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable, .enable = s3c24xx_dclk_enable,
.ops = &dclk_ops, .ops = &dclk_ops,
@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
struct clk s3c24xx_clkout0 = { struct clk s3c24xx_clkout0 = {
.name = "clkout0", .name = "clkout0",
.id = -1,
.ops = &clkout_ops, .ops = &clkout_ops,
}; };
struct clk s3c24xx_clkout1 = { struct clk s3c24xx_clkout1 = {
.name = "clkout1", .name = "clkout1",
.id = -1,
.ops = &clkout_ops, .ops = &clkout_ops,
}; };

7
arch/arm/plat-s3c24xx/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do {} while (0)
#endif

21
arch/arm/plat-s3c24xx/s3c2410-clock.c
View File

@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_NAND, .ctrlbit = S3C2410_CLKCON_NAND,
}, { }, {
.name = "sdi", .name = "sdi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SDI, .ctrlbit = S3C2410_CLKCON_SDI,
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_ADC, .ctrlbit = S3C2410_CLKCON_ADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIC, .ctrlbit = S3C2410_CLKCON_IIC,
}, { }, {
.name = "iis", .name = "iis",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIS, .ctrlbit = S3C2410_CLKCON_IIS,
}, { }, {
.name = "spi", .name = "spi",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SPI, .ctrlbit = S3C2410_CLKCON_SPI,
@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC, .ctrlbit = S3C2410_CLKCON_LCDC,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO, .ctrlbit = S3C2410_CLKCON_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH, .ctrlbit = S3C2410_CLKCON_USBH,
}, { }, {
.name = "usb-device", .name = "usb-device",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD, .ctrlbit = S3C2410_CLKCON_USBD,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT, .ctrlbit = S3C2410_CLKCON_PWMT,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c2410-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0, .ctrlbit = S3C2410_CLKCON_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c2410-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1, .ctrlbit = S3C2410_CLKCON_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c2410-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2, .ctrlbit = S3C2410_CLKCON_UART2,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2410_clkcon_enable, .enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC, .ctrlbit = S3C2410_CLKCON_RTC,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = 0, .ctrlbit = 0,
}, { }, {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
}, { }, {
.name = "usb-bus-gadget", .name = "usb-bus-gadget",
.id = -1,
.parent = &clk_usb_bus, .parent = &clk_usb_bus,
}, },
}; };

39
arch/arm/plat-s3c24xx/s3c2443-clock.c
View File

@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
struct clk clk_mpllref = { struct clk clk_mpllref = {
.name = "mpllref", .name = "mpllref",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}; };
static struct clk *clk_epllref_sources[] = { static struct clk *clk_epllref_sources[] = {
@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
struct clksrc_clk clk_epllref = { struct clksrc_clk clk_epllref = {
.clk = { .clk = {
.name = "epllref", .name = "epllref",
.id = -1,
}, },
.sources = &(struct clksrc_sources) { .sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources, .sources = clk_epllref_sources,
@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
.clk = { .clk = {
.name = "esysclk", .name = "esysclk",
.parent = &clk_epll, .parent = &clk_epll,
.id = -1,
}, },
.sources = &(struct clksrc_sources) { .sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources, .sources = clk_sysclk_sources,
@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
static struct clk clk_mdivclk = { static struct clk clk_mdivclk = {
.name = "mdivclk", .name = "mdivclk",
.parent = &clk_mpllref, .parent = &clk_mpllref,
.id = -1,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk, .get_rate = s3c2443_getrate_mdivclk,
}, },
@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
.clk = { .clk = {
.name = "msysclk", .name = "msysclk",
.parent = &clk_xtal, .parent = &clk_xtal,
.id = -1,
}, },
.sources = &(struct clksrc_sources) { .sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources, .sources = clk_msysclk_sources,
@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
static struct clk clk_prediv = { static struct clk clk_prediv = {
.name = "prediv", .name = "prediv",
.id = -1,
.parent = &clk_msysclk.clk, .parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) { .ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate, .get_rate = s3c2443_prediv_getrate,
@ -174,7 +168,6 @@ static struct clk clk_prediv = {
static struct clksrc_clk clk_usb_bus_host = { static struct clksrc_clk clk_usb_bus_host = {
.clk = { .clk = {
.name = "usb-bus-host-parent", .name = "usb-bus-host-parent",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST, .ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* ART baud-rate clock sourced from esysclk via a divisor */ /* ART baud-rate clock sourced from esysclk via a divisor */
.clk = { .clk = {
.name = "uartclk", .name = "uartclk",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
}, },
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* camera interface bus-clock, divided down from esysclk */ /* camera interface bus-clock, divided down from esysclk */
.clk = { .clk = {
.name = "camif-upll", /* same as 2440 name */ .name = "camif-upll", /* same as 2440 name */
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK, .ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
}, { }, {
.clk = { .clk = {
.name = "display-if", .name = "display-if",
.id = -1,
.parent = &clk_esysclk.clk, .parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK, .ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s, .enable = s3c2443_clkcon_enable_s,
@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC, .ctrlbit = S3C2443_PCLKCON_ADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC, .ctrlbit = S3C2443_PCLKCON_IIC,
@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "dma", .name = "dma",
.id = 0,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0, .ctrlbit = S3C2443_HCLKCON_DMA0,
}, { }, {
.name = "dma", .name = "dma",
.id = 1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1, .ctrlbit = S3C2443_HCLKCON_DMA1,
}, { }, {
.name = "dma", .name = "dma",
.id = 2,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2, .ctrlbit = S3C2443_HCLKCON_DMA2,
}, { }, {
.name = "dma", .name = "dma",
.id = 3,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3, .ctrlbit = S3C2443_HCLKCON_DMA3,
}, { }, {
.name = "dma", .name = "dma",
.id = 4,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4, .ctrlbit = S3C2443_HCLKCON_DMA4,
}, { }, {
.name = "dma", .name = "dma",
.id = 5,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5, .ctrlbit = S3C2443_HCLKCON_DMA5,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC, .ctrlbit = S3C2443_HCLKCON_HSMMC,
}, { }, {
.name = "gpio", .name = "gpio",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO, .ctrlbit = S3C2443_PCLKCON_GPIO,
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH, .ctrlbit = S3C2443_HCLKCON_USBH,
}, { }, {
.name = "usb-device", .name = "usb-device",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD, .ctrlbit = S3C2443_HCLKCON_USBD,
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC, .ctrlbit = S3C2443_HCLKCON_LCDC,
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT, .ctrlbit = S3C2443_PCLKCON_PWMT,
}, { }, {
.name = "cfc", .name = "cfc",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC, .ctrlbit = S3C2443_HCLKCON_CFC,
}, { }, {
.name = "ssmc", .name = "ssmc",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c2443_clkcon_enable_h, .enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC, .ctrlbit = S3C2443_HCLKCON_SSMC,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s3c2440-uart.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0, .ctrlbit = S3C2443_PCLKCON_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s3c2440-uart.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1, .ctrlbit = S3C2443_PCLKCON_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s3c2440-uart.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2, .ctrlbit = S3C2443_PCLKCON_UART2,
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s3c2440-uart.3",
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3, .ctrlbit = S3C2443_PCLKCON_UART3,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC, .ctrlbit = S3C2443_PCLKCON_RTC,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT, .ctrlbit = S3C2443_PCLKCON_WDT,
}, { }, {
.name = "ac97", .name = "ac97",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97, .ctrlbit = S3C2443_PCLKCON_AC97,
}, { }, {
.name = "nand", .name = "nand",
.id = -1,
.parent = &clk_h, .parent = &clk_h,
}, { }, {
.name = "usb-bus-host", .name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus_host.clk, .parent = &clk_usb_bus_host.clk,
} }
}; };

9
arch/arm/plat-s5p/s5p-time.c
View File

@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void)
unsigned long event_id = timer_source.event_id; unsigned long event_id = timer_source.event_id;
unsigned long source_id = timer_source.source_id; unsigned long source_id = timer_source.source_id;
char devname[15];
timerclk = clk_get(NULL, "timers"); timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk)) if (IS_ERR(timerclk))
@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void)
clk_enable(timerclk); clk_enable(timerclk);
sprintf(devname, "s3c24xx-pwm.%lu", event_id);
s3c_device_timer[event_id].id = event_id;
s3c_device_timer[event_id].dev.init_name = devname;
tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin"); tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
if (IS_ERR(tin_event)) if (IS_ERR(tin_event))
panic("failed to get pwm-tin clock for event timer"); panic("failed to get pwm-tin clock for event timer");
@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void)
clk_enable(tin_event); clk_enable(tin_event);
sprintf(devname, "s3c24xx-pwm.%lu", source_id);
s3c_device_timer[source_id].id = source_id;
s3c_device_timer[source_id].dev.init_name = devname;
tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin"); tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
if (IS_ERR(tin_source)) if (IS_ERR(tin_source))
panic("failed to get pwm-tin clock for source timer"); panic("failed to get pwm-tin clock for source timer");

98
arch/arm/plat-samsung/clock.c
View File

@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0; return 0;
} }
static int dev_is_s3c_uart(struct device *dev)
{
struct platform_device **pdev = s3c24xx_uart_devs;
int i;
for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
if (*pdev && dev == &(*pdev)->dev)
return 1;
return 0;
}
/*
* Serial drivers call get_clock() very early, before platform bus
* has been set up, this requires a special check to let them get
* a proper clock
*/
static int dev_is_platform_device(struct device *dev)
{
return dev->bus == &platform_bus_type ||
(dev->bus == NULL && dev_is_s3c_uart(dev));
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p;
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || !dev_is_platform_device(dev))
idno = -1;
else
idno = to_platform_device(dev)->id;
spin_lock(&clocks_lock);
list_for_each_entry(p, &clocks, list) {
if (p->id == idno &&
strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
/* check for the case where a device was supplied, but the
* clock that was being searched for is not device specific */
if (IS_ERR(clk)) {
list_for_each_entry(p, &clocks, list) {
if (p->id == -1 && strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
}
spin_unlock(&clocks_lock);
return clk;
}
void clk_put(struct clk *clk)
{
module_put(clk->owner);
}
int clk_enable(struct clk *clk) int clk_enable(struct clk *clk)
{ {
if (IS_ERR(clk) || clk == NULL) if (IS_ERR(clk) || clk == NULL)
@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return ret; return ret;
} }
EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable); EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable); EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate); EXPORT_SYMBOL(clk_get_rate);
@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
struct clk clk_xtal = { struct clk clk_xtal = {
.name = "xtal", .name = "xtal",
.id = -1,
.rate = 0, .rate = 0,
.parent = NULL, .parent = NULL,
.ctrlbit = 0, .ctrlbit = 0,
@ -273,30 +202,25 @@ struct clk clk_xtal = {
struct clk clk_ext = { struct clk clk_ext = {
.name = "ext", .name = "ext",
.id = -1,
}; };
struct clk clk_epll = { struct clk clk_epll = {
.name = "epll", .name = "epll",
.id = -1,
}; };
struct clk clk_mpll = { struct clk clk_mpll = {
.name = "mpll", .name = "mpll",
.id = -1,
.ops = &clk_ops_def_setrate, .ops = &clk_ops_def_setrate,
}; };
struct clk clk_upll = { struct clk clk_upll = {
.name = "upll", .name = "upll",
.id = -1,
.parent = NULL, .parent = NULL,
.ctrlbit = 0, .ctrlbit = 0,
}; };
struct clk clk_f = { struct clk clk_f = {
.name = "fclk", .name = "fclk",
.id = -1,
.rate = 0, .rate = 0,
.parent = &clk_mpll, .parent = &clk_mpll,
.ctrlbit = 0, .ctrlbit = 0,
@ -304,7 +228,6 @@ struct clk clk_f = {
struct clk clk_h = { struct clk clk_h = {
.name = "hclk", .name = "hclk",
.id = -1,
.rate = 0, .rate = 0,
.parent = NULL, .parent = NULL,
.ctrlbit = 0, .ctrlbit = 0,
@ -313,7 +236,6 @@ struct clk clk_h = {
struct clk clk_p = { struct clk clk_p = {
.name = "pclk", .name = "pclk",
.id = -1,
.rate = 0, .rate = 0,
.parent = NULL, .parent = NULL,
.ctrlbit = 0, .ctrlbit = 0,
@ -322,7 +244,6 @@ struct clk clk_p = {
struct clk clk_usb_bus = { struct clk clk_usb_bus = {
.name = "usb-bus", .name = "usb-bus",
.id = -1,
.rate = 0, .rate = 0,
.parent = &clk_upll, .parent = &clk_upll,
}; };
@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
struct clk s3c24xx_uclk = { struct clk s3c24xx_uclk = {
.name = "uclk", .name = "uclk",
.id = -1,
}; };
/* initialise the clock system */ /* initialise the clock system */
@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
if (clk->enable == NULL) if (clk->enable == NULL)
clk->enable = clk_null_enable; clk->enable = clk_null_enable;
/* add to the list of available clocks */ /* fill up the clk_lookup structure and register it*/
clk->lookup.dev_id = clk->devname;
/* Quick check to see if this clock has already been registered. */ clk->lookup.con_id = clk->name;
BUG_ON(clk->list.prev != clk->list.next); clk->lookup.clk = clk;
clkdev_add(&clk->lookup);
spin_lock(&clocks_lock);
list_add(&clk->list, &clocks);
spin_unlock(&clocks_lock);
return 0; return 0;
} }
@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
char s[255]; char s[255];
char *p = s; char *p = s;
p += sprintf(p, "%s", c->name); p += sprintf(p, "%s", c->devname);
if (c->id >= 0)
sprintf(p, ":%d", c->id);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
if (!d) if (!d)

3
arch/arm/plat-samsung/include/plat/clock.h
View File

@ -10,6 +10,7 @@
*/ */
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/clkdev.h>
struct clk; struct clk;
@ -40,6 +41,7 @@ struct clk {
struct module *owner; struct module *owner;
struct clk *parent; struct clk *parent;
const char *name; const char *name;
const char *devname;
int id; int id;
int usage; int usage;
unsigned long rate; unsigned long rate;
@ -47,6 +49,7 @@ struct clk {
struct clk_ops *ops; struct clk_ops *ops;
int (*enable)(struct clk *, int enable); int (*enable)(struct clk *, int enable);
struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */ struct dentry *dent; /* For visible tree hierarchy */
#endif #endif

10
arch/arm/plat-samsung/pwm-clock.c
View File

@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = { [0] = {
.clk = { .clk = {
.name = "pwm-tdiv", .name = "pwm-tdiv",
.devname = "s3c24xx-pwm.0",
.ops = &clk_tdiv_ops, .ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0], .parent = &clk_timer_scaler[0],
}, },
@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[1] = { [1] = {
.clk = { .clk = {
.name = "pwm-tdiv", .name = "pwm-tdiv",
.devname = "s3c24xx-pwm.1",
.ops = &clk_tdiv_ops, .ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0], .parent = &clk_timer_scaler[0],
} }
@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[2] = { [2] = {
.clk = { .clk = {
.name = "pwm-tdiv", .name = "pwm-tdiv",
.devname = "s3c24xx-pwm.2",
.ops = &clk_tdiv_ops, .ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1], .parent = &clk_timer_scaler[1],
}, },
@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[3] = { [3] = {
.clk = { .clk = {
.name = "pwm-tdiv", .name = "pwm-tdiv",
.devname = "s3c24xx-pwm.3",
.ops = &clk_tdiv_ops, .ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1], .parent = &clk_timer_scaler[1],
}, },
@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[4] = { [4] = {
.clk = { .clk = {
.name = "pwm-tdiv", .name = "pwm-tdiv",
.devname = "s3c24xx-pwm.4",
.ops = &clk_tdiv_ops, .ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1], .parent = &clk_timer_scaler[1],
}, },
@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
static struct clk clk_tin[] = { static struct clk clk_tin[] = {
[0] = { [0] = {
.name = "pwm-tin", .name = "pwm-tin",
.devname = "s3c24xx-pwm.0",
.id = 0, .id = 0,
.ops = &clk_tin_ops, .ops = &clk_tin_ops,
}, },
[1] = { [1] = {
.name = "pwm-tin", .name = "pwm-tin",
.devname = "s3c24xx-pwm.1",
.id = 1, .id = 1,
.ops = &clk_tin_ops, .ops = &clk_tin_ops,
}, },
[2] = { [2] = {
.name = "pwm-tin", .name = "pwm-tin",
.devname = "s3c24xx-pwm.2",
.id = 2, .id = 2,
.ops = &clk_tin_ops, .ops = &clk_tin_ops,
}, },
[3] = { [3] = {
.name = "pwm-tin", .name = "pwm-tin",
.devname = "s3c24xx-pwm.3",
.id = 3, .id = 3,
.ops = &clk_tin_ops, .ops = &clk_tin_ops,
}, },
[4] = { [4] = {
.name = "pwm-tin", .name = "pwm-tin",
.devname = "s3c24xx-pwm.4",
.id = 4, .id = 4,
.ops = &clk_tin_ops, .ops = &clk_tin_ops,
}, },

2
arch/arm/plat-samsung/time.c
View File

@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
clk_enable(timerclk); clk_enable(timerclk);
if (!use_tclk1_12()) { if (!use_tclk1_12()) {
tmpdev.id = 4;
tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin = clk_get(&tmpdev.dev, "pwm-tin"); tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin)) if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer"); panic("failed to get pwm-tin clock for system timer");

2
drivers/tty/serial/s3c2410.c
View File

@ -96,8 +96,6 @@ static struct platform_driver s3c2410_serial_driver = {
}, },
}; };
s3c24xx_console_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
static int __init s3c2410_serial_init(void) static int __init s3c2410_serial_init(void)
{ {
return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf); return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);

2
drivers/tty/serial/s3c2412.c
View File

@ -130,8 +130,6 @@ static struct platform_driver s3c2412_serial_driver = {
}, },
}; };
s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
static inline int s3c2412_serial_init(void) static inline int s3c2412_serial_init(void)
{ {
return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf); return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);

2
drivers/tty/serial/s3c2440.c
View File

@ -159,8 +159,6 @@ static struct platform_driver s3c2440_serial_driver = {
}, },
}; };
s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
static int __init s3c2440_serial_init(void) static int __init s3c2440_serial_init(void)
{ {
return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf); return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);

2
drivers/tty/serial/s3c6400.c
View File

@ -130,8 +130,6 @@ static struct platform_driver s3c6400_serial_driver = {
}, },
}; };
s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
static int __init s3c6400_serial_init(void) static int __init s3c6400_serial_init(void)
{ {
return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf); return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);

7
drivers/tty/serial/s5pv210.c
View File

@ -135,13 +135,6 @@ static struct platform_driver s5p_serial_driver = {
}, },
}; };
static int __init s5pv210_serial_console_init(void)
{
return s3c24xx_serial_initconsole(&s5p_serial_driver, s5p_uart_inf);
}
console_initcall(s5pv210_serial_console_init);
static int __init s5p_serial_init(void) static int __init s5p_serial_init(void)
{ {
return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf); return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);

9
drivers/tty/serial/samsung.c
View File

@ -1416,10 +1416,8 @@ s3c24xx_serial_console_setup(struct console *co, char *options)
/* is the port configured? */ /* is the port configured? */
if (port->mapbase == 0x0) { if (port->mapbase == 0x0)
co->index = 0; return -ENODEV;
port = &s3c24xx_serial_ports[co->index].port;
}
cons_uart = port; cons_uart = port;
@ -1451,7 +1449,8 @@ static struct console s3c24xx_serial_console = {
.flags = CON_PRINTBUFFER, .flags = CON_PRINTBUFFER,
.index = -1, .index = -1,
.write = s3c24xx_serial_console_write, .write = s3c24xx_serial_console_write,
.setup = s3c24xx_serial_console_setup .setup = s3c24xx_serial_console_setup,
.data = &s3c24xx_uart_drv,
}; };
int s3c24xx_serial_initconsole(struct platform_driver *drv, int s3c24xx_serial_initconsole(struct platform_driver *drv,

19
drivers/tty/serial/samsung.h
View File

@ -79,25 +79,6 @@ extern int s3c24xx_serial_initconsole(struct platform_driver *drv,
extern int s3c24xx_serial_init(struct platform_driver *drv, extern int s3c24xx_serial_init(struct platform_driver *drv,
struct s3c24xx_uart_info *info); struct s3c24xx_uart_info *info);
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
#define s3c24xx_console_init(__drv, __inf) \
static int __init s3c_serial_console_init(void) \
{ \
struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \
int i; \
\
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \
uinfo[i] = __inf; \
return s3c24xx_serial_initconsole(__drv, uinfo); \
} \
\
console_initcall(s3c_serial_console_init)
#else
#define s3c24xx_console_init(drv, inf) extern void no_console(void)
#endif
#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG #ifdef CONFIG_SERIAL_SAMSUNG_DEBUG
extern void printascii(const char *); extern void printascii(const char *);