pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
Certain SoC own multiple register base for accessing each pin groups, it's easy to be done with extend struct mtk_pin_field_calc to support the kind of SoC such as MT8183. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Sean Wang
Linus Walleij
parent
ea051eb384
commit
2bc47dfe4f
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@ -713,25 +713,41 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
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{
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struct resource *res;
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struct mtk_pinctrl *hw;
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int err;
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int err, i;
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hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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hw->soc = soc;
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hw->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "missing IO resource\n");
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return -ENXIO;
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if (!hw->soc->nbase_names) {
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dev_err(&pdev->dev,
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"SoC should be assigned at least one register base\n");
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return -EINVAL;
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}
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hw->dev = &pdev->dev;
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hw->base = devm_ioremap_resource(&pdev->dev, res);
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hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
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sizeof(*hw->base), GFP_KERNEL);
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if (IS_ERR(hw->base))
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return PTR_ERR(hw->base);
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for (i = 0; i < hw->soc->nbase_names; i++) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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hw->soc->base_names[i]);
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if (!res) {
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dev_err(&pdev->dev, "missing IO resource\n");
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return -ENXIO;
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}
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hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(hw->base[i]))
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return PTR_ERR(hw->base[i]);
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}
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hw->nbase = hw->soc->nbase_names;
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/* Setup pins descriptions per SoC types */
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mtk_desc.pins = (const struct pinctrl_pin_desc *)hw->soc->pins;
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mtk_desc.npins = hw->soc->npins;
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@ -768,6 +768,8 @@ static const struct mtk_pin_soc mt7622_data = {
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.gpio_m = 1,
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.eint_m = 1,
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.ies_present = false,
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.base_names = mtk_default_register_base_names,
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.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
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.bias_disable_set = mtk_pinconf_bias_disable_set,
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.bias_disable_get = mtk_pinconf_bias_disable_get,
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.bias_set = mtk_pinconf_bias_set,
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@ -18,15 +18,15 @@
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#define BOND_MSDC0E_CLR 0x1
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#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 15, false)
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#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 16, 0)
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#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 16, 1)
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#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
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@ -1383,6 +1383,8 @@ static struct mtk_pin_soc mt7623_data = {
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.gpio_m = 0,
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.eint_m = 0,
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.ies_present = true,
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.base_names = mtk_default_register_base_names,
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.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
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.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
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.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
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.bias_set = mtk_pinconf_bias_set_rev1,
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@ -1402,9 +1404,9 @@ static void mt7623_bonding_disable(struct platform_device *pdev)
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{
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struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
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mtk_rmw(hw, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
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mtk_rmw(hw, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
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mtk_rmw(hw, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
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mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
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mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
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mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
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}
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static const struct of_device_id mt7623_pctrl_match[] = {
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@ -39,24 +39,24 @@ const struct mtk_drive_desc mtk_drive[] = {
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[DRV_GRP4] = { 2, 16, 2, 1 },
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};
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static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
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static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
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{
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writel_relaxed(val, pctl->base + reg);
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writel_relaxed(val, pctl->base[i] + reg);
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}
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static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
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static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
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{
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return readl_relaxed(pctl->base + reg);
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return readl_relaxed(pctl->base[i] + reg);
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}
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void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
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void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
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{
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u32 val;
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val = mtk_r32(pctl, reg);
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val = mtk_r32(pctl, i, reg);
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val &= ~mask;
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val |= set;
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mtk_w32(pctl, reg, val);
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mtk_w32(pctl, i, reg, val);
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}
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static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
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@ -82,6 +82,12 @@ static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
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return -EINVAL;
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}
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if (c->i_base > hw->nbase - 1) {
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dev_err(hw->dev, "Invalid base is found for pin = %d (%s)\n",
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desc->number, desc->name);
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return -EINVAL;
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}
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/* Calculated bits as the overall offset the pin is located at,
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* if c->fixed is held, that determines the all the pins in the
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* range use the same field with the s_pin.
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@ -92,6 +98,7 @@ static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
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/* Fill pfd from bits. For example 32-bit register applied is assumed
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* when c->sz_reg is equal to 32.
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*/
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pfd->index = c->i_base;
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pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
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pfd->bitpos = bits % c->sz_reg;
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pfd->mask = (1 << c->x_bits) - 1;
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@ -139,10 +146,10 @@ static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
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mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
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mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
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mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
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(value & pf->mask) << pf->bitpos);
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mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
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mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
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(value & pf->mask) >> nbits_l);
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}
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@ -153,8 +160,10 @@ static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
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mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
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l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
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h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
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l = (mtk_r32(hw, pf->index, pf->offset)
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>> pf->bitpos) & (BIT(nbits_l) - 1);
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h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
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& (BIT(nbits_h) - 1);
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*value = (h << nbits_l) | l;
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}
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@ -170,7 +179,7 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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return err;
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if (!pf.next)
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mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
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mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
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(value & pf.mask) << pf.bitpos);
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else
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mtk_hw_write_cross_field(hw, &pf, value);
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@ -189,7 +198,8 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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return err;
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if (!pf.next)
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*value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
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*value = (mtk_r32(hw, pf.index, pf.offset)
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>> pf.bitpos) & pf.mask;
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else
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mtk_hw_read_cross_field(hw, &pf, value);
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@ -18,10 +18,11 @@
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#define EINT_NA -1
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#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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_x_bits, _sz_reg, _fixed) { \
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#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
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_s_bit, _x_bits, _sz_reg, _fixed) { \
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.s_pin = _s_pin, \
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.e_pin = _e_pin, \
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.i_base = _i_base, \
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.s_addr = _s_addr, \
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.x_addrs = _x_addrs, \
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.s_bit = _s_bit, \
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@ -31,11 +32,11 @@
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}
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#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 32, 0)
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#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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_x_bits, 32, 1)
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/* List these attributes which could be modified for the pin */
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@ -73,8 +74,13 @@ enum {
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DRV_GRP_MAX,
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};
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static const char * const mtk_default_register_base_names[] = {
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"base",
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};
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/* struct mtk_pin_field - the structure that holds the information of the field
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* used to describe the attribute for the pin
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* @base: the index pointing to the entry in base address list
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* @offset: the register offset relative to the base address
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* @mask: the mask used to filter out the field from the register
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* @bitpos: the start bit relative to the register
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@ -82,6 +88,7 @@ enum {
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next register
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*/
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struct mtk_pin_field {
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u8 index;
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u32 offset;
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u32 mask;
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u8 bitpos;
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@ -92,6 +99,7 @@ struct mtk_pin_field {
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* the guide used to look up the relevant field
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* @s_pin: the start pin within the range
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* @e_pin: the end pin within the range
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* @i_base: the index pointing to the entry in base address list
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* @s_addr: the start address for the range
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* @x_addrs: the address distance between two consecutive registers
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* within the range
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@ -105,6 +113,7 @@ struct mtk_pin_field {
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struct mtk_pin_field_calc {
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u16 s_pin;
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u16 e_pin;
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u8 i_base;
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u32 s_addr;
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u8 x_addrs;
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u8 s_bit;
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@ -157,6 +166,8 @@ struct mtk_pin_soc {
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u8 gpio_m;
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u8 eint_m;
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bool ies_present;
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const char * const *base_names;
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unsigned int nbase_names;
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/* Specific pinconfig operations */
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int (*bias_disable_set)(struct mtk_pinctrl *hw,
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@ -183,14 +194,15 @@ struct mtk_pin_soc {
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struct mtk_pinctrl {
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struct pinctrl_dev *pctrl;
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void __iomem *base;
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void __iomem **base;
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u8 nbase;
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struct device *dev;
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struct gpio_chip chip;
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const struct mtk_pin_soc *soc;
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struct mtk_eint *eint;
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};
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void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set);
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void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
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int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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int field, int value);
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