soc: qcom: llcc: Add write-cache cacheable support
Newer SoCs with LLCC IP version 2.1.0.0 and later support write sub-cache cacheable feature. Use a separate llcc_slice_config member "write_scid_cacheable_en" to identify this feature and program LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it. Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Tested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/83372c8178f579d055ec58212ce5af5d55abadd4.1643355594.git.quic_saipraka@quicinc.com
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@ -51,10 +51,12 @@
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#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
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#define LLCC_TRP_PCB_ACT 0x21f04
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#define LLCC_TRP_WRSC_EN 0x21f20
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#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
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#define BANK_OFFSET_STRIDE 0x80000
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#define LLCC_VERSION_2_0_0_0 0x02000000
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#define LLCC_VERSION_2_1_0_0 0x02010000
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/**
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* struct llcc_slice_config - Data associated with the llcc slice
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@ -80,6 +82,8 @@
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* collapse.
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* @activate_on_init: Activate the slice immediately after it is programmed
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* @write_scid_en: Bit enables write cache support for a given scid.
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* @write_scid_cacheable_en: Enables write cache cacheable support for a
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* given scid (not supported on v2 or older hardware).
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*/
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struct llcc_slice_config {
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u32 usecase_id;
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@ -95,6 +99,7 @@ struct llcc_slice_config {
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bool retain_on_pc;
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bool activate_on_init;
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bool write_scid_en;
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bool write_scid_cacheable_en;
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};
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struct qcom_llcc_config {
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@ -515,6 +520,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
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return ret;
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}
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if (drv_data->version >= LLCC_VERSION_2_1_0_0) {
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u32 wr_cache_en;
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wr_cache_en = config->write_scid_cacheable_en << config->slice_id;
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ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN,
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BIT(config->slice_id), wr_cache_en);
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if (ret)
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return ret;
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}
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if (config->activate_on_init) {
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desc.slice_id = config->slice_id;
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ret = llcc_slice_activate(&desc);
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