Merge branch 'amd-iommu/pagetable' into amd-iommu/2.6.32
Conflicts: arch/x86/kernel/amd_iommu.c
This commit is contained in:
Joerg Roedel
commit
2b681fafcc
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@ -147,19 +147,25 @@
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#define PAGE_MODE_1_LEVEL 0x01
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#define PAGE_MODE_2_LEVEL 0x02
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#define PAGE_MODE_3_LEVEL 0x03
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#define PAGE_MODE_4_LEVEL 0x04
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#define PAGE_MODE_5_LEVEL 0x05
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#define PAGE_MODE_6_LEVEL 0x06
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#define IOMMU_PDE_NL_0 0x000ULL
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#define IOMMU_PDE_NL_1 0x200ULL
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#define IOMMU_PDE_NL_2 0x400ULL
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#define IOMMU_PDE_NL_3 0x600ULL
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#define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
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#define PM_LEVEL_SIZE(x) (((x) < 6) ? \
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((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
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(0xffffffffffffffffULL))
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#define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
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#define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
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#define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
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IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
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#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
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#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
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#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
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#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
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#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
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#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
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#define PM_MAP_4k 0
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#define PM_ADDR_MASK 0x000ffffffffff000ULL
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#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
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(~((1ULL << (12 + ((lvl) * 9))) - 1)))
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#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
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#define IOMMU_PTE_P (1ULL << 0)
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#define IOMMU_PTE_TV (1ULL << 1)
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@ -168,11 +174,6 @@
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#define IOMMU_PTE_IR (1ULL << 61)
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#define IOMMU_PTE_IW (1ULL << 62)
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#define IOMMU_L1_PDE(address) \
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((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define IOMMU_L2_PDE(address) \
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((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
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#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
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#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
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#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
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@ -230,6 +231,7 @@ struct protection_domain {
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int mode; /* paging mode (0-6 levels) */
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u64 *pt_root; /* page table root pointer */
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unsigned long flags; /* flags to find out type of domain */
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bool updated; /* complete domain flush required */
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unsigned dev_cnt; /* devices assigned to this domain */
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void *priv; /* private data */
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};
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@ -47,7 +47,6 @@ static DEFINE_SPINLOCK(iommu_pd_list_lock);
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*/
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static struct protection_domain *pt_domain;
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#ifdef CONFIG_IOMMU_API
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static struct iommu_ops amd_iommu_ops;
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/*
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@ -60,13 +59,16 @@ struct iommu_cmd {
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static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
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struct unity_map_entry *e);
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static struct dma_ops_domain *find_protection_domain(u16 devid);
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static u64* alloc_pte(struct protection_domain *dom,
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unsigned long address, u64
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**pte_page, gfp_t gfp);
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static u64 *alloc_pte(struct protection_domain *domain,
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unsigned long address, int end_lvl,
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u64 **pte_page, gfp_t gfp);
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static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
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unsigned long start_page,
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unsigned int pages);
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static void reset_iommu_command_buffer(struct amd_iommu *iommu);
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static u64 *fetch_pte(struct protection_domain *domain,
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unsigned long address, int map_size);
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static void update_domain(struct protection_domain *domain);
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#ifdef CONFIG_AMD_IOMMU_STATS
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@ -535,12 +537,15 @@ static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
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}
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}
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void amd_iommu_flush_all_devices(void)
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static void flush_devices_by_domain(struct protection_domain *domain)
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{
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struct amd_iommu *iommu;
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int i;
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for (i = 0; i <= amd_iommu_last_bdf; ++i) {
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if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
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(amd_iommu_pd_table[i] != domain))
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continue;
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iommu = amd_iommu_rlookup_table[i];
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if (!iommu)
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@ -567,6 +572,11 @@ static void reset_iommu_command_buffer(struct amd_iommu *iommu)
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iommu->reset_in_progress = false;
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}
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void amd_iommu_flush_all_devices(void)
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{
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flush_devices_by_domain(NULL);
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}
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/****************************************************************************
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*
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* The functions below are used the create the page table mappings for
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@ -584,18 +594,21 @@ static void reset_iommu_command_buffer(struct amd_iommu *iommu)
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static int iommu_map_page(struct protection_domain *dom,
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unsigned long bus_addr,
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unsigned long phys_addr,
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int prot)
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int prot,
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int map_size)
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{
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u64 __pte, *pte;
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bus_addr = PAGE_ALIGN(bus_addr);
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phys_addr = PAGE_ALIGN(phys_addr);
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/* only support 512GB address spaces for now */
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if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
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BUG_ON(!PM_ALIGNED(map_size, bus_addr));
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BUG_ON(!PM_ALIGNED(map_size, phys_addr));
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if (!(prot & IOMMU_PROT_MASK))
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return -EINVAL;
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pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
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pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
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if (IOMMU_PTE_PRESENT(*pte))
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return -EBUSY;
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@ -608,29 +621,18 @@ static int iommu_map_page(struct protection_domain *dom,
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*pte = __pte;
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update_domain(dom);
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return 0;
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}
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static void iommu_unmap_page(struct protection_domain *dom,
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unsigned long bus_addr)
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unsigned long bus_addr, int map_size)
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{
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u64 *pte;
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u64 *pte = fetch_pte(dom, bus_addr, map_size);
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pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
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if (!IOMMU_PTE_PRESENT(*pte))
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return;
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pte = IOMMU_PTE_PAGE(*pte);
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pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
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if (!IOMMU_PTE_PRESENT(*pte))
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return;
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pte = IOMMU_PTE_PAGE(*pte);
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pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
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*pte = 0;
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if (pte)
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*pte = 0;
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}
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/*
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@ -685,7 +687,8 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
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for (addr = e->address_start; addr < e->address_end;
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addr += PAGE_SIZE) {
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ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
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ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
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PM_MAP_4k);
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if (ret)
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return ret;
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/*
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@ -740,24 +743,29 @@ static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
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* This function checks if there is a PTE for a given dma address. If
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* there is one, it returns the pointer to it.
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*/
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static u64* fetch_pte(struct protection_domain *domain,
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unsigned long address)
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static u64 *fetch_pte(struct protection_domain *domain,
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unsigned long address, int map_size)
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{
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int level;
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u64 *pte;
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pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
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level = domain->mode - 1;
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pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
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if (!IOMMU_PTE_PRESENT(*pte))
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return NULL;
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while (level > map_size) {
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if (!IOMMU_PTE_PRESENT(*pte))
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return NULL;
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pte = IOMMU_PTE_PAGE(*pte);
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pte = &pte[IOMMU_PTE_L1_INDEX(address)];
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level -= 1;
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if (!IOMMU_PTE_PRESENT(*pte))
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return NULL;
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pte = IOMMU_PTE_PAGE(*pte);
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pte = &pte[PM_LEVEL_INDEX(level, address)];
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pte = IOMMU_PTE_PAGE(*pte);
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pte = &pte[IOMMU_PTE_L0_INDEX(address)];
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if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
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pte = NULL;
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break;
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}
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}
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return pte;
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}
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@ -797,7 +805,7 @@ static int alloc_new_range(struct amd_iommu *iommu,
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u64 *pte, *pte_page;
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for (i = 0; i < num_ptes; ++i) {
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pte = alloc_pte(&dma_dom->domain, address,
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pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
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&pte_page, gfp);
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if (!pte)
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goto out_free;
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@ -830,16 +838,20 @@ static int alloc_new_range(struct amd_iommu *iommu,
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for (i = dma_dom->aperture[index]->offset;
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i < dma_dom->aperture_size;
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i += PAGE_SIZE) {
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u64 *pte = fetch_pte(&dma_dom->domain, i);
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u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
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if (!pte || !IOMMU_PTE_PRESENT(*pte))
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continue;
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dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
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}
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update_domain(&dma_dom->domain);
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return 0;
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out_free:
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update_domain(&dma_dom->domain);
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free_page((unsigned long)dma_dom->aperture[index]->bitmap);
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kfree(dma_dom->aperture[index]);
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@ -1079,7 +1091,7 @@ static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
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dma_dom->domain.id = domain_id_alloc();
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if (dma_dom->domain.id == 0)
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goto free_dma_dom;
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dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
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dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
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dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
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dma_dom->domain.flags = PD_DMA_OPS_MASK;
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dma_dom->domain.priv = dma_dom;
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@ -1133,20 +1145,9 @@ static struct protection_domain *domain_for_device(u16 devid)
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return dom;
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}
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/*
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* If a device is not yet associated with a domain, this function does
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* assigns it visible for the hardware
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*/
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static void __attach_device(struct amd_iommu *iommu,
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struct protection_domain *domain,
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u16 devid)
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static void set_dte_entry(u16 devid, struct protection_domain *domain)
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{
|
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u64 pte_root;
|
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|
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/* lock domain */
|
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spin_lock(&domain->lock);
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|
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pte_root = virt_to_phys(domain->pt_root);
|
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u64 pte_root = virt_to_phys(domain->pt_root);
|
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|
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pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
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<< DEV_ENTRY_MODE_SHIFT;
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|
|
@ -1157,6 +1158,21 @@ static void __attach_device(struct amd_iommu *iommu,
|
|||
amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
|
||||
|
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amd_iommu_pd_table[devid] = domain;
|
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}
|
||||
|
||||
/*
|
||||
* If a device is not yet associated with a domain, this function does
|
||||
* assigns it visible for the hardware
|
||||
*/
|
||||
static void __attach_device(struct amd_iommu *iommu,
|
||||
struct protection_domain *domain,
|
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u16 devid)
|
||||
{
|
||||
/* lock domain */
|
||||
spin_lock(&domain->lock);
|
||||
|
||||
/* update DTE entry */
|
||||
set_dte_entry(devid, domain);
|
||||
|
||||
domain->dev_cnt += 1;
|
||||
|
||||
|
|
@ -1164,6 +1180,10 @@ static void __attach_device(struct amd_iommu *iommu,
|
|||
spin_unlock(&domain->lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* If a device is not yet associated with a domain, this function does
|
||||
* assigns it visible for the hardware
|
||||
*/
|
||||
static void attach_device(struct amd_iommu *iommu,
|
||||
struct protection_domain *domain,
|
||||
u16 devid)
|
||||
|
|
@ -1389,40 +1409,92 @@ static int get_device_resources(struct device *dev,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void update_device_table(struct protection_domain *domain)
|
||||
{
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i <= amd_iommu_last_bdf; ++i) {
|
||||
if (amd_iommu_pd_table[i] != domain)
|
||||
continue;
|
||||
write_lock_irqsave(&amd_iommu_devtable_lock, flags);
|
||||
set_dte_entry(i, domain);
|
||||
write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
static void update_domain(struct protection_domain *domain)
|
||||
{
|
||||
if (!domain->updated)
|
||||
return;
|
||||
|
||||
update_device_table(domain);
|
||||
flush_devices_by_domain(domain);
|
||||
iommu_flush_domain(domain->id);
|
||||
|
||||
domain->updated = false;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the pte_page is not yet allocated this function is called
|
||||
* This function is used to add another level to an IO page table. Adding
|
||||
* another level increases the size of the address space by 9 bits to a size up
|
||||
* to 64 bits.
|
||||
*/
|
||||
static u64* alloc_pte(struct protection_domain *dom,
|
||||
unsigned long address, u64 **pte_page, gfp_t gfp)
|
||||
static bool increase_address_space(struct protection_domain *domain,
|
||||
gfp_t gfp)
|
||||
{
|
||||
u64 *pte;
|
||||
|
||||
if (domain->mode == PAGE_MODE_6_LEVEL)
|
||||
/* address space already 64 bit large */
|
||||
return false;
|
||||
|
||||
pte = (void *)get_zeroed_page(gfp);
|
||||
if (!pte)
|
||||
return false;
|
||||
|
||||
*pte = PM_LEVEL_PDE(domain->mode,
|
||||
virt_to_phys(domain->pt_root));
|
||||
domain->pt_root = pte;
|
||||
domain->mode += 1;
|
||||
domain->updated = true;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static u64 *alloc_pte(struct protection_domain *domain,
|
||||
unsigned long address,
|
||||
int end_lvl,
|
||||
u64 **pte_page,
|
||||
gfp_t gfp)
|
||||
{
|
||||
u64 *pte, *page;
|
||||
int level;
|
||||
|
||||
pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
|
||||
while (address > PM_LEVEL_SIZE(domain->mode))
|
||||
increase_address_space(domain, gfp);
|
||||
|
||||
if (!IOMMU_PTE_PRESENT(*pte)) {
|
||||
page = (u64 *)get_zeroed_page(gfp);
|
||||
if (!page)
|
||||
return NULL;
|
||||
*pte = IOMMU_L2_PDE(virt_to_phys(page));
|
||||
level = domain->mode - 1;
|
||||
pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
|
||||
|
||||
while (level > end_lvl) {
|
||||
if (!IOMMU_PTE_PRESENT(*pte)) {
|
||||
page = (u64 *)get_zeroed_page(gfp);
|
||||
if (!page)
|
||||
return NULL;
|
||||
*pte = PM_LEVEL_PDE(level, virt_to_phys(page));
|
||||
}
|
||||
|
||||
level -= 1;
|
||||
|
||||
pte = IOMMU_PTE_PAGE(*pte);
|
||||
|
||||
if (pte_page && level == end_lvl)
|
||||
*pte_page = pte;
|
||||
|
||||
pte = &pte[PM_LEVEL_INDEX(level, address)];
|
||||
}
|
||||
|
||||
pte = IOMMU_PTE_PAGE(*pte);
|
||||
pte = &pte[IOMMU_PTE_L1_INDEX(address)];
|
||||
|
||||
if (!IOMMU_PTE_PRESENT(*pte)) {
|
||||
page = (u64 *)get_zeroed_page(gfp);
|
||||
if (!page)
|
||||
return NULL;
|
||||
*pte = IOMMU_L1_PDE(virt_to_phys(page));
|
||||
}
|
||||
|
||||
pte = IOMMU_PTE_PAGE(*pte);
|
||||
|
||||
if (pte_page)
|
||||
*pte_page = pte;
|
||||
|
||||
pte = &pte[IOMMU_PTE_L0_INDEX(address)];
|
||||
|
||||
return pte;
|
||||
}
|
||||
|
||||
|
|
@ -1441,10 +1513,13 @@ static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
|
|||
|
||||
pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
|
||||
if (!pte) {
|
||||
pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
|
||||
pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
|
||||
GFP_ATOMIC);
|
||||
aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
|
||||
} else
|
||||
pte += IOMMU_PTE_L0_INDEX(address);
|
||||
pte += PM_LEVEL_INDEX(0, address);
|
||||
|
||||
update_domain(&dom->domain);
|
||||
|
||||
return pte;
|
||||
}
|
||||
|
|
@ -1506,7 +1581,7 @@ static void dma_ops_domain_unmap(struct amd_iommu *iommu,
|
|||
if (!pte)
|
||||
return;
|
||||
|
||||
pte += IOMMU_PTE_L0_INDEX(address);
|
||||
pte += PM_LEVEL_INDEX(0, address);
|
||||
|
||||
WARN_ON(!*pte);
|
||||
|
||||
|
|
@ -2240,7 +2315,7 @@ static int amd_iommu_map_range(struct iommu_domain *dom,
|
|||
paddr &= PAGE_MASK;
|
||||
|
||||
for (i = 0; i < npages; ++i) {
|
||||
ret = iommu_map_page(domain, iova, paddr, prot);
|
||||
ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -2261,7 +2336,7 @@ static void amd_iommu_unmap_range(struct iommu_domain *dom,
|
|||
iova &= PAGE_MASK;
|
||||
|
||||
for (i = 0; i < npages; ++i) {
|
||||
iommu_unmap_page(domain, iova);
|
||||
iommu_unmap_page(domain, iova, PM_MAP_4k);
|
||||
iova += PAGE_SIZE;
|
||||
}
|
||||
|
||||
|
|
@ -2276,21 +2351,9 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
|
|||
phys_addr_t paddr;
|
||||
u64 *pte;
|
||||
|
||||
pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
|
||||
pte = fetch_pte(domain, iova, PM_MAP_4k);
|
||||
|
||||
if (!IOMMU_PTE_PRESENT(*pte))
|
||||
return 0;
|
||||
|
||||
pte = IOMMU_PTE_PAGE(*pte);
|
||||
pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
|
||||
|
||||
if (!IOMMU_PTE_PRESENT(*pte))
|
||||
return 0;
|
||||
|
||||
pte = IOMMU_PTE_PAGE(*pte);
|
||||
pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
|
||||
|
||||
if (!IOMMU_PTE_PRESENT(*pte))
|
||||
if (!pte || !IOMMU_PTE_PRESENT(*pte))
|
||||
return 0;
|
||||
|
||||
paddr = *pte & IOMMU_PAGE_MASK;
|
||||
|
|
|
|||
Loading…
Reference in New Issue