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!221 [linux-5.4/next] Add support for Zhaoxin CPUs 

Merge pull request !221 from LeoLiu-oc/linux-5.4-next-01-zhaoxin-support
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刘诗 2024-09-20 08:00:23 +00:00 committed by Gitee
parent b2be5c757d 4513f0a9b1
commit 2b42d3f326
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GPG Key ID: 173E9B9CA92EEF8F
4 changed files with 51 additions and 22 deletions
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2
arch/x86/Kconfig.cpu
View File

@ -382,7 +382,7 @@ config X86_DEBUGCTLMSR
config IA32_FEAT_CTL
def_bool y
depends on CPU_SUP_INTEL
depends on CPU_SUP_INTEL || CPU_SUP_CENTAUR || CPU_SUP_ZHAOXIN
menuconfig PROCESSOR_SELECT
bool "Supported processor vendors" if EXPERT

21
arch/x86/include/asm/cpufeatures.h
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@ -146,8 +146,12 @@
#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
#define X86_FEATURE_SM2 (5*32 + 0) /* sm2 present*/
#define X86_FEATURE_SM2_EN (5*32 + 1) /* sm2 enabled */
#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
#define X86_FEATURE_CCS (5*32 + 4) /* "sm3 sm4" present */
#define X86_FEATURE_CCS_EN (5*32 + 5) /* "sm3_en sm4_en" enabled */
#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
@ -156,6 +160,23 @@
#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
#define X86_FEATURE_ZX_FMA (5*32 + 15) /* FMA supported */
#define X86_FEATURE_PARALLAX (5*32 + 16) /* Adaptive P-state control present */
#define X86_FEATURE_PARALLAX_EN (5*32 + 17) /* Adaptive P-state control enabled */
#define X86_FEATURE_OVERSTRESS (5*32 + 18) /* Overstress Feature for auto overclock present */
#define X86_FEATURE_OVERSTRESS_EN (5*32 + 19) /* Overstress Feature for auto overclock enabled */
#define X86_FEATURE_TM3 (5*32 + 20) /* Thermal Monitor 3 present */
#define X86_FEATURE_TM3_EN (5*32 + 21) /* Thermal Monitor 3 enabled */
#define X86_FEATURE_RNG2 (5*32 + 22) /* 2nd generation of RNG present */
#define X86_FEATURE_RNG2_EN (5*32 + 23) /* 2nd generation of RNG enabled */
#define X86_FEATURE_SEM (5*32 + 24) /* SME feature present */
#define X86_FEATURE_PHE2 (5*32 + 25) /* SHA384 and SHA 512 present */
#define X86_FEATURE_PHE2_EN (5*32 + 26) /* SHA384 and SHA 512 enabled */
#define X86_FEATURE_XMODX (5*32 + 27) /* "rsa" XMODEXP and MONTMUL2 instructions are present */
#define X86_FEATURE_XMODX_EN (5*32 + 28) /* "rsa_en" XMODEXP and MONTMUL2instructions are enabled */
#define X86_FEATURE_VEX (5*32 + 29) /* VEX instructions are present */
#define X86_FEATURE_VEX_EN (5*32 + 30) /* VEX instructions are enabled */
#define X86_FEATURE_STK (5*32 + 31) /* STK are present */
/* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */

39
arch/x86/kernel/cpu/centaur.c
View File

@ -72,7 +72,8 @@ static void init_c3(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
cpu_detect_cache_sizes(c);
if (c->x86 >= 7)
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
}
enum {
@ -98,18 +99,15 @@ enum {
static void early_init_centaur(struct cpuinfo_x86 *c)
{
switch (c->x86) {
#ifdef CONFIG_X86_32
case 5:
/* Emulate MTRRs using Centaur's MCR. */
/* Emulate MTRRs using Centaur's MCR. */
if (c->x86 == 5)
set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
break;
#endif
case 6:
if (c->x86_model >= 0xf)
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
break;
}
if ((c->x86 == 6 && c->x86_model >= 0xf) ||
(c->x86 >= 7))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
@ -117,6 +115,9 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
if (detect_extended_topology_early(c) < 0)
detect_ht_early(c);
}
static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
@ -160,11 +161,14 @@ static void init_centaur(struct cpuinfo_x86 *c)
clear_cpu_cap(c, 0*32+31);
#endif
early_init_centaur(c);
detect_extended_topology(c);
init_intel_cacheinfo(c);
detect_num_cpu_cores(c);
if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
detect_num_cpu_cores(c);
#ifdef CONFIG_X86_32
detect_ht(c);
#endif
}
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);
@ -178,9 +182,8 @@ static void init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
}
switch (c->x86) {
#ifdef CONFIG_X86_32
case 5:
if (c->x86 == 5) {
switch (c->x86_model) {
case 4:
name = "C6";
@ -240,16 +243,16 @@ static void init_centaur(struct cpuinfo_x86 *c)
c->x86_cache_size = (cc>>24)+(dd>>24);
}
sprintf(c->x86_model_id, "WinChip %s", name);
break;
#endif
case 6:
init_c3(c);
break;
}
#endif
if (c->x86 == 6 || c->x86 >= 7)
init_c3(c);
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif
init_ia32_feat_ctl(c);
if (cpu_has(c, X86_FEATURE_VMX))
centaur_detect_vmx_virtcap(c);
}

11
arch/x86/kernel/cpu/zhaoxin.c
View File

@ -58,8 +58,6 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
if (c->x86 >= 0x6)
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
cpu_detect_cache_sizes(c);
}
static void early_init_zhaoxin(struct cpuinfo_x86 *c)
@ -87,6 +85,8 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
}
if (detect_extended_topology_early(c) < 0)
detect_ht_early(c);
}
static void zhaoxin_detect_vmx_virtcap(struct cpuinfo_x86 *c)
@ -117,11 +117,14 @@ static void zhaoxin_detect_vmx_virtcap(struct cpuinfo_x86 *c)
static void init_zhaoxin(struct cpuinfo_x86 *c)
{
early_init_zhaoxin(c);
detect_extended_topology(c);
init_intel_cacheinfo(c);
detect_num_cpu_cores(c);
if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
detect_num_cpu_cores(c);
#ifdef CONFIG_X86_32
detect_ht(c);
#endif
}
if (c->cpuid_level > 9) {
unsigned int eax = cpuid_eax(10);
@ -141,6 +144,8 @@ static void init_zhaoxin(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
#endif
init_ia32_feat_ctl(c);
if (cpu_has(c, X86_FEATURE_VMX))
zhaoxin_detect_vmx_virtcap(c);
}