drm/radeon: fix typo in PG flags
s/CG/PG/ in the GFX powergating flag name. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9a71677874
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2b19d17fbd
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@ -5558,7 +5558,7 @@ static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
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{
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u32 data, orig;
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
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orig = data = RREG32(RLC_PG_CNTL);
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data |= GFX_PG_ENABLE;
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if (orig != data)
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@ -5822,7 +5822,7 @@ static void cik_init_pg(struct radeon_device *rdev)
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if (rdev->pg_flags) {
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cik_enable_sck_slowdown_on_pu(rdev, true);
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cik_enable_sck_slowdown_on_pd(rdev, true);
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
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cik_init_gfx_cgpg(rdev);
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cik_enable_cp_pg(rdev, true);
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cik_enable_gds_pg(rdev, true);
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@ -5836,7 +5836,7 @@ static void cik_fini_pg(struct radeon_device *rdev)
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{
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if (rdev->pg_flags) {
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cik_update_gfx_pg(rdev, false);
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
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cik_enable_cp_pg(rdev, false);
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cik_enable_gds_pg(rdev, false);
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}
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@ -181,7 +181,7 @@ extern int radeon_aspm;
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#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
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/* PG flags */
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#define RADEON_PG_SUPPORT_GFX_CG (1 << 0)
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#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
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#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
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#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
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#define RADEON_PG_SUPPORT_UVD (1 << 3)
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@ -2391,7 +2391,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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RADEON_CG_SUPPORT_HDP_LS |
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RADEON_CG_SUPPORT_HDP_MGCG;
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rdev->pg_flags = 0 |
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/*RADEON_PG_SUPPORT_GFX_CG | */
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/*RADEON_PG_SUPPORT_GFX_PG | */
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RADEON_PG_SUPPORT_SDMA;
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break;
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case CHIP_OLAND:
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@ -2480,7 +2480,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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RADEON_CG_SUPPORT_HDP_LS |
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RADEON_CG_SUPPORT_HDP_MGCG;
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rdev->pg_flags = 0;
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/*RADEON_PG_SUPPORT_GFX_CG |
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/*RADEON_PG_SUPPORT_GFX_PG |
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RADEON_PG_SUPPORT_GFX_SMG |
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RADEON_PG_SUPPORT_GFX_DMG |
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RADEON_PG_SUPPORT_UVD |
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@ -2508,7 +2508,7 @@ int radeon_asic_init(struct radeon_device *rdev)
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RADEON_CG_SUPPORT_HDP_LS |
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RADEON_CG_SUPPORT_HDP_MGCG;
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rdev->pg_flags = 0;
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/*RADEON_PG_SUPPORT_GFX_CG |
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/*RADEON_PG_SUPPORT_GFX_PG |
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RADEON_PG_SUPPORT_GFX_SMG |
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RADEON_PG_SUPPORT_UVD |
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RADEON_PG_SUPPORT_VCE |
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@ -4894,7 +4894,7 @@ static void si_enable_gfx_cgpg(struct radeon_device *rdev,
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{
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u32 tmp;
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)) {
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if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
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tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
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WREG32(RLC_TTOP_D, tmp);
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@ -5416,7 +5416,7 @@ static void si_init_pg(struct radeon_device *rdev)
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si_init_dma_pg(rdev);
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}
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si_init_ao_cu_mask(rdev);
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
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if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
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si_init_gfx_cgpg(rdev);
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}
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si_enable_dma_pg(rdev, true);
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