sh-pfc: sh7785: Remove unused input_pu range
The PFC SH7785 SoC data contains a input_pu range used to configure pull-up resistors using the legacy non-pinconf API. That API has been removed from the driver, the range is thus not used anymore. Remove it. If required, configuring pull-up resistors for the SH7785 can be implemented using the pinconf API, as done for the SH-Mobile, R-Mobile and R-Car platforms. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
parent
5f86072afb
commit
2afb968126
|
|
@ -77,36 +77,6 @@ enum {
|
|||
PR3_IN, PR2_IN, PR1_IN, PR0_IN,
|
||||
PINMUX_INPUT_END,
|
||||
|
||||
PINMUX_INPUT_PULLUP_BEGIN,
|
||||
PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
|
||||
PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
|
||||
PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
|
||||
PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
|
||||
PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
|
||||
PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
|
||||
PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
|
||||
PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
|
||||
PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
|
||||
PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
|
||||
PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
|
||||
PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
|
||||
PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
|
||||
PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
|
||||
PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
|
||||
PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
|
||||
PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU,
|
||||
PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU,
|
||||
PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU,
|
||||
PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU,
|
||||
PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU,
|
||||
PM1_IN_PU, PM0_IN_PU,
|
||||
PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU,
|
||||
PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU,
|
||||
PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU,
|
||||
PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU,
|
||||
PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU,
|
||||
PINMUX_INPUT_PULLUP_END,
|
||||
|
||||
PINMUX_OUTPUT_BEGIN,
|
||||
PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
|
||||
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
|
||||
|
|
@ -358,147 +328,147 @@ enum {
|
|||
static const pinmux_enum_t pinmux_data[] = {
|
||||
|
||||
/* PA GPIO */
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
|
||||
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
|
||||
PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
|
||||
PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
|
||||
PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
|
||||
PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
|
||||
PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
|
||||
PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
|
||||
PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
|
||||
|
||||
/* PB GPIO */
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
|
||||
PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
|
||||
PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
|
||||
PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
|
||||
PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
|
||||
PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
|
||||
PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
|
||||
PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
|
||||
PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
|
||||
|
||||
/* PC GPIO */
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
|
||||
PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
|
||||
PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
|
||||
PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
|
||||
PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
|
||||
PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
|
||||
PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
|
||||
PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
|
||||
PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
|
||||
|
||||
/* PD GPIO */
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
|
||||
PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
|
||||
PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
|
||||
PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
|
||||
PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
|
||||
PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
|
||||
PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
|
||||
PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
|
||||
PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
|
||||
|
||||
/* PE GPIO */
|
||||
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
|
||||
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
|
||||
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
|
||||
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
|
||||
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
|
||||
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
|
||||
PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT),
|
||||
PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT),
|
||||
PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT),
|
||||
PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT),
|
||||
PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT),
|
||||
PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT),
|
||||
|
||||
/* PF GPIO */
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
|
||||
PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
|
||||
PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
|
||||
PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
|
||||
PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
|
||||
PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
|
||||
PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
|
||||
PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
|
||||
PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
|
||||
|
||||
/* PG GPIO */
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
|
||||
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
|
||||
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
|
||||
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
|
||||
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
|
||||
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
|
||||
PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
|
||||
PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
|
||||
PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
|
||||
PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT),
|
||||
PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT),
|
||||
PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT),
|
||||
PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT),
|
||||
PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT),
|
||||
|
||||
/* PH GPIO */
|
||||
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
|
||||
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
|
||||
PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
|
||||
PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
|
||||
PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
|
||||
PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
|
||||
PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
|
||||
PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
|
||||
PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
|
||||
PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
|
||||
|
||||
/* PJ GPIO */
|
||||
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
|
||||
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
|
||||
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
|
||||
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
|
||||
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
|
||||
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
|
||||
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
|
||||
PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU),
|
||||
PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
|
||||
PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
|
||||
PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
|
||||
PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
|
||||
PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
|
||||
PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
|
||||
PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
|
||||
PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT),
|
||||
|
||||
/* PK GPIO */
|
||||
PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU),
|
||||
PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU),
|
||||
PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU),
|
||||
PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU),
|
||||
PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU),
|
||||
PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU),
|
||||
PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU),
|
||||
PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU),
|
||||
PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT),
|
||||
PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT),
|
||||
PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT),
|
||||
PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT),
|
||||
PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT),
|
||||
PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT),
|
||||
PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT),
|
||||
PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT),
|
||||
|
||||
/* PL GPIO */
|
||||
PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU),
|
||||
PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU),
|
||||
PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU),
|
||||
PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU),
|
||||
PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU),
|
||||
PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU),
|
||||
PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU),
|
||||
PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU),
|
||||
PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT),
|
||||
PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT),
|
||||
PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT),
|
||||
PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT),
|
||||
PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT),
|
||||
PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT),
|
||||
PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT),
|
||||
PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT),
|
||||
|
||||
/* PM GPIO */
|
||||
PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU),
|
||||
PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU),
|
||||
PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT),
|
||||
PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT),
|
||||
|
||||
/* PN GPIO */
|
||||
PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU),
|
||||
PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU),
|
||||
PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU),
|
||||
PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU),
|
||||
PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU),
|
||||
PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU),
|
||||
PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU),
|
||||
PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU),
|
||||
PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT),
|
||||
PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT),
|
||||
PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT),
|
||||
PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT),
|
||||
PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT),
|
||||
PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT),
|
||||
PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT),
|
||||
PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT),
|
||||
|
||||
/* PP GPIO */
|
||||
PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU),
|
||||
PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU),
|
||||
PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU),
|
||||
PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU),
|
||||
PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU),
|
||||
PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU),
|
||||
PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT),
|
||||
PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT),
|
||||
PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT),
|
||||
PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT),
|
||||
PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT),
|
||||
PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT),
|
||||
|
||||
/* PQ GPIO */
|
||||
PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU),
|
||||
PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU),
|
||||
PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU),
|
||||
PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU),
|
||||
PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU),
|
||||
PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT),
|
||||
PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT),
|
||||
PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT),
|
||||
PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT),
|
||||
PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT),
|
||||
|
||||
/* PR GPIO */
|
||||
PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU),
|
||||
PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU),
|
||||
PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU),
|
||||
PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU),
|
||||
PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT),
|
||||
PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT),
|
||||
PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT),
|
||||
PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT),
|
||||
|
||||
/* PA FN */
|
||||
PINMUX_DATA(D63_AD31_MARK, PA7_FN),
|
||||
|
|
@ -1020,114 +990,114 @@ static const struct pinmux_func pinmux_func_gpios[] = {
|
|||
|
||||
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
|
||||
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
|
||||
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
|
||||
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
|
||||
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
|
||||
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
|
||||
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
|
||||
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
|
||||
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
|
||||
PA7_FN, PA7_OUT, PA7_IN, 0,
|
||||
PA6_FN, PA6_OUT, PA6_IN, 0,
|
||||
PA5_FN, PA5_OUT, PA5_IN, 0,
|
||||
PA4_FN, PA4_OUT, PA4_IN, 0,
|
||||
PA3_FN, PA3_OUT, PA3_IN, 0,
|
||||
PA2_FN, PA2_OUT, PA2_IN, 0,
|
||||
PA1_FN, PA1_OUT, PA1_IN, 0,
|
||||
PA0_FN, PA0_OUT, PA0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) {
|
||||
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
|
||||
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
|
||||
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
|
||||
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
|
||||
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
|
||||
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
|
||||
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
|
||||
PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
|
||||
PB7_FN, PB7_OUT, PB7_IN, 0,
|
||||
PB6_FN, PB6_OUT, PB6_IN, 0,
|
||||
PB5_FN, PB5_OUT, PB5_IN, 0,
|
||||
PB4_FN, PB4_OUT, PB4_IN, 0,
|
||||
PB3_FN, PB3_OUT, PB3_IN, 0,
|
||||
PB2_FN, PB2_OUT, PB2_IN, 0,
|
||||
PB1_FN, PB1_OUT, PB1_IN, 0,
|
||||
PB0_FN, PB0_OUT, PB0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) {
|
||||
PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
|
||||
PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
|
||||
PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
|
||||
PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
|
||||
PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
|
||||
PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
|
||||
PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
|
||||
PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
|
||||
PC7_FN, PC7_OUT, PC7_IN, 0,
|
||||
PC6_FN, PC6_OUT, PC6_IN, 0,
|
||||
PC5_FN, PC5_OUT, PC5_IN, 0,
|
||||
PC4_FN, PC4_OUT, PC4_IN, 0,
|
||||
PC3_FN, PC3_OUT, PC3_IN, 0,
|
||||
PC2_FN, PC2_OUT, PC2_IN, 0,
|
||||
PC1_FN, PC1_OUT, PC1_IN, 0,
|
||||
PC0_FN, PC0_OUT, PC0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) {
|
||||
PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
|
||||
PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
|
||||
PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
|
||||
PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
|
||||
PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
|
||||
PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
|
||||
PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
|
||||
PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
|
||||
PD7_FN, PD7_OUT, PD7_IN, 0,
|
||||
PD6_FN, PD6_OUT, PD6_IN, 0,
|
||||
PD5_FN, PD5_OUT, PD5_IN, 0,
|
||||
PD4_FN, PD4_OUT, PD4_IN, 0,
|
||||
PD3_FN, PD3_OUT, PD3_IN, 0,
|
||||
PD2_FN, PD2_OUT, PD2_IN, 0,
|
||||
PD1_FN, PD1_OUT, PD1_IN, 0,
|
||||
PD0_FN, PD0_OUT, PD0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
|
||||
PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
|
||||
PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
|
||||
PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
|
||||
PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
|
||||
PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU }
|
||||
PE5_FN, PE5_OUT, PE5_IN, 0,
|
||||
PE4_FN, PE4_OUT, PE4_IN, 0,
|
||||
PE3_FN, PE3_OUT, PE3_IN, 0,
|
||||
PE2_FN, PE2_OUT, PE2_IN, 0,
|
||||
PE1_FN, PE1_OUT, PE1_IN, 0,
|
||||
PE0_FN, PE0_OUT, PE0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) {
|
||||
PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
|
||||
PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
|
||||
PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
|
||||
PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
|
||||
PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
|
||||
PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
|
||||
PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
|
||||
PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
|
||||
PF7_FN, PF7_OUT, PF7_IN, 0,
|
||||
PF6_FN, PF6_OUT, PF6_IN, 0,
|
||||
PF5_FN, PF5_OUT, PF5_IN, 0,
|
||||
PF4_FN, PF4_OUT, PF4_IN, 0,
|
||||
PF3_FN, PF3_OUT, PF3_IN, 0,
|
||||
PF2_FN, PF2_OUT, PF2_IN, 0,
|
||||
PF1_FN, PF1_OUT, PF1_IN, 0,
|
||||
PF0_FN, PF0_OUT, PF0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) {
|
||||
PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
|
||||
PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
|
||||
PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
|
||||
PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
|
||||
PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
|
||||
PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
|
||||
PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
|
||||
PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU }
|
||||
PG7_FN, PG7_OUT, PG7_IN, 0,
|
||||
PG6_FN, PG6_OUT, PG6_IN, 0,
|
||||
PG5_FN, PG5_OUT, PG5_IN, 0,
|
||||
PG4_FN, PG4_OUT, PG4_IN, 0,
|
||||
PG3_FN, PG3_OUT, PG3_IN, 0,
|
||||
PG2_FN, PG2_OUT, PG2_IN, 0,
|
||||
PG1_FN, PG1_OUT, PG1_IN, 0,
|
||||
PG0_FN, PG0_OUT, PG0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) {
|
||||
PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
|
||||
PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
|
||||
PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
|
||||
PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
|
||||
PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
|
||||
PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
|
||||
PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
|
||||
PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
|
||||
PH7_FN, PH7_OUT, PH7_IN, 0,
|
||||
PH6_FN, PH6_OUT, PH6_IN, 0,
|
||||
PH5_FN, PH5_OUT, PH5_IN, 0,
|
||||
PH4_FN, PH4_OUT, PH4_IN, 0,
|
||||
PH3_FN, PH3_OUT, PH3_IN, 0,
|
||||
PH2_FN, PH2_OUT, PH2_IN, 0,
|
||||
PH1_FN, PH1_OUT, PH1_IN, 0,
|
||||
PH0_FN, PH0_OUT, PH0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) {
|
||||
PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
|
||||
PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
|
||||
PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
|
||||
PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
|
||||
PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
|
||||
PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
|
||||
PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
|
||||
PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU }
|
||||
PJ7_FN, PJ7_OUT, PJ7_IN, 0,
|
||||
PJ6_FN, PJ6_OUT, PJ6_IN, 0,
|
||||
PJ5_FN, PJ5_OUT, PJ5_IN, 0,
|
||||
PJ4_FN, PJ4_OUT, PJ4_IN, 0,
|
||||
PJ3_FN, PJ3_OUT, PJ3_IN, 0,
|
||||
PJ2_FN, PJ2_OUT, PJ2_IN, 0,
|
||||
PJ1_FN, PJ1_OUT, PJ1_IN, 0,
|
||||
PJ0_FN, PJ0_OUT, PJ0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) {
|
||||
PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU,
|
||||
PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU,
|
||||
PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU,
|
||||
PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU,
|
||||
PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU,
|
||||
PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU,
|
||||
PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU,
|
||||
PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU }
|
||||
PK7_FN, PK7_OUT, PK7_IN, 0,
|
||||
PK6_FN, PK6_OUT, PK6_IN, 0,
|
||||
PK5_FN, PK5_OUT, PK5_IN, 0,
|
||||
PK4_FN, PK4_OUT, PK4_IN, 0,
|
||||
PK3_FN, PK3_OUT, PK3_IN, 0,
|
||||
PK2_FN, PK2_OUT, PK2_IN, 0,
|
||||
PK1_FN, PK1_OUT, PK1_IN, 0,
|
||||
PK0_FN, PK0_OUT, PK0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) {
|
||||
PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU,
|
||||
PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU,
|
||||
PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU,
|
||||
PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU,
|
||||
PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU,
|
||||
PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU,
|
||||
PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU,
|
||||
PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU }
|
||||
PL7_FN, PL7_OUT, PL7_IN, 0,
|
||||
PL6_FN, PL6_OUT, PL6_IN, 0,
|
||||
PL5_FN, PL5_OUT, PL5_IN, 0,
|
||||
PL4_FN, PL4_OUT, PL4_IN, 0,
|
||||
PL3_FN, PL3_OUT, PL3_IN, 0,
|
||||
PL2_FN, PL2_OUT, PL2_IN, 0,
|
||||
PL1_FN, PL1_OUT, PL1_IN, 0,
|
||||
PL0_FN, PL0_OUT, PL0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
|
|
@ -1136,48 +1106,48 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU,
|
||||
PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU }
|
||||
PM1_FN, PM1_OUT, PM1_IN, 0,
|
||||
PM0_FN, PM0_OUT, PM0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) {
|
||||
PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU,
|
||||
PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU,
|
||||
PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU,
|
||||
PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU,
|
||||
PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU,
|
||||
PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU,
|
||||
PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU,
|
||||
PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU }
|
||||
PN7_FN, PN7_OUT, PN7_IN, 0,
|
||||
PN6_FN, PN6_OUT, PN6_IN, 0,
|
||||
PN5_FN, PN5_OUT, PN5_IN, 0,
|
||||
PN4_FN, PN4_OUT, PN4_IN, 0,
|
||||
PN3_FN, PN3_OUT, PN3_IN, 0,
|
||||
PN2_FN, PN2_OUT, PN2_IN, 0,
|
||||
PN1_FN, PN1_OUT, PN1_IN, 0,
|
||||
PN0_FN, PN0_OUT, PN0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU,
|
||||
PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU,
|
||||
PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU,
|
||||
PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU,
|
||||
PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU,
|
||||
PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU }
|
||||
PP5_FN, PP5_OUT, PP5_IN, 0,
|
||||
PP4_FN, PP4_OUT, PP4_IN, 0,
|
||||
PP3_FN, PP3_OUT, PP3_IN, 0,
|
||||
PP2_FN, PP2_OUT, PP2_IN, 0,
|
||||
PP1_FN, PP1_OUT, PP1_IN, 0,
|
||||
PP0_FN, PP0_OUT, PP0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU,
|
||||
PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU,
|
||||
PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU,
|
||||
PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU,
|
||||
PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU }
|
||||
PQ4_FN, PQ4_OUT, PQ4_IN, 0,
|
||||
PQ3_FN, PQ3_OUT, PQ3_IN, 0,
|
||||
PQ2_FN, PQ2_OUT, PQ2_IN, 0,
|
||||
PQ1_FN, PQ1_OUT, PQ1_IN, 0,
|
||||
PQ0_FN, PQ0_OUT, PQ0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) {
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU,
|
||||
PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU,
|
||||
PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU,
|
||||
PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU }
|
||||
PR3_FN, PR3_OUT, PR3_IN, 0,
|
||||
PR2_FN, PR2_OUT, PR2_IN, 0,
|
||||
PR1_FN, PR1_OUT, PR1_IN, 0,
|
||||
PR0_FN, PR0_OUT, PR0_IN, 0 }
|
||||
},
|
||||
{ PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) {
|
||||
P1MSEL15_0, P1MSEL15_1,
|
||||
|
|
@ -1289,7 +1259,6 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
const struct sh_pfc_soc_info sh7785_pinmux_info = {
|
||||
.name = "sh7785_pfc",
|
||||
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
|
||||
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
|
||||
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue