ARM: dts: rockchip: add core rk3288 dtsi
Node definitions shared by all rk3288 based boards. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Heiko Stuebner
parent
7a1917abdd
commit
2ab557b72d
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3288";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x500>;
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};
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cpu@501 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x501>;
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};
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cpu@502 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x502>;
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};
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cpu@503 {
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device_type = "cpu";
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compatible = "arm,cortex-a12";
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reg = <0x503>;
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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i2c1: i2c@ff140000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff140000 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff150000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff150000 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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i2c4: i2c@ff160000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff160000 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C4>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff170000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C5>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff180000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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status = "disabled";
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};
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uart1: serial@ff190000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff190000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart2: serial@ff690000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff690000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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status = "disabled";
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};
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uart3: serial@ff1b0000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff1b0000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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status = "disabled";
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};
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uart4: serial@ff1c0000 {
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compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
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reg = <0xff1c0000 0x100>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_xfer>;
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status = "disabled";
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff650000 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c2: i2c@ff660000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0xff660000 0x1000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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pmu: power-management@ff730000 {
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compatible = "rockchip,rk3288-pmu", "syscon";
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reg = <0xff730000 0x100>;
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};
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sgrf: syscon@ff740000 {
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compatible = "rockchip,rk3288-sgrf", "syscon";
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reg = <0xff740000 0x1000>;
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};
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cru: clock-controller@ff760000 {
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compatible = "rockchip,rk3288-cru";
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reg = <0xff760000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3288-grf", "syscon";
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reg = <0xff770000 0x1000>;
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};
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wdt: watchdog@ff800000 {
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compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
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reg = <0xff800000 0x100>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0xffc01000 0x1000>,
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<0xffc02000 0x1000>,
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<0xffc04000 0x2000>,
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<0xffc06000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3288-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@ff750000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff750000 0x100>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@ff780000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff780000 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@ff790000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff790000 0x100>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@ff7a0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7a0000 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio4@ff7b0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7b0000 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO4>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio5@ff7c0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7c0000 0x100>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO5>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio6@ff7d0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7d0000 0x100>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO6>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio7: gpio7@ff7e0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7e0000 0x100>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO7>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio8: gpio8@ff7f0000 {
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compatible = "rockchip,gpio-bank";
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reg = <0xff7f0000 0x100>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
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<0 16 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
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<8 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
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<6 10 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
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<2 17 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
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<7 18 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c5 {
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i2c5_xfer: i2c5-xfer {
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rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
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<7 20 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sdmmc {
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sdmmc_clk: sdmmc-clk {
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rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
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};
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sdmmc_cd: sdmcc-cd {
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rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
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};
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sdmmc_bus1: sdmmc-bus1 {
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rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
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};
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 17 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 18 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<6 19 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_pwr: emmc-pwr {
|
||||
rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus1: emmc-bus1 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus4: emmc-bus4 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 3 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 1 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 2 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 3 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 4 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 5 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 6 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 7 RK_FUNC_2 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<4 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<5 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<7 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<7 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
uart4_xfer: uart4-xfer {
|
||||
rockchip,pins = <5 12 3 &pcfg_pull_up>,
|
||||
<5 13 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart4_cts: uart4-cts {
|
||||
rockchip,pins = <5 14 3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart4_rts: uart4-rts {
|
||||
rockchip,pins = <5 15 3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue