mtd: spi-nor: Add a post BFPT parsing fixup hook
Experience has proven that SFDP tables are sometimes wrong, and parsing of these broken tables can lead to erroneous flash config. This leaves us 2 options: 1/ set the SPI_NOR_SKIP_SFDP flag and completely ignore SFDP parsing 2/ fix things at runtime While #1 should always work, it might imply extra work if most of the SFDP is correct. #2 has the benefit of keeping the generic SFDP parsing logic almost untouched while allowing SPI NOR manufacturer drivers to fix the broken bits. Add a spi_nor_fixups struct where we'll put all our fixup hooks, each of them being called at a different point in the scan process. We start a hook called just after the BFPT parsing to allow fixing up info extracted from the BFPT section. More hooks will be added if other sections need to be fixed. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Boris Brezillon
parent
548ed6847f
commit
2aaa5f7e0c
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@ -42,6 +42,196 @@
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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struct spi_nor_pp_command {
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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SNOR_CMD_READ_1_1_1_DTR,
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/* Dual SPI */
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SNOR_CMD_READ_1_1_2,
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SNOR_CMD_READ_1_2_2,
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SNOR_CMD_READ_2_2_2,
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SNOR_CMD_READ_1_2_2_DTR,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_1_4_4,
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octo SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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SNOR_CMD_READ_1_8_8_DTR,
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SNOR_CMD_READ_MAX
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};
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enum spi_nor_pp_command_index {
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SNOR_CMD_PP,
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/* Quad SPI */
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SNOR_CMD_PP_1_1_4,
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octo SPI */
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SNOR_CMD_PP_1_1_8,
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SNOR_CMD_PP_1_8_8,
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SNOR_CMD_PP_8_8_8,
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SNOR_CMD_PP_MAX
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};
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
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int (*quad_enable)(struct spi_nor *nor);
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};
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struct sfdp_parameter_header {
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u8 id_lsb;
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u8 minor;
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u8 major;
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u8 length; /* in double words */
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u8 parameter_table_pointer[3]; /* byte address */
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u8 id_msb;
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};
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#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
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#define SFDP_PARAM_HEADER_PTP(p) \
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(((p)->parameter_table_pointer[2] << 16) | \
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((p)->parameter_table_pointer[1] << 8) | \
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((p)->parameter_table_pointer[0] << 0))
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#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
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#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
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#define SFDP_SIGNATURE 0x50444653U
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#define SFDP_JESD216_MAJOR 1
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#define SFDP_JESD216_MINOR 0
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#define SFDP_JESD216A_MINOR 5
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#define SFDP_JESD216B_MINOR 6
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struct sfdp_header {
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u32 signature; /* Ox50444653U <=> "SFDP" */
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u8 minor;
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u8 major;
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u8 nph; /* 0-base number of parameter headers */
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u8 unused;
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/* Basic Flash Parameter Table. */
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struct sfdp_parameter_header bfpt_header;
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};
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/* Basic Flash Parameter Table */
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/*
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* JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
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* They are indexed from 1 but C arrays are indexed from 0.
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*/
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#define BFPT_DWORD(i) ((i) - 1)
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#define BFPT_DWORD_MAX 16
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/* The first version of JESB216 defined only 9 DWORDs. */
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#define BFPT_DWORD_MAX_JESD216 9
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/* 1st DWORD. */
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#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
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#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
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#define BFPT_DWORD1_DTR BIT(19)
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#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
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#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
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#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
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/* 5th DWORD. */
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#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
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#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
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/* 11th DWORD. */
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#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
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#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
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/* 15th DWORD. */
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/*
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* (from JESD216 rev B)
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* Quad Enable Requirements (QER):
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* - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
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* reads based on instruction. DQ3/HOLD# functions are hold during
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* instruction phase.
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* - 001b: QE is bit 1 of status register 2. It is set via Write Status with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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* Writing only one byte to the status register has the side-effect of
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* clearing status register 2, including the QE bit. The 100b code is
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* used if writing one byte to the status register does not modify
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* status register 2.
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* - 010b: QE is bit 6 of status register 1. It is set via Write Status with
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* one data byte where bit 6 is one.
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* [...]
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* - 011b: QE is bit 7 of status register 2. It is set via Write status
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* register 2 instruction 3Eh with one data byte where bit 7 is one.
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* [...]
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* The status register 2 is read using instruction 3Fh.
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* - 100b: QE is bit 1 of status register 2. It is set via Write Status with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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* In contrast to the 001b code, writing one byte to the status
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* register does not modify status register 2.
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* - 101b: QE is bit 1 of status register 2. Status register 1 is read using
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* Read Status instruction 05h. Status register2 is read using
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* instruction 35h. QE is set via Writ Status instruction 01h with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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*/
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#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
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#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
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#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
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#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
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#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
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#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
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#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
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struct sfdp_bfpt {
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u32 dwords[BFPT_DWORD_MAX];
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};
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/**
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* struct spi_nor_fixups - SPI NOR fixup hooks
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* @post_bfpt: called after the BFPT table has been parsed
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*
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* Those hooks can be used to tweak the SPI NOR configuration when the SFDP
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* table is broken or not available.
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*/
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struct spi_nor_fixups {
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int (*post_bfpt)(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params);
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};
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struct flash_info {
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char *name;
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@ -91,6 +281,9 @@ struct flash_info {
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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/* Part specific fixup hooks. */
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const struct spi_nor_fixups *fixups;
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int (*quad_enable)(struct spi_nor *nor);
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};
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@ -2076,71 +2269,6 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
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return 0;
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}
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struct spi_nor_read_command {
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u8 num_mode_clocks;
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u8 num_wait_states;
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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struct spi_nor_pp_command {
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u8 opcode;
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enum spi_nor_protocol proto;
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};
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enum spi_nor_read_command_index {
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SNOR_CMD_READ,
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SNOR_CMD_READ_FAST,
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SNOR_CMD_READ_1_1_1_DTR,
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/* Dual SPI */
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SNOR_CMD_READ_1_1_2,
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SNOR_CMD_READ_1_2_2,
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SNOR_CMD_READ_2_2_2,
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SNOR_CMD_READ_1_2_2_DTR,
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/* Quad SPI */
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SNOR_CMD_READ_1_1_4,
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SNOR_CMD_READ_1_4_4,
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SNOR_CMD_READ_4_4_4,
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SNOR_CMD_READ_1_4_4_DTR,
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/* Octo SPI */
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SNOR_CMD_READ_1_1_8,
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SNOR_CMD_READ_1_8_8,
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SNOR_CMD_READ_8_8_8,
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SNOR_CMD_READ_1_8_8_DTR,
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SNOR_CMD_READ_MAX
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};
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enum spi_nor_pp_command_index {
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SNOR_CMD_PP,
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/* Quad SPI */
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SNOR_CMD_PP_1_1_4,
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SNOR_CMD_PP_1_4_4,
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SNOR_CMD_PP_4_4_4,
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/* Octo SPI */
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SNOR_CMD_PP_1_1_8,
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SNOR_CMD_PP_1_8_8,
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SNOR_CMD_PP_8_8_8,
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SNOR_CMD_PP_MAX
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};
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struct spi_nor_flash_parameter {
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u64 size;
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u32 page_size;
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struct spi_nor_hwcaps hwcaps;
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struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
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struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
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int (*quad_enable)(struct spi_nor *nor);
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};
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static void
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spi_nor_set_read_settings(struct spi_nor_read_command *read,
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u8 num_mode_clocks,
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@ -2263,117 +2391,6 @@ static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
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return ret;
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}
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struct sfdp_parameter_header {
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u8 id_lsb;
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u8 minor;
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u8 major;
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u8 length; /* in double words */
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u8 parameter_table_pointer[3]; /* byte address */
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u8 id_msb;
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};
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#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
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#define SFDP_PARAM_HEADER_PTP(p) \
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(((p)->parameter_table_pointer[2] << 16) | \
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((p)->parameter_table_pointer[1] << 8) | \
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((p)->parameter_table_pointer[0] << 0))
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#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
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#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
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#define SFDP_SIGNATURE 0x50444653U
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#define SFDP_JESD216_MAJOR 1
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#define SFDP_JESD216_MINOR 0
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#define SFDP_JESD216A_MINOR 5
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#define SFDP_JESD216B_MINOR 6
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struct sfdp_header {
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u32 signature; /* Ox50444653U <=> "SFDP" */
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u8 minor;
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u8 major;
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u8 nph; /* 0-base number of parameter headers */
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u8 unused;
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/* Basic Flash Parameter Table. */
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struct sfdp_parameter_header bfpt_header;
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};
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/* Basic Flash Parameter Table */
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/*
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* JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
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* They are indexed from 1 but C arrays are indexed from 0.
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*/
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#define BFPT_DWORD(i) ((i) - 1)
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#define BFPT_DWORD_MAX 16
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/* The first version of JESB216 defined only 9 DWORDs. */
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#define BFPT_DWORD_MAX_JESD216 9
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/* 1st DWORD. */
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#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
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#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
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#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
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#define BFPT_DWORD1_DTR BIT(19)
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#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
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#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
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#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
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/* 5th DWORD. */
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#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
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#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
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/* 11th DWORD. */
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#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
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#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
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/* 15th DWORD. */
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/*
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* (from JESD216 rev B)
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* Quad Enable Requirements (QER):
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* - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
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* reads based on instruction. DQ3/HOLD# functions are hold during
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* instruction phase.
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* - 001b: QE is bit 1 of status register 2. It is set via Write Status with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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* Writing only one byte to the status register has the side-effect of
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* clearing status register 2, including the QE bit. The 100b code is
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* used if writing one byte to the status register does not modify
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* status register 2.
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* - 010b: QE is bit 6 of status register 1. It is set via Write Status with
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* one data byte where bit 6 is one.
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* [...]
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* - 011b: QE is bit 7 of status register 2. It is set via Write status
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* register 2 instruction 3Eh with one data byte where bit 7 is one.
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* [...]
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* The status register 2 is read using instruction 3Fh.
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* - 100b: QE is bit 1 of status register 2. It is set via Write Status with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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* In contrast to the 001b code, writing one byte to the status
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* register does not modify status register 2.
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* - 101b: QE is bit 1 of status register 2. Status register 1 is read using
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* Read Status instruction 05h. Status register2 is read using
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* instruction 35h. QE is set via Writ Status instruction 01h with
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* two data bytes where bit 1 of the second byte is one.
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* [...]
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*/
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#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
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#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
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#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
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#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
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#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
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#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
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#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
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struct sfdp_bfpt {
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u32 dwords[BFPT_DWORD_MAX];
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};
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/* Fast Read settings. */
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static inline void
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@ -2617,6 +2634,19 @@ static void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
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map->uniform_erase_type = erase_mask;
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}
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static int
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spi_nor_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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if (nor->info->fixups && nor->info->fixups->post_bfpt)
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return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt,
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params);
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return 0;
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}
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/**
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* spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
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* @nor: pointer to a 'struct spi_nor'
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@ -2769,7 +2799,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
|
|||
|
||||
/* Stop here if not JESD216 rev A or later. */
|
||||
if (bfpt_header->length < BFPT_DWORD_MAX)
|
||||
return 0;
|
||||
return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
|
||||
params);
|
||||
|
||||
/* Page size: this field specifies 'N' so the page size = 2^N bytes. */
|
||||
params->page_size = bfpt.dwords[BFPT_DWORD(11)];
|
||||
|
|
@ -2804,7 +2835,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
|
||||
}
|
||||
|
||||
#define SMPT_CMD_ADDRESS_LEN_MASK GENMASK(23, 22)
|
||||
|
|
|
|||
Loading…
Reference in New Issue