drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL
Track the system agent voltage we request from pcode in the cdclk state on SKL/KBL/CFL. Annoyingly we can't actually read out the current value since there's no pcode command to do that, so we'll have to just assume that it worked. v2: s/voltage/voltage_level/ (Rodrigo) Cc: Mika Kahola <mika.kahola@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-6-ville.syrjala@linux.intel.com
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d7ffaeef96
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@ -785,6 +785,24 @@ static int skl_calc_cdclk(int min_cdclk, int vco)
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}
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}
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}
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}
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static u8 skl_calc_voltage_level(int cdclk)
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{
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switch (cdclk) {
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default:
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case 308571:
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case 337500:
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return 0;
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case 450000:
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case 432000:
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return 1;
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case 540000:
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return 2;
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case 617143:
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case 675000:
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return 3;
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}
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}
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static void skl_dpll0_update(struct drm_i915_private *dev_priv,
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static void skl_dpll0_update(struct drm_i915_private *dev_priv,
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struct intel_cdclk_state *cdclk_state)
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struct intel_cdclk_state *cdclk_state)
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{
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{
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@ -835,7 +853,7 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
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cdclk_state->cdclk = cdclk_state->ref;
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cdclk_state->cdclk = cdclk_state->ref;
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if (cdclk_state->vco == 0)
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if (cdclk_state->vco == 0)
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return;
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goto out;
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cdctl = I915_READ(CDCLK_CTL);
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cdctl = I915_READ(CDCLK_CTL);
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@ -876,6 +894,14 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv,
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break;
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break;
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}
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}
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}
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}
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out:
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/*
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* Can't read this out :( Let's assume it's
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* at least what the CDCLK frequency requires.
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*/
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cdclk_state->voltage_level =
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skl_calc_voltage_level(cdclk_state->cdclk);
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}
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}
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/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
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/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
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@ -960,7 +986,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
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{
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{
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int cdclk = cdclk_state->cdclk;
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int cdclk = cdclk_state->cdclk;
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int vco = cdclk_state->vco;
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int vco = cdclk_state->vco;
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u32 freq_select, pcu_ack;
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u32 freq_select;
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int ret;
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int ret;
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mutex_lock(&dev_priv->pcu_lock);
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mutex_lock(&dev_priv->pcu_lock);
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@ -984,21 +1010,17 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
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case 308571:
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case 308571:
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case 337500:
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case 337500:
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freq_select = CDCLK_FREQ_337_308;
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freq_select = CDCLK_FREQ_337_308;
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pcu_ack = 0;
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break;
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break;
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case 450000:
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case 450000:
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case 432000:
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case 432000:
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freq_select = CDCLK_FREQ_450_432;
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freq_select = CDCLK_FREQ_450_432;
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pcu_ack = 1;
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break;
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break;
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case 540000:
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case 540000:
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freq_select = CDCLK_FREQ_540;
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freq_select = CDCLK_FREQ_540;
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pcu_ack = 2;
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break;
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break;
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case 617143:
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case 617143:
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case 675000:
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case 675000:
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freq_select = CDCLK_FREQ_675_617;
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freq_select = CDCLK_FREQ_675_617;
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pcu_ack = 3;
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break;
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break;
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}
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}
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@ -1014,7 +1036,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
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/* inform PCU of the change */
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/* inform PCU of the change */
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mutex_lock(&dev_priv->pcu_lock);
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mutex_lock(&dev_priv->pcu_lock);
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sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
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sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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cdclk_state->voltage_level);
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mutex_unlock(&dev_priv->pcu_lock);
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mutex_unlock(&dev_priv->pcu_lock);
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intel_update_cdclk(dev_priv);
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intel_update_cdclk(dev_priv);
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@ -1093,6 +1116,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
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if (cdclk_state.vco == 0)
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if (cdclk_state.vco == 0)
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cdclk_state.vco = 8100000;
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cdclk_state.vco = 8100000;
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cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
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cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
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cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
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skl_set_cdclk(dev_priv, &cdclk_state);
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skl_set_cdclk(dev_priv, &cdclk_state);
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}
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}
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@ -1110,6 +1134,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
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cdclk_state.cdclk = cdclk_state.ref;
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cdclk_state.cdclk = cdclk_state.ref;
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cdclk_state.vco = 0;
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cdclk_state.vco = 0;
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cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
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skl_set_cdclk(dev_priv, &cdclk_state);
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skl_set_cdclk(dev_priv, &cdclk_state);
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}
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}
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@ -1968,12 +1993,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
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intel_state->cdclk.logical.vco = vco;
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intel_state->cdclk.logical.vco = vco;
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intel_state->cdclk.logical.cdclk = cdclk;
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intel_state->cdclk.logical.cdclk = cdclk;
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intel_state->cdclk.logical.voltage_level =
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skl_calc_voltage_level(cdclk);
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if (!intel_state->active_crtcs) {
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if (!intel_state->active_crtcs) {
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cdclk = skl_calc_cdclk(0, vco);
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cdclk = skl_calc_cdclk(0, vco);
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intel_state->cdclk.actual.vco = vco;
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intel_state->cdclk.actual.vco = vco;
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intel_state->cdclk.actual.cdclk = cdclk;
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intel_state->cdclk.actual.cdclk = cdclk;
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intel_state->cdclk.actual.voltage_level =
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skl_calc_voltage_level(cdclk);
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} else {
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} else {
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intel_state->cdclk.actual =
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intel_state->cdclk.actual =
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intel_state->cdclk.logical;
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intel_state->cdclk.logical;
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