Merge tag 'socfpga-clk-fix-for-3.15' of git://git.rocketboards.org/linux-socfpga-next into clk-fixes-socfpga
clk: socfpga: clock fix for v3.15 Currently on 3.15-rc1, the SOCFPGA platform is unable to boot. This patch fixes the issue and allows the platform to boot.
This commit is contained in:
commit
2aa6dd07bd
|
@ -20,6 +20,7 @@
|
||||||
#include <linux/clk-provider.h>
|
#include <linux/clk-provider.h>
|
||||||
#include <linux/io.h>
|
#include <linux/io.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
|
||||||
#include "clk.h"
|
#include "clk.h"
|
||||||
|
|
||||||
|
@ -43,6 +44,8 @@
|
||||||
|
|
||||||
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
|
#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
|
||||||
|
|
||||||
|
void __iomem *clk_mgr_base_addr;
|
||||||
|
|
||||||
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
||||||
unsigned long parent_rate)
|
unsigned long parent_rate)
|
||||||
{
|
{
|
||||||
|
@ -87,6 +90,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
|
||||||
const char *clk_name = node->name;
|
const char *clk_name = node->name;
|
||||||
const char *parent_name[SOCFPGA_MAX_PARENTS];
|
const char *parent_name[SOCFPGA_MAX_PARENTS];
|
||||||
struct clk_init_data init;
|
struct clk_init_data init;
|
||||||
|
struct device_node *clkmgr_np;
|
||||||
int rc;
|
int rc;
|
||||||
int i = 0;
|
int i = 0;
|
||||||
|
|
||||||
|
@ -96,6 +100,9 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
|
||||||
if (WARN_ON(!pll_clk))
|
if (WARN_ON(!pll_clk))
|
||||||
return NULL;
|
return NULL;
|
||||||
|
|
||||||
|
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
|
||||||
|
clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
|
||||||
|
BUG_ON(!clk_mgr_base_addr);
|
||||||
pll_clk->hw.reg = clk_mgr_base_addr + reg;
|
pll_clk->hw.reg = clk_mgr_base_addr + reg;
|
||||||
|
|
||||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||||
|
|
|
@ -17,28 +17,11 @@
|
||||||
* You should have received a copy of the GNU General Public License
|
* You should have received a copy of the GNU General Public License
|
||||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
#include <linux/clk.h>
|
|
||||||
#include <linux/clkdev.h>
|
|
||||||
#include <linux/clk-provider.h>
|
|
||||||
#include <linux/io.h>
|
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
#include <linux/of_address.h>
|
|
||||||
|
|
||||||
#include "clk.h"
|
#include "clk.h"
|
||||||
|
|
||||||
void __iomem *clk_mgr_base_addr;
|
CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init);
|
||||||
|
CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init);
|
||||||
static const struct of_device_id socfpga_child_clocks[] __initconst = {
|
CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init);
|
||||||
{ .compatible = "altr,socfpga-pll-clock", socfpga_pll_init, },
|
|
||||||
{ .compatible = "altr,socfpga-perip-clk", socfpga_periph_init, },
|
|
||||||
{ .compatible = "altr,socfpga-gate-clk", socfpga_gate_init, },
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init socfpga_clkmgr_init(struct device_node *node)
|
|
||||||
{
|
|
||||||
clk_mgr_base_addr = of_iomap(node, 0);
|
|
||||||
of_clk_init(socfpga_child_clocks);
|
|
||||||
}
|
|
||||||
CLK_OF_DECLARE(socfpga_mgr, "altr,clk-mgr", socfpga_clkmgr_init);
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue