drm/amd/pm: fulfill the OD support for SMU13.0.7
Fulfill the interfaces for OD settings retrieving and setting. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
parent
1718e973e3
commit
2a9aa52e46
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@ -1022,16 +1022,118 @@ static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
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value);
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}
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static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
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int od_feature_bit)
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{
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PPTable_t *pptable = smu->smu_table.driver_pptable;
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const OverDriveLimits_t * const overdrive_upperlimits =
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&pptable->SkuTable.OverDriveLimitsBasicMax;
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return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
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}
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static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
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int od_feature_bit,
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bool lower_boundary,
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int32_t *min,
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int32_t *max)
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{
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PPTable_t *pptable = smu->smu_table.driver_pptable;
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const OverDriveLimits_t * const overdrive_upperlimits =
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&pptable->SkuTable.OverDriveLimitsBasicMax;
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const OverDriveLimits_t * const overdrive_lowerlimits =
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&pptable->SkuTable.OverDriveLimitsMin;
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int32_t od_min_setting, od_max_setting;
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switch (od_feature_bit) {
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case PP_OD_FEATURE_GFXCLK_BIT:
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if (lower_boundary) {
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od_min_setting = overdrive_lowerlimits->GfxclkFmin;
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od_max_setting = overdrive_upperlimits->GfxclkFmin;
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} else {
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od_min_setting = overdrive_lowerlimits->GfxclkFmax;
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od_max_setting = overdrive_upperlimits->GfxclkFmax;
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}
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break;
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case PP_OD_FEATURE_UCLK_BIT:
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if (lower_boundary) {
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od_min_setting = overdrive_lowerlimits->UclkFmin;
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od_max_setting = overdrive_upperlimits->UclkFmin;
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} else {
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od_min_setting = overdrive_lowerlimits->UclkFmax;
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od_max_setting = overdrive_upperlimits->UclkFmax;
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}
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break;
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case PP_OD_FEATURE_GFX_VF_CURVE_BIT:
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od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
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od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
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break;
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default:
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break;
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}
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if (min)
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*min = od_min_setting;
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if (max)
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*max = od_max_setting;
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}
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static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
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OverDriveTableExternal_t *od_table)
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{
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struct amdgpu_device *adev = smu->adev;
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dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
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od_table->OverDriveTable.GfxclkFmax);
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dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
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od_table->OverDriveTable.UclkFmax);
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}
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static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
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OverDriveTableExternal_t *od_table)
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{
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int ret = 0;
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ret = smu_cmn_update_table(smu,
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SMU_TABLE_OVERDRIVE,
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0,
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(void *)od_table,
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false);
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if (ret)
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dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
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return ret;
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}
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static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
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OverDriveTableExternal_t *od_table)
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{
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int ret = 0;
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ret = smu_cmn_update_table(smu,
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SMU_TABLE_OVERDRIVE,
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0,
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(void *)od_table,
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true);
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if (ret)
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dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
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return ret;
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}
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static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type,
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char *buf)
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{
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struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
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struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
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OverDriveTableExternal_t *od_table =
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(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
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struct smu_13_0_dpm_table *single_dpm_table;
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struct smu_13_0_pcie_table *pcie_table;
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uint32_t gen_speed, lane_width;
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int i, curr_freq, size = 0;
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int32_t min_value, max_value;
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int ret = 0;
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smu_cmn_get_sysfs_buf(&buf, &size);
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@ -1148,6 +1250,89 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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"*" : "");
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break;
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case SMU_OD_SCLK:
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if (!smu_v13_0_7_is_od_feature_supported(smu,
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PP_OD_FEATURE_GFXCLK_BIT))
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break;
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size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
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size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
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od_table->OverDriveTable.GfxclkFmin,
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od_table->OverDriveTable.GfxclkFmax);
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break;
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case SMU_OD_MCLK:
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if (!smu_v13_0_7_is_od_feature_supported(smu,
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PP_OD_FEATURE_UCLK_BIT))
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break;
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size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
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size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
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od_table->OverDriveTable.UclkFmin,
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od_table->OverDriveTable.UclkFmax);
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break;
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case SMU_OD_VDDC_CURVE:
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if (!smu_v13_0_7_is_od_feature_supported(smu,
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PP_OD_FEATURE_GFX_VF_CURVE_BIT))
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break;
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size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
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for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
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size += sysfs_emit_at(buf, size, "%d: %dmv\n",
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i,
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od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i]);
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break;
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case SMU_OD_RANGE:
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if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
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!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
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!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
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break;
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size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
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if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFXCLK_BIT,
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true,
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&min_value,
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NULL);
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFXCLK_BIT,
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false,
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NULL,
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&max_value);
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size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
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min_value, max_value);
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}
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if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_UCLK_BIT,
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true,
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&min_value,
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NULL);
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_UCLK_BIT,
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false,
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NULL,
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&max_value);
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size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
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min_value, max_value);
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}
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if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFX_VF_CURVE_BIT,
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true,
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&min_value,
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&max_value);
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size += sysfs_emit_at(buf, size, "VDDC_CURVE: %7dmv %10dmv\n",
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min_value, max_value);
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}
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break;
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default:
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break;
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}
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@ -1155,6 +1340,222 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
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return size;
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}
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static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
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enum PP_OD_DPM_TABLE_COMMAND type,
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long input[],
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uint32_t size)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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OverDriveTableExternal_t *od_table =
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(OverDriveTableExternal_t *)table_context->overdrive_table;
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struct amdgpu_device *adev = smu->adev;
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uint32_t offset_of_featurectrlmask;
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int32_t minimum, maximum;
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uint32_t feature_ctrlmask;
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int i, ret = 0;
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switch (type) {
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case PP_OD_EDIT_SCLK_VDDC_TABLE:
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if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
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dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
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return -ENOTSUPP;
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}
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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dev_info(adev->dev, "invalid number of input parameters %d\n", size);
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return -EINVAL;
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}
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switch (input[i]) {
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case 0:
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFXCLK_BIT,
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true,
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&minimum,
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&maximum);
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if (input[i + 1] < minimum ||
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input[i + 1] > maximum) {
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dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
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input[i + 1], minimum, maximum);
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return -EINVAL;
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}
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od_table->OverDriveTable.GfxclkFmin = input[i + 1];
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od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
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break;
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case 1:
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFXCLK_BIT,
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false,
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&minimum,
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&maximum);
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if (input[i + 1] < minimum ||
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input[i + 1] > maximum) {
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dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
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input[i + 1], minimum, maximum);
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return -EINVAL;
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}
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od_table->OverDriveTable.GfxclkFmax = input[i + 1];
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od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
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break;
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default:
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dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
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dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
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return -EINVAL;
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}
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}
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if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
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dev_err(adev->dev,
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"Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
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(uint32_t)od_table->OverDriveTable.GfxclkFmin,
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(uint32_t)od_table->OverDriveTable.GfxclkFmax);
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return -EINVAL;
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}
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break;
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case PP_OD_EDIT_MCLK_VDDC_TABLE:
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if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
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dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
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return -ENOTSUPP;
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}
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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dev_info(adev->dev, "invalid number of input parameters %d\n", size);
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return -EINVAL;
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}
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switch (input[i]) {
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case 0:
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_UCLK_BIT,
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true,
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&minimum,
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&maximum);
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if (input[i + 1] < minimum ||
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input[i + 1] > maximum) {
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dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
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input[i + 1], minimum, maximum);
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return -EINVAL;
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}
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od_table->OverDriveTable.UclkFmin = input[i + 1];
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od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
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break;
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case 1:
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_UCLK_BIT,
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false,
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&minimum,
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&maximum);
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if (input[i + 1] < minimum ||
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input[i + 1] > maximum) {
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dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
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input[i + 1], minimum, maximum);
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return -EINVAL;
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}
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od_table->OverDriveTable.UclkFmax = input[i + 1];
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od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
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break;
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default:
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dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
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dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
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return -EINVAL;
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}
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}
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if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
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dev_err(adev->dev,
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"Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
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(uint32_t)od_table->OverDriveTable.UclkFmin,
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(uint32_t)od_table->OverDriveTable.UclkFmax);
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return -EINVAL;
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}
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break;
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case PP_OD_EDIT_VDDC_CURVE:
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if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
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dev_warn(adev->dev, "VF curve setting not supported!\n");
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return -ENOTSUPP;
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}
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if (input[0] >= PP_NUM_OD_VF_CURVE_POINTS ||
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input[0] < 0)
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return -EINVAL;
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smu_v13_0_7_get_od_setting_limits(smu,
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PP_OD_FEATURE_GFX_VF_CURVE_BIT,
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true,
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&minimum,
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&maximum);
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if (input[1] < minimum ||
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input[1] > maximum) {
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dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
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input[1], minimum, maximum);
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return -EINVAL;
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}
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od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[input[0]] = input[1];
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od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFX_VF_CURVE_BIT;
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break;
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case PP_OD_RESTORE_DEFAULT_TABLE:
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feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
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memcpy(od_table,
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table_context->boot_overdrive_table,
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sizeof(OverDriveTableExternal_t));
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od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
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fallthrough;
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case PP_OD_COMMIT_DPM_TABLE:
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/*
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* The member below instructs PMFW the settings focused in
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* this single operation.
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* `uint32_t FeatureCtrlMask;`
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* It does not contain actual informations about user's custom
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* settings. Thus we do not cache it.
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*/
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offset_of_featurectrlmask = offsetof(OverDriveTable_t, FeatureCtrlMask);
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if (memcmp(od_table + offset_of_featurectrlmask,
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table_context->user_overdrive_table + offset_of_featurectrlmask,
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sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask)) {
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smu_v13_0_7_dump_od_table(smu, od_table);
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ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
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if (ret) {
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dev_err(adev->dev, "Failed to upload overdrive table!\n");
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return ret;
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}
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od_table->OverDriveTable.FeatureCtrlMask = 0;
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memcpy(table_context->user_overdrive_table + offset_of_featurectrlmask,
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od_table + offset_of_featurectrlmask,
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sizeof(OverDriveTableExternal_t) - offset_of_featurectrlmask);
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if (!memcmp(table_context->user_overdrive_table,
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table_context->boot_overdrive_table,
|
||||
sizeof(OverDriveTableExternal_t)))
|
||||
smu->user_dpm_profile.user_od = false;
|
||||
else
|
||||
smu->user_dpm_profile.user_od = true;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
|
||||
enum smu_clk_type clk_type,
|
||||
uint32_t mask)
|
||||
|
|
@ -1380,49 +1781,6 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
|
|||
return sizeof(struct gpu_metrics_v1_3);
|
||||
}
|
||||
|
||||
static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
|
||||
OverDriveTableExternal_t *od_table)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = smu_cmn_update_table(smu,
|
||||
SMU_TABLE_OVERDRIVE,
|
||||
0,
|
||||
(void *)od_table,
|
||||
false);
|
||||
if (ret)
|
||||
dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
|
||||
OverDriveTableExternal_t *od_table)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = smu_cmn_update_table(smu,
|
||||
SMU_TABLE_OVERDRIVE,
|
||||
0,
|
||||
(void *)od_table,
|
||||
true);
|
||||
if (ret)
|
||||
dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
|
||||
OverDriveTableExternal_t *od_table)
|
||||
{
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
|
||||
dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
|
||||
od_table->OverDriveTable.GfxclkFmax);
|
||||
dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
|
||||
od_table->OverDriveTable.UclkFmax);
|
||||
}
|
||||
|
||||
static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
|
||||
{
|
||||
OverDriveTableExternal_t *od_table =
|
||||
|
|
@ -1886,6 +2244,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
|
|||
.set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
|
||||
.set_default_od_settings = smu_v13_0_7_set_default_od_settings,
|
||||
.restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,
|
||||
.od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,
|
||||
.set_performance_level = smu_v13_0_set_performance_level,
|
||||
.gfx_off_control = smu_v13_0_gfx_off_control,
|
||||
.get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
|
||||
|
|
|
|||
Loading…
Reference in New Issue