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drm/i915: Fixup non-24bpp support for VGA screens on Haswell 

The LPT PCH only supports 8bpc, so we need to force the pipe bpp
to the right value.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2013-04-19 11:24:39 +02:00
parent 996a2239f9
commit 2a7aceecf1
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/i915/intel_crt.c
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@ -214,6 +214,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_SPLIT(dev)) if (HAS_PCH_SPLIT(dev))
pipe_config->has_pch_encoder = true; pipe_config->has_pch_encoder = true;
/* LPT FDI RX only supports 8bpc. */
if (HAS_PCH_LPT(dev))
pipe_config->pipe_bpp = 24;
return true; return true;
} }