Pull fsys_gettimeofday into release branch
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commit
2a467d5f7d
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@ -210,23 +210,21 @@ ENTRY(fsys_gettimeofday)
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// Note that instructions are optimized for McKinley. McKinley can
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// process two bundles simultaneously and therefore we continuously
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// try to feed the CPU two bundles and then a stop.
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//
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// Additional note that code has changed a lot. Optimization is TBD.
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// Comments begin with "?" are maybe outdated.
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tnat.nz p6,p0 = r31 // ? branch deferred to fit later bundle
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mov pr = r30,0xc000 // Set predicates according to function
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add r2 = TI_FLAGS+IA64_TASK_SIZE,r16
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tnat.nz p6,p0 = r31 // guard against Nat argument
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(p6) br.cond.spnt.few .fail_einval
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movl r20 = fsyscall_gtod_data // load fsyscall gettimeofday data address
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;;
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ld4 r2 = [r2] // process work pending flags
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movl r29 = itc_jitter_data // itc_jitter
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add r22 = IA64_GTOD_WALL_TIME_OFFSET,r20 // wall_time
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ld4 r2 = [r2] // process work pending flags
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;;
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(p15) add r22 = IA64_GTOD_MONO_TIME_OFFSET,r20 // monotonic_time
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add r21 = IA64_CLKSRC_MMIO_OFFSET,r20
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add r19 = IA64_ITC_LASTCYCLE_OFFSET,r29
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mov pr = r30,0xc000 // Set predicates according to function
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;;
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and r2 = TIF_ALLWORK_MASK,r2
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(p6) br.cond.spnt.few .fail_einval // ? deferred branch
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add r19 = IA64_ITC_LASTCYCLE_OFFSET,r29
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(p15) add r22 = IA64_GTOD_MONO_TIME_OFFSET,r20 // monotonic_time
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;;
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add r26 = IA64_CLKSRC_CYCLE_LAST_OFFSET,r20 // clksrc_cycle_last
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cmp.ne p6, p0 = 0, r2 // Fallback if work is scheduled
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@ -258,7 +256,6 @@ ENTRY(fsys_gettimeofday)
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(p8) mov r2 = ar.itc // CPU_TIMER. 36 clocks latency!!!
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(p9) ld8 r2 = [r30] // MMIO_TIMER. Could also have latency issues..
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(p13) ld8 r25 = [r19] // get itc_lastcycle value
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;; // ? could be removed by moving the last add upward
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ld8 r9 = [r22],IA64_TIMESPEC_TV_NSEC_OFFSET // tv_sec
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;;
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ld8 r8 = [r22],-IA64_TIMESPEC_TV_NSEC_OFFSET // tv_nsec
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@ -285,13 +282,12 @@ ENTRY(fsys_gettimeofday)
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EX(.fail_efault, probe.w.fault r31, 3)
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xmpy.l f8 = f8,f7 // nsec_per_cyc*(counter-last_counter)
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;;
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// ? simulate tbit.nz.or p7,p0 = r28,0
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getf.sig r2 = f8
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mf
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;;
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ld4 r10 = [r20] // gtod_lock.sequence
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shr.u r2 = r2,r23 // shift by factor
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;; // ? overloaded 3 bundles!
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;;
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add r8 = r8,r2 // Add xtime.nsecs
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cmp4.ne p7,p0 = r28,r10
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(p7) br.cond.dpnt.few .time_redo // sequence number changed, redo
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@ -319,9 +315,9 @@ EX(.fail_efault, probe.w.fault r31, 3)
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EX(.fail_efault, probe.w.fault r23, 3) // This also costs 5 cycles
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(p14) xmpy.hu f8 = f8, f7 // xmpy has 5 cycles latency so use it
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;;
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mov r8 = r0
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(p14) getf.sig r2 = f8
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;;
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mov r8 = r0
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(p14) shr.u r21 = r2, 4
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;;
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EX(.fail_efault, st8 [r31] = r9)
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@ -135,10 +135,10 @@ ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
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while (offp < (s32 *) end) {
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wp = (u64 *) ia64_imva((char *) offp + *offp);
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wp[0] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */
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wp[1] = 0x0004000000000200UL;
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wp[2] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */
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wp[3] = 0x0084006880000200UL;
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wp[0] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */
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wp[1] = 0x0084006880000200UL;
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wp[2] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */
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wp[3] = 0x0004000000000200UL;
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ia64_fc(wp); ia64_fc(wp + 2);
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++offp;
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}
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