arm64: debug: avoid accessing mdscr_el1 on fault paths where possible
Since mdscr_el1 is part of the debug register group, it is highly likely
to be trapped by a hypervisor to prevent virtual machines from debugging
(buggering?) each other. Unfortunately, this absolutely destroys our
performance, since we access the register on many of our low-level
fault handling paths to keep track of the various debug state machines.
This patch removes our dependency on mdscr_el1 in the case that debugging
is not being used. More specifically we:
- Use TIF_SINGLESTEP to indicate that a task is stepping at EL0 and
avoid disabling step in the MDSCR when we don't need to.
MDSCR_EL1.SS handling is moved to kernel_entry, when trapping from
userspace.
- Ensure debug exceptions are re-enabled on *all* exception entry
paths, even the debug exception handling path (where we re-enable
exceptions after invoking the handler). Since we can now rely on
MDSCR_EL1.SS being cleared by the entry code, exception handlers can
usually enable debug immediately before enabling interrupts.
- Remove all debug exception unmasking from ret_to_user and
el1_preempt, since we will never get here with debug exceptions
masked.
This results in a slight change to kernel debug behaviour, where we now
step into interrupt handlers and data aborts from EL1 when debugging the
kernel, which is actually a useful thing to do. A side-effect of this is
that it *does* potentially prevent stepping off {break,watch}points when
there is a high-frequency interrupt source (e.g. a timer), so a debugger
would need to use either breakpoints or manually disable interrupts to
get around this issue.
With this patch applied, guest performance is restored under KVM when
debug register accesses are trapped (and we get a measurable performance
increase on the host on Cortex-A57 too).
Cc: Ian Campbell <ian.campbell@citrix.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon
Catalin Marinas
parent
dc60b777fc
commit
2a2830703a
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@ -21,6 +21,7 @@
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#endif
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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/*
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* Stack pushing/popping (register pairs only). Equivalent to store decrement
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@ -68,23 +69,31 @@
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msr daifclr, #8
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.endm
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.macro disable_step, tmp
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.macro disable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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mrs \tmp, mdscr_el1
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bic \tmp, \tmp, #1
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msr mdscr_el1, \tmp
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isb // Synchronise with enable_dbg
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9990:
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.endm
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.macro enable_step, tmp
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.macro enable_step_tsk, flgs, tmp
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tbz \flgs, #TIF_SINGLESTEP, 9990f
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disable_dbg
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mrs \tmp, mdscr_el1
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orr \tmp, \tmp, #1
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msr mdscr_el1, \tmp
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9990:
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.endm
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.macro enable_dbg_if_not_stepping, tmp
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mrs \tmp, mdscr_el1
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tbnz \tmp, #0, 9990f
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enable_dbg
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9990:
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/*
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* Enable both debug exceptions and interrupts. This is likely to be
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* faster than two daifclr operations, since writes to this register
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* are self-synchronising.
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*/
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.macro enable_dbg_and_irq
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msr daifclr, #(8 | 2)
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.endm
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/*
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@ -60,6 +60,9 @@
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push x0, x1
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.if \el == 0
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mrs x21, sp_el0
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get_thread_info tsk // Ensure MDSCR_EL1.SS is clear,
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ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
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disable_step_tsk x19, x20 // exceptions when scheduling.
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.else
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add x21, sp, #S_FRAME_SIZE
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.endif
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@ -259,7 +262,7 @@ el1_da:
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* Data abort handling
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*/
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mrs x0, far_el1
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enable_dbg_if_not_stepping x2
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enable_dbg
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// re-enable interrupts if they were enabled in the aborted context
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tbnz x23, #7, 1f // PSR_I_BIT
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enable_irq
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@ -275,6 +278,7 @@ el1_sp_pc:
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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enable_dbg
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mov x1, x25
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mov x2, sp
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b do_sp_pc_abort
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@ -282,6 +286,7 @@ el1_undef:
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/*
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* Undefined instruction
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*/
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enable_dbg
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mov x0, sp
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b do_undefinstr
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el1_dbg:
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@ -294,10 +299,11 @@ el1_dbg:
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mrs x0, far_el1
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mov x2, sp // struct pt_regs
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bl do_debug_exception
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enable_dbg
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kernel_exit 1
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el1_inv:
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// TODO: add support for undefined instructions in kernel mode
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enable_dbg
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mov x0, sp
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mov x1, #BAD_SYNC
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mrs x2, esr_el1
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@ -307,7 +313,7 @@ ENDPROC(el1_sync)
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.align 6
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el1_irq:
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kernel_entry 1
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enable_dbg_if_not_stepping x0
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enable_dbg
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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@ -332,8 +338,7 @@ ENDPROC(el1_irq)
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#ifdef CONFIG_PREEMPT
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el1_preempt:
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mov x24, lr
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1: enable_dbg
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bl preempt_schedule_irq // irq en/disable is done inside
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1: bl preempt_schedule_irq // irq en/disable is done inside
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ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
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tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
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ret x24
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@ -349,7 +354,7 @@ el0_sync:
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC64 // SVC in 64-bit state
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b.eq el0_svc
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adr lr, ret_from_exception
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adr lr, ret_to_user
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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@ -378,7 +383,7 @@ el0_sync_compat:
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC32 // SVC in 32-bit state
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b.eq el0_svc_compat
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adr lr, ret_from_exception
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adr lr, ret_to_user
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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@ -423,11 +428,8 @@ el0_da:
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*/
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mrs x0, far_el1
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bic x0, x0, #(0xff << 56)
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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enable_dbg_and_irq
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mov x1, x25
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mov x2, sp
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b do_mem_abort
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@ -436,11 +438,8 @@ el0_ia:
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* Instruction abort handling
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*/
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mrs x0, far_el1
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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enable_dbg_and_irq
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orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
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mov x2, sp
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b do_mem_abort
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@ -448,6 +447,7 @@ el0_fpsimd_acc:
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/*
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* Floating Point or Advanced SIMD access
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*/
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enable_dbg
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mov x0, x25
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mov x1, sp
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b do_fpsimd_acc
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@ -455,6 +455,7 @@ el0_fpsimd_exc:
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/*
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* Floating Point or Advanced SIMD exception
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*/
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enable_dbg
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mov x0, x25
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mov x1, sp
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b do_fpsimd_exc
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@ -463,11 +464,8 @@ el0_sp_pc:
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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enable_dbg_and_irq
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mov x1, x25
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mov x2, sp
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b do_sp_pc_abort
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@ -475,9 +473,9 @@ el0_undef:
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/*
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* Undefined instruction
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*/
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mov x0, sp
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// enable interrupts before calling the main handler
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enable_irq
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enable_dbg_and_irq
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mov x0, sp
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b do_undefinstr
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el0_dbg:
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/*
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@ -485,11 +483,13 @@ el0_dbg:
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*/
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tbnz x24, #0, el0_inv // EL0 only
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mrs x0, far_el1
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disable_step x1
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mov x1, x25
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mov x2, sp
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b do_debug_exception
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bl do_debug_exception
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enable_dbg
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b ret_to_user
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el0_inv:
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enable_dbg
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mov x0, sp
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mov x1, #BAD_SYNC
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mrs x2, esr_el1
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@ -500,15 +500,12 @@ ENDPROC(el0_sync)
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el0_irq:
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kernel_entry 0
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el0_irq_naked:
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disable_step x1
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isb
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enable_dbg
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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irq_handler
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get_thread_info tsk
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_on
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@ -516,14 +513,6 @@ el0_irq_naked:
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b ret_to_user
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ENDPROC(el0_irq)
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/*
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* This is the return code to user mode for abort handlers
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*/
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ret_from_exception:
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get_thread_info tsk
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b ret_to_user
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ENDPROC(ret_from_exception)
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/*
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* Register switch for AArch64. The callee-saved registers need to be saved
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* and restored. On entry:
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@ -563,10 +552,7 @@ ret_fast_syscall:
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ldr x1, [tsk, #TI_FLAGS]
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and x2, x1, #_TIF_WORK_MASK
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cbnz x2, fast_work_pending
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tbz x1, #TIF_SINGLESTEP, fast_exit
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disable_dbg
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enable_step x2
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fast_exit:
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enable_step_tsk x1, x2
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kernel_exit 0, ret = 1
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/*
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@ -585,7 +571,6 @@ work_pending:
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bl do_notify_resume
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b ret_to_user
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work_resched:
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enable_dbg
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bl schedule
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/*
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@ -596,9 +581,7 @@ ret_to_user:
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ldr x1, [tsk, #TI_FLAGS]
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and x2, x1, #_TIF_WORK_MASK
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cbnz x2, work_pending
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tbz x1, #TIF_SINGLESTEP, no_work_pending
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disable_dbg
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enable_step x2
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enable_step_tsk x1, x2
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no_work_pending:
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kernel_exit 0, ret = 0
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ENDPROC(ret_to_user)
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@ -625,12 +608,8 @@ el0_svc:
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mov sc_nr, #__NR_syscalls
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el0_svc_naked: // compat entry point
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stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
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disable_step x16
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isb
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enable_dbg
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enable_irq
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enable_dbg_and_irq
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get_thread_info tsk
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ldr x16, [tsk, #TI_FLAGS] // check for syscall tracing
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tbnz x16, #TIF_SYSCALL_TRACE, __sys_trace // are we tracing syscalls?
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adr lr, ret_fast_syscall // return address
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