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clk: renesas: rzg2l: Simplify multiplication/shift logic 

"a * (1 << b)" == "a << b".

No change in generated code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2022-02-21 17:25:20 +01:00
parent 9d18f81b35
commit 29db30c45f
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/renesas/rzg2l-cpg.c
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@ -289,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
mult = MDIV(val1) + KDIV(val1) / 65536;
div = PDIV(val1) * (1 << SDIV(val2));
div = PDIV(val1) << SDIV(val2);
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
}