clk: ingenic: add JZ4780 CGU support
Add support for the clocks provided by the CGU in the Ingenic JZ4780 SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Co-authored-by: Paul Cercueil <paul@crapouillou.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10157/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
50d893ff72
commit
29136ad581
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@ -1,2 +1,3 @@
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obj-y += cgu.o
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obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o
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obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o
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@ -0,0 +1,733 @@
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/*
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* Ingenic JZ4780 SoC CGU driver
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*
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* Copyright (c) 2013-2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/jz4780-cgu.h>
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#include "cgu.h"
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/* CGU register offsets */
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#define CGU_REG_CLOCKCONTROL 0x00
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#define CGU_REG_PLLCONTROL 0x0c
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#define CGU_REG_APLL 0x10
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#define CGU_REG_MPLL 0x14
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#define CGU_REG_EPLL 0x18
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#define CGU_REG_VPLL 0x1c
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#define CGU_REG_CLKGR0 0x20
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#define CGU_REG_OPCR 0x24
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#define CGU_REG_CLKGR1 0x28
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#define CGU_REG_DDRCDR 0x2c
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#define CGU_REG_VPUCDR 0x30
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#define CGU_REG_USBPCR 0x3c
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#define CGU_REG_USBRDT 0x40
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#define CGU_REG_USBVBFIL 0x44
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#define CGU_REG_USBPCR1 0x48
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#define CGU_REG_LP0CDR 0x54
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LP1CDR 0x64
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#define CGU_REG_MSC0CDR 0x68
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#define CGU_REG_UHCCDR 0x6c
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#define CGU_REG_SSICDR 0x74
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#define CGU_REG_CIMCDR 0x7c
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#define CGU_REG_PCMCDR 0x84
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#define CGU_REG_GPUCDR 0x88
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#define CGU_REG_HDMICDR 0x8c
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#define CGU_REG_MSC1CDR 0xa4
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#define CGU_REG_MSC2CDR 0xa8
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#define CGU_REG_BCHCDR 0xac
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#define CGU_REG_CLOCKSTATUS 0xd4
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/* bits within the OPCR register */
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#define OPCR_SPENDN0 (1 << 7)
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#define OPCR_SPENDN1 (1 << 6)
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/* bits within the USBPCR register */
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#define USBPCR_USB_MODE BIT(31)
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#define USBPCR_IDPULLUP_MASK (0x3 << 28)
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#define USBPCR_COMMONONN BIT(25)
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#define USBPCR_VBUSVLDEXT BIT(24)
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#define USBPCR_VBUSVLDEXTSEL BIT(23)
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#define USBPCR_POR BIT(22)
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#define USBPCR_OTG_DISABLE BIT(20)
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#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
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#define USBPCR_OTGTUNE_MASK (0x7 << 14)
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#define USBPCR_SQRXTUNE_MASK (0x7 << 11)
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#define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
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#define USBPCR_TXPREEMPHTUNE BIT(6)
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#define USBPCR_TXHSXVTUNE_MASK (0x3 << 4)
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#define USBPCR_TXVREFTUNE_MASK 0xf
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/* bits within the USBPCR1 register */
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#define USBPCR1_REFCLKSEL_SHIFT 26
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#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
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#define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
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#define USBPCR1_REFCLKDIV_SHIFT 24
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#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_USB_SEL BIT(28)
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#define USBPCR1_WORD_IF0 BIT(19)
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#define USBPCR1_WORD_IF1 BIT(18)
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/* bits within the USBRDT register */
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#define USBRDT_VBFIL_LD_EN BIT(25)
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#define USBRDT_USBRDT_MASK 0x7fffff
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/* bits within the USBVBFIL register */
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#define USBVBFIL_IDDIGFIL_SHIFT 16
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#define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT)
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#define USBVBFIL_USBVBFIL_MASK (0xffff)
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static struct ingenic_cgu *cgu;
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static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
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{
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/* we only use CLKCORE, revisit if that ever changes */
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return 0;
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}
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static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
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{
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unsigned long flags;
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u32 usbpcr1;
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if (idx > 0)
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return -EINVAL;
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spin_lock_irqsave(&cgu->lock, flags);
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
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/* we only use CLKCORE */
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usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
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writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 usbpcr1;
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unsigned refclk_div;
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
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switch (refclk_div) {
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case USBPCR1_REFCLKDIV_12:
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return 12000000;
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case USBPCR1_REFCLKDIV_24:
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return 24000000;
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case USBPCR1_REFCLKDIV_48:
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return 48000000;
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case USBPCR1_REFCLKDIV_19_2:
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return 19200000;
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}
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BUG();
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return parent_rate;
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}
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static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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if (req_rate < 15600000)
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return 12000000;
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if (req_rate < 21600000)
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return 19200000;
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if (req_rate < 36000000)
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return 24000000;
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return 48000000;
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}
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static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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unsigned long flags;
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u32 usbpcr1, div_bits;
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switch (req_rate) {
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case 12000000:
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div_bits = USBPCR1_REFCLKDIV_12;
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break;
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case 19200000:
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div_bits = USBPCR1_REFCLKDIV_19_2;
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break;
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case 24000000:
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div_bits = USBPCR1_REFCLKDIV_24;
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break;
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case 48000000:
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div_bits = USBPCR1_REFCLKDIV_48;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&cgu->lock, flags);
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
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usbpcr1 |= div_bits;
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writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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static struct clk_ops jz4780_otg_phy_ops = {
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.get_parent = jz4780_otg_phy_get_parent,
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.set_parent = jz4780_otg_phy_set_parent,
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.recalc_rate = jz4780_otg_phy_recalc_rate,
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.round_rate = jz4780_otg_phy_round_rate,
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.set_rate = jz4780_otg_phy_set_rate,
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};
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static const s8 pll_od_encoding[16] = {
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0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
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0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
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};
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static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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/* External clocks */
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[JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
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[JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
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/* PLLs */
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#define DEF_PLL(name) { \
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.reg = CGU_REG_ ## name, \
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.m_shift = 19, \
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.m_bits = 13, \
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.m_offset = 1, \
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.n_shift = 13, \
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.n_bits = 6, \
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.n_offset = 1, \
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.od_shift = 9, \
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.od_bits = 4, \
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.od_max = 16, \
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.od_encoding = pll_od_encoding, \
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.stable_bit = 6, \
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.bypass_bit = 1, \
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.enable_bit = 0, \
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}
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[JZ4780_CLK_APLL] = {
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"apll", CGU_CLK_PLL,
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.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
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.pll = DEF_PLL(APLL),
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},
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[JZ4780_CLK_MPLL] = {
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"mpll", CGU_CLK_PLL,
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.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
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.pll = DEF_PLL(MPLL),
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},
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[JZ4780_CLK_EPLL] = {
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"epll", CGU_CLK_PLL,
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.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
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.pll = DEF_PLL(EPLL),
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},
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[JZ4780_CLK_VPLL] = {
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"vpll", CGU_CLK_PLL,
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.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
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.pll = DEF_PLL(VPLL),
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},
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#undef DEF_PLL
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/* Custom (SoC-specific) OTG PHY */
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[JZ4780_CLK_OTGPHY] = {
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"otg_phy", CGU_CLK_CUSTOM,
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.parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
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.custom = { &jz4780_otg_phy_ops },
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},
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/* Muxes & dividers */
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[JZ4780_CLK_SCLKA] = {
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"sclk_a", CGU_CLK_MUX,
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.parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
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JZ4780_CLK_RTCLK },
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.mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
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},
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[JZ4780_CLK_CPUMUX] = {
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"cpumux", CGU_CLK_MUX,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_EPLL },
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.mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
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},
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[JZ4780_CLK_CPU] = {
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"cpu", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },
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},
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[JZ4780_CLK_L2CACHE] = {
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"l2cache", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },
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},
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[JZ4780_CLK_AHB0] = {
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"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_EPLL },
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.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
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.div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },
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},
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[JZ4780_CLK_AHB2PMUX] = {
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"ahb2_apb_mux", CGU_CLK_MUX,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_RTCLK },
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.mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
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},
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[JZ4780_CLK_AHB2] = {
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"ahb2", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },
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},
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[JZ4780_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },
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},
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[JZ4780_CLK_DDR] = {
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
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.mux = { CGU_REG_DDRCDR, 30, 2 },
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.div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },
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},
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[JZ4780_CLK_VPU] = {
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"vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_EPLL, -1 },
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.mux = { CGU_REG_VPUCDR, 30, 2 },
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.div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR1, 2 },
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},
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[JZ4780_CLK_I2SPLL] = {
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"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
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.mux = { CGU_REG_I2SCDR, 30, 1 },
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.div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },
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},
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[JZ4780_CLK_I2S] = {
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"i2s", CGU_CLK_MUX,
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.parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
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.mux = { CGU_REG_I2SCDR, 31, 1 },
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},
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[JZ4780_CLK_LCD0PIXCLK] = {
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"lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_VPLL, -1 },
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.mux = { CGU_REG_LP0CDR, 30, 2 },
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.div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },
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},
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[JZ4780_CLK_LCD1PIXCLK] = {
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"lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_VPLL, -1 },
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.mux = { CGU_REG_LP1CDR, 30, 2 },
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.div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },
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},
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[JZ4780_CLK_MSCMUX] = {
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"msc_mux", CGU_CLK_MUX,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
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.mux = { CGU_REG_MSC0CDR, 30, 2 },
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},
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[JZ4780_CLK_MSC0] = {
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"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
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.div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR0, 3 },
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},
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[JZ4780_CLK_MSC1] = {
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"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
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.div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },
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||||
.gate = { CGU_REG_CLKGR0, 11 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_MSC2] = {
|
||||
"msc2", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
||||
.div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR0, 12 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UHC] = {
|
||||
"uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||
JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
|
||||
.mux = { CGU_REG_UHCCDR, 30, 2 },
|
||||
.div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR0, 24 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SSIPLL] = {
|
||||
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
||||
.mux = { CGU_REG_SSICDR, 30, 1 },
|
||||
.div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SSI] = {
|
||||
"ssi", CGU_CLK_MUX,
|
||||
.parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
|
||||
.mux = { CGU_REG_SSICDR, 31, 1 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_CIMMCLK] = {
|
||||
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
||||
.mux = { CGU_REG_CIMCDR, 31, 1 },
|
||||
.div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_PCMPLL] = {
|
||||
"pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||
JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
|
||||
.mux = { CGU_REG_PCMCDR, 29, 2 },
|
||||
.div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_PCM] = {
|
||||
"pcm", CGU_CLK_MUX | CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
|
||||
.mux = { CGU_REG_PCMCDR, 31, 1 },
|
||||
.gate = { CGU_REG_CLKGR1, 3 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_GPU] = {
|
||||
"gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||
JZ4780_CLK_EPLL },
|
||||
.mux = { CGU_REG_GPUCDR, 30, 2 },
|
||||
.div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR1, 4 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_HDMI] = {
|
||||
"hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||
JZ4780_CLK_VPLL, -1 },
|
||||
.mux = { CGU_REG_HDMICDR, 30, 2 },
|
||||
.div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },
|
||||
.gate = { CGU_REG_CLKGR1, 9 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_BCH] = {
|
||||
"bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||
JZ4780_CLK_EPLL },
|
||||
.mux = { CGU_REG_BCHCDR, 30, 2 },
|
||||
.div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },
|
||||
.gate = { CGU_REG_CLKGR0, 1 },
|
||||
},
|
||||
|
||||
/* Gate-only clocks */
|
||||
|
||||
[JZ4780_CLK_NEMC] = {
|
||||
"nemc", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 0 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_OTG0] = {
|
||||
"otg0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 2 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SSI0] = {
|
||||
"ssi0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_SSI, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 4 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SMB0] = {
|
||||
"smb0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 5 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SMB1] = {
|
||||
"smb1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 6 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SCC] = {
|
||||
"scc", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 7 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_AIC] = {
|
||||
"aic", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 8 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_TSSI0] = {
|
||||
"tssi0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 9 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_OWI] = {
|
||||
"owi", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 10 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_KBC] = {
|
||||
"kbc", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 13 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SADC] = {
|
||||
"sadc", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 14 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UART0] = {
|
||||
"uart0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 15 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UART1] = {
|
||||
"uart1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 16 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UART2] = {
|
||||
"uart2", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 17 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UART3] = {
|
||||
"uart3", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 18 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SSI1] = {
|
||||
"ssi1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_SSI, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 19 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SSI2] = {
|
||||
"ssi2", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_SSI, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 20 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_PDMA] = {
|
||||
"pdma", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 21 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_GPS] = {
|
||||
"gps", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 22 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_MAC] = {
|
||||
"mac", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 23 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SMB2] = {
|
||||
"smb2", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 24 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_CIM] = {
|
||||
"cim", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 26 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_LCD] = {
|
||||
"lcd", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 28 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_TVE] = {
|
||||
"tve", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_LCD, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 27 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_IPU] = {
|
||||
"ipu", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 29 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_DDR0] = {
|
||||
"ddr0", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_DDR, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 30 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_DDR1] = {
|
||||
"ddr1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_DDR, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR0, 31 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SMB3] = {
|
||||
"smb3", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 0 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_TSSI1] = {
|
||||
"tssi1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 1 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_COMPRESS] = {
|
||||
"compress", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 5 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_AIC1] = {
|
||||
"aic1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 6 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_GPVLC] = {
|
||||
"gpvlc", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 7 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_OTG1] = {
|
||||
"otg1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 8 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_UART4] = {
|
||||
"uart4", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 10 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_AHBMON] = {
|
||||
"ahb_mon", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 11 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_SMB4] = {
|
||||
"smb4", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 12 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_DES] = {
|
||||
"des", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 13 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_X2D] = {
|
||||
"x2d", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 14 },
|
||||
},
|
||||
|
||||
[JZ4780_CLK_CORE1] = {
|
||||
"core1", CGU_CLK_GATE,
|
||||
.parents = { JZ4780_CLK_CPU, -1, -1, -1 },
|
||||
.gate = { CGU_REG_CLKGR1, 15 },
|
||||
},
|
||||
|
||||
};
|
||||
|
||||
static void __init jz4780_cgu_init(struct device_node *np)
|
||||
{
|
||||
int retval;
|
||||
|
||||
cgu = ingenic_cgu_new(jz4780_cgu_clocks,
|
||||
ARRAY_SIZE(jz4780_cgu_clocks), np);
|
||||
if (!cgu) {
|
||||
pr_err("%s: failed to initialise CGU\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
retval = ingenic_cgu_register_clocks(cgu);
|
||||
if (retval) {
|
||||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
}
|
||||
CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
|
||||
Loading…
Reference in New Issue