b43: HT-PHY: Define some regs for 0x2059 radio
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -81,10 +81,10 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
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udelay(50);
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/* Calibration */
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b43_radio_mask(dev, 0x2b, ~0x1);
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b43_radio_mask(dev, 0x2e, ~0x4);
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b43_radio_set(dev, 0x2e, 0x4);
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b43_radio_set(dev, 0x2b, 0x1);
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b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1);
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b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4);
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b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4);
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b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1);
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udelay(300);
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}
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@ -92,20 +92,27 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
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/* Calibrate resistors in LPF of PLL? */
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static void b43_radio_2059_rcal(struct b43_wldev *dev)
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{
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b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
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/* Enable */
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b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1);
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usleep_range(10, 20);
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b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
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b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
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b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
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/* Start */
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b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2);
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usleep_range(100, 200);
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b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
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if (!b43_radio_wait_value(dev, R2059_C3 | 0x145, 1, 1, 100,
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/* Stop */
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b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2);
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if (!b43_radio_wait_value(dev, R2059_C3 | R2059_RCAL_STATUS, 1, 1, 100,
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1000000))
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b43err(dev->wl, "Radio 0x2059 rcal timeout\n");
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b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
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/* Disable */
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b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1);
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b43_radio_set(dev, 0xa, 0x60);
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}
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@ -118,19 +125,23 @@ static void b43_radio_2057_rccal(struct b43_wldev *dev)
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int i;
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for (i = 0; i < 3; i++) {
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b43_radio_write(dev, 0x17F, radio_values[i][0]);
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b43_radio_write(dev, 0x13D, 0x6E);
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b43_radio_write(dev, 0x13E, radio_values[i][1]);
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b43_radio_write(dev, 0x13C, 0x55);
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b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]);
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b43_radio_write(dev, R2059_RCCAL_X1, 0x6E);
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b43_radio_write(dev, R2059_RCCAL_TRC0, radio_values[i][1]);
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if (!b43_radio_wait_value(dev, 0x140, 2, 2,
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/* Start */
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b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55);
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/* Wait */
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if (!b43_radio_wait_value(dev, R2059_RCCAL_DONE_OSCCAP, 2, 2,
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500, 5000000))
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b43err(dev->wl, "Radio 0x2059 rccal timeout\n");
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b43_radio_write(dev, 0x13C, 0x15);
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/* Stop */
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b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15);
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}
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b43_radio_mask(dev, 0x17F, ~0x1);
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b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1);
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}
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static void b43_radio_2059_init_pre(struct b43_wldev *dev)
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@ -155,18 +166,20 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
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for (i = 0; i < ARRAY_SIZE(routing); i++)
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b43_radio_set(dev, routing[i] | 0x146, 0x3);
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b43_radio_set(dev, 0x2e, 0x0078);
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b43_radio_set(dev, 0xc0, 0x0080);
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/* Post init starts below */
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b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078);
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b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080);
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msleep(2);
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b43_radio_mask(dev, 0x2e, ~0x0078);
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b43_radio_mask(dev, 0xc0, ~0x0080);
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b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078);
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b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080);
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if (1) { /* FIXME */
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b43_radio_2059_rcal(dev);
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b43_radio_2057_rccal(dev);
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}
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b43_radio_mask(dev, 0x11, ~0x0008);
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b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008);
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}
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/**************************************************
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@ -10,6 +10,18 @@
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#define R2059_C3 0x800
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#define R2059_ALL 0xC00
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#define R2059_RCAL_CONFIG 0x004
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#define R2059_RFPLL_MASTER 0x011
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#define R2059_RFPLL_MISC_EN 0x02b
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#define R2059_RFPLL_MISC_CAL_RESETN 0x02e
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#define R2059_XTAL_CONFIG2 0x0c0
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#define R2059_RCCAL_START_R1_Q1_P1 0x13c
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#define R2059_RCCAL_X1 0x13d
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#define R2059_RCCAL_TRC0 0x13e
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#define R2059_RCCAL_DONE_OSCCAP 0x140
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#define R2059_RCAL_STATUS 0x145
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#define R2059_RCCAL_MASTER 0x17f
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/* Values for various registers uploaded on channel switching */
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struct b43_phy_ht_channeltab_e_radio2059 {
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/* The channel frequency in MHz */
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