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drm: G33-class hardware has a newer 965-style MCH (no DCC register). 

Fixes bad software fallback rendering in Mesa in dual-channel configurations.

d9a2470012588dc5313a5ac8bb2f03575af00e99

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Eric Anholt 2008-09-15 13:13:34 -07:00 committed by Dave Airlie
parent 4f481ed22e
commit 28af0a2767
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/i915_gem_tiling.c
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@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
*/ */
swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if (!IS_I965G(dev) || IS_I965GM(dev)) { } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
uint32_t dcc; uint32_t dcc;
/* On 915-945 and GM965, channel interleave by the CPU is /* On 915-945 and GM965, channel interleave by the CPU is