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Pin control changes for the v6.5 kernel cycle: 

No core changes this time.
 
 New drivers:
 
 - Tegra234 support.
 
 - Qualcomm IPQ5018 support.
 
 - Intel Meteor Lake-S support.
 
 - Qualcomm SDX75 subdriver.
 
 - Qualcomm SPMI-based PM8953 support.
 
 Improvements:
 
 - Fix up support for GPIO3 on the AXP209.
 
 - Push-pull drive configuration support for the AT91 PIO4.
 
 - Fix misc non-urgent bugs in the AMD driver.
 
 - Misc non-urgent improved error handling.
 
 - Misc janitorial and minor improvements.
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Merge tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "No core changes this time

  New drivers:

   - Tegra234 support

   - Qualcomm IPQ5018 support

   - Intel Meteor Lake-S support

   - Qualcomm SDX75 subdriver

   - Qualcomm SPMI-based PM8953 support

  Improvements:

   - Fix up support for GPIO3 on the AXP209

   - Push-pull drive configuration support for the AT91 PIO4

   - Fix misc non-urgent bugs in the AMD driver

   - Misc non-urgent improved error handling

   - Misc janitorial and minor improvements"

* tag 'pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
  pinctrl: cherryview: Drop goto label
  pinctrl: baytrail: invert if condition
  pinctrl: baytrail: add warning for BYT_VAL_REG retrieval failure
  pinctrl: baytrail: reduce scope of spinlock in ->dbg_show() hook
  pinctrl: tegra: avoid duplicate field initializers
  dt-bindings: pinctrl: qcom,sdx65-tlmm: add pcie_clkreq function
  pinctrl: mlxbf3: remove broken Kconfig 'select'
  pinctrl: spear: Remove unused of_gpio.h inclusion
  pinctrl: lantiq: Remove unused of_gpio.h inclusion
  pinctrl: at91-pio4: check return value of devm_kasprintf()
  pinctrl: microchip-sgpio: check return value of devm_kasprintf()
  pinctrl: freescale: Fix a memory out of bounds when num_configs is 1
  pinctrl: intel: refine ->irq_set_type() hook
  pinctrl: intel: refine ->set_mux() hook
  pinctrl: baytrail: Use str_hi_lo() helper
  lib/string_choices: Add str_high_low() helper
  lib/string_helpers: Split out string_choices.h
  lib/string_helpers: Add missing header files to MAINTAINERS database
  pinctrl: npcm7xx: Add missing check for ioremap
  pinctrl:sunplus: Add check for kmalloc
  ...
This commit is contained in:
Linus Torvalds 2023-06-30 14:57:19 -07:00
parent 9c3255a8f3 9f0648f13e
commit 28968f384b
112 changed files with 11641 additions and 7405 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
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@ -37,7 +37,8 @@ right representation of the pin.
Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use:
- bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
input-schmitt-enable, input-debounce, output-low, output-high.
drive-push-pull input-schmitt-enable, input-debounce, output-low,
output-high.
- for microchip,sama7g5-pinctrl only:
- slew-rate: 0 - disabled, 1 - enabled (default)
- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for

78
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml Normal file
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@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra234 AON Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
$ref: nvidia,tegra234-pinmux-common.yaml
properties:
compatible:
const: nvidia,tegra234-pinmux-aon
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
properties:
nvidia,pins:
items:
enum: [ can0_dout_paa0, can0_din_paa1, can1_dout_paa2,
can1_din_paa3, can0_stb_paa4, can0_en_paa5,
soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0,
can1_en_pbb1, soc_gpio50_pbb2, can1_err_pbb3,
spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
sce_error_pee0, vcomp_alert_pee1,
ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
soc_gpio26_pee5, soc_gpio27_pee6, bootv_ctl_n_pee7,
hdmi_cec_pgg0,
# drive groups
drive_touch_clk_pcc4, drive_uart3_rx_pcc6,
drive_uart3_tx_pcc5, drive_gen8_i2c_sda_pdd2,
drive_gen8_i2c_scl_pdd1, drive_spi2_mosi_pcc2,
drive_gen2_i2c_scl_pcc7, drive_spi2_cs0_pcc3,
drive_gen2_i2c_sda_pdd0, drive_spi2_sck_pcc0,
drive_spi2_miso_pcc1, drive_can1_dout_paa2,
drive_can1_din_paa3, drive_can0_dout_paa0,
drive_can0_din_paa1, drive_can0_stb_paa4,
drive_can0_en_paa5, drive_soc_gpio49_paa6,
drive_can0_err_paa7, drive_can1_stb_pbb0,
drive_can1_en_pbb1, drive_soc_gpio50_pbb2,
drive_can1_err_pbb3, drive_sce_error_pee0,
drive_batt_oc_pee3, drive_bootv_ctl_n_pee7,
drive_power_on_pee4, drive_soc_gpio26_pee5,
drive_soc_gpio27_pee6, drive_ao_retention_n_pee2,
drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@c300000 {
compatible = "nvidia,tegra234-pinmux-aon";
reg = <0xc300000 0x4000>;
pinctrl-names = "cec";
pinctrl-0 = <&cec_state>;
cec_state: pinmux-cec {
cec {
nvidia,pins = "hdmi_cec_pgg0";
nvidia,function = "gp";
};
};
};
...

66
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml Normal file
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@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra234 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
reg:
items:
- description: pinmux registers
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra-pinmux-common.yaml
# We would typically use unevaluatedProperties here but that has the
# downside that all the properties in the common bindings become valid
# for all chip generations. In this case, however, we want the per-SoC
# bindings to be able to override which of the common properties are
# allowed, since not all pinmux generations support the same sets of
# properties. This way, the common bindings define the format of the
# properties but the per-SoC bindings define which of them apply to a
# given chip.
additionalProperties: false
properties:
nvidia,function:
enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2,
eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3,
pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi,
sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte,
usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd,
i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4,
ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb,
displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3,
tsc_alt, istctrl, vi1_alt, dspk1, igpu ]
# out of the common properties, only these are allowed for Tegra234
nvidia,pins: true
nvidia,pull: true
nvidia,tristate: true
nvidia,schmitt: true
nvidia,enable-input: true
nvidia,open-drain: true
nvidia,lock: true
nvidia,drive-type: true
nvidia,io-hv: true
required:
- nvidia,pins
required:
- compatible
- reg
additionalProperties: true
...

139
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml Normal file
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@ -0,0 +1,139 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra234 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
$ref: nvidia,tegra234-pinmux-common.yaml
properties:
compatible:
const: nvidia,tegra234-pinmux
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
properties:
nvidia,pins:
items:
enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
dap4_din_pa6, dap4_fs_pa7, soc_gpio08_pb0,
qspi0_sck_pc0, qspi0_cs_n_pc1,
qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
soc_gpio13_pg0, soc_gpio14_pg1, soc_gpio15_pg2,
soc_gpio16_pg3, soc_gpio17_pg4, soc_gpio18_pg5,
soc_gpio19_pg6, soc_gpio20_pg7, soc_gpio21_ph0,
soc_gpio22_ph1, soc_gpio06_ph2, uart4_tx_ph3,
uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
soc_gpio41_ph7, soc_gpio42_pi0, soc_gpio43_pi1,
soc_gpio44_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
cpu_pwr_req_pi5, soc_gpio07_pi6,
sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
pex_wake_n_pl2, soc_gpio34_pl3, dp_aux_ch0_hpd_pm0,
dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
dp_aux_ch3_hpd_pm3, soc_gpio55_pm4, soc_gpio36_pm5,
soc_gpio53_pm6, soc_gpio38_pm7, dp_aux_ch3_n_pn0,
soc_gpio39_pn1, soc_gpio40_pn2, dp_aux_ch1_p_pn3,
dp_aux_ch1_n_pn4, dp_aux_ch2_p_pn5, dp_aux_ch2_n_pn6,
dp_aux_ch3_p_pn7, extperiph1_clk_pp0,
extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
soc_gpio23_pp4, soc_gpio24_pp5, soc_gpio25_pp6,
pwr_i2c_scl_pp7, pwr_i2c_sda_pq0, soc_gpio28_pq1,
soc_gpio29_pq2, soc_gpio30_pq3, soc_gpio31_pq4,
soc_gpio32_pq5, soc_gpio33_pq6, soc_gpio35_pq7,
soc_gpio37_pr0, soc_gpio56_pr1, uart1_tx_pr2,
uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
soc_gpio61_pw0, soc_gpio62_pw1, gpu_pwr_req_px0,
cv_pwr_req_px1, gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4,
uart2_rx_px5, uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
spi5_sck_pac0, spi5_miso_pac1, spi5_mosi_pac2,
spi5_cs0_pac3, soc_gpio57_pac4, soc_gpio58_pac5,
soc_gpio59_pac6, soc_gpio60_pac7, soc_gpio45_pad0,
soc_gpio46_pad1, soc_gpio47_pad2, soc_gpio48_pad3,
ufs0_ref_clk_pae0, ufs0_rst_n_pae1,
pex_l5_clkreq_n_paf0, pex_l5_rst_n_paf1,
pex_l6_clkreq_n_paf2, pex_l6_rst_n_paf3,
pex_l7_clkreq_n_pag0, pex_l7_rst_n_pag1,
pex_l8_clkreq_n_pag2, pex_l8_rst_n_pag3,
pex_l9_clkreq_n_pag4, pex_l9_rst_n_pag5,
pex_l10_clkreq_n_pag6, pex_l10_rst_n_pag7,
sdmmc1_comp, eqos_comp, qspi_comp,
# drive groups
drive_soc_gpio08_pb0, drive_soc_gpio36_pm5,
drive_soc_gpio53_pm6, drive_soc_gpio55_pm4,
drive_soc_gpio38_pm7, drive_soc_gpio39_pn1,
drive_soc_gpio40_pn2, drive_dp_aux_ch0_hpd_pm0,
drive_dp_aux_ch1_hpd_pm1, drive_dp_aux_ch2_hpd_pm2,
drive_dp_aux_ch3_hpd_pm3, drive_dp_aux_ch1_p_pn3,
drive_dp_aux_ch1_n_pn4, drive_dp_aux_ch2_p_pn5,
drive_dp_aux_ch2_n_pn6, drive_dp_aux_ch3_p_pn7,
drive_dp_aux_ch3_n_pn0, drive_pex_l2_clkreq_n_pk4,
drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
drive_soc_gpio34_pl3, drive_pex_l5_clkreq_n_paf0,
drive_pex_l5_rst_n_paf1, drive_pex_l6_clkreq_n_paf2,
drive_pex_l6_rst_n_paf3, drive_pex_l10_clkreq_n_pag6,
drive_pex_l10_rst_n_pag7, drive_pex_l7_clkreq_n_pag0,
drive_pex_l7_rst_n_pag1, drive_pex_l8_clkreq_n_pag2,
drive_pex_l8_rst_n_pag3, drive_pex_l9_clkreq_n_pag4,
drive_pex_l9_rst_n_pag5, drive_sdmmc1_clk_pj0,
drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
drive_sdmmc1_dat0_pj2 ]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@2430000 {
compatible = "nvidia,tegra234-pinmux";
reg = <0x2430000 0x17000>;
pinctrl-names = "pex_rst";
pinctrl-0 = <&pex_rst_c5_out_state>;
pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
pexrst {
nvidia,pins = "pex_l5_rst_n_paf1";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
};
};
...

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Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml Normal file
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@ -0,0 +1,127 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ5018 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description:
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
properties:
compatible:
const: qcom,ipq5018-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 24
gpio-line-names:
maxItems: 47
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq5018-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq5018-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq5018-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
minItems: 1
maxItems: 8
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
required:
- pins
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 47>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
uart-w-state {
rx-pins {
pins = "gpio33";
function = "blsp1_uart1";
bias-pull-down;
};
tx-pins {
pins = "gpio34";
function = "blsp1_uart1";
bias-pull-down;
};
};
};
...

11
Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
View File

@ -53,6 +53,7 @@ $defs:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
@ -86,19 +87,9 @@ $defs:
rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
wci20, wci21, wsa_swrm ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

3
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View File

@ -49,6 +49,7 @@ properties:
- qcom,pm8921-gpio
- qcom,pm8941-gpio
- qcom,pm8950-gpio
- qcom,pm8953-gpio
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
@ -175,6 +176,7 @@ allOf:
- qcom,pm8350b-gpio
- qcom,pm8550ve-gpio
- qcom,pm8950-gpio
- qcom,pm8953-gpio
- qcom,pmi632-gpio
then:
properties:
@ -434,6 +436,7 @@ $defs:
- gpio1-gpio44 for pm8921
- gpio1-gpio36 for pm8941
- gpio1-gpio8 for pm8950 (hole on gpio3)
- gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6)
- gpio1-gpio22 for pm8994
- gpio1-gpio26 for pm8998
- gpio1-gpio22 for pma8084

11
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml
View File

@ -45,6 +45,7 @@ $defs:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
@ -81,19 +82,9 @@ $defs:
uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
vsense_trigger, wlan1_adc0, wlan1_adc1 ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

12
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
View File

@ -55,6 +55,7 @@ $defs:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
@ -104,20 +105,9 @@ $defs:
usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
vsense_trigger ]
bias-bus-hold: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

2
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml
View File

@ -85,7 +85,7 @@ $defs:
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, pcie_clkreq,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,

137
Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml Normal file
View File

@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SDX75 TLMM block
maintainers:
- Rohit Agarwal <quic_rohiagar@quicinc.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sdx75-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
gpio-reserved-ranges:
minItems: 1
maxItems: 67
gpio-line-names:
maxItems: 133
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sdx75-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sdx75-tlmm-state"
additionalProperties: false
$defs:
qcom-sdx75-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2,
coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist,
ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg,
emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc,
eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk,
gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist,
ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens,
native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e,
pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync,
pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss,
qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira,
qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3,
qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc,
rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb,
sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n,
spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1,
tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
usb2phy_ac_en, vsense_trigger_mirnat]
required:
- pins
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,sdx75-tlmm";
reg = <0x0f100000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 133>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-state {
rx-pins {
pins = "gpio12";
function = "qup_se1_l2_mira";
bias-disable;
};
tx-pins {
pins = "gpio13";
function = "qup_se1_l3_mira";
bias-disable;
};
};
};
...

11
Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml
View File

@ -62,6 +62,7 @@ $defs:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
@ -102,19 +103,9 @@ $defs:
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
wsa_data ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
required:
- compatible
- reg

6
MAINTAINERS
View File

@ -2947,7 +2947,6 @@ F: Documentation/devicetree/bindings/arm/ti/k3.yaml
F: Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
F: include/dt-bindings/pinctrl/k3.h
ARM/TOSHIBA VISCONTI ARCHITECTURE
M: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
@ -8719,6 +8718,9 @@ F: drivers/input/touchscreen/resistive-adc-touch.c
GENERIC STRING LIBRARY
R: Andy Shevchenko <andy@kernel.org>
S: Maintained
F: include/linux/string.h
F: include/linux/string_choices.h
F: include/linux/string_helpers.h
F: lib/string.c
F: lib/string_helpers.c
F: lib/test-string_helpers.c
@ -16794,7 +16796,7 @@ PIN CONTROLLER - QUALCOMM
M: Bjorn Andersson <andersson@kernel.org>
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt
F: Documentation/devicetree/bindings/pinctrl/qcom,*
F: drivers/pinctrl/qcom/
PIN CONTROLLER - RENESAS

12
drivers/gpio/gpio-tegra186.c
View File

@ -964,11 +964,15 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
np = of_find_matching_node(NULL, tegra186_pmc_of_match);
if (np) {
irq->parent_domain = irq_find_host(np);
of_node_put(np);
if (of_device_is_available(np)) {
irq->parent_domain = irq_find_host(np);
of_node_put(np);
if (!irq->parent_domain)
return -EPROBE_DEFER;
if (!irq->parent_domain)
return -EPROBE_DEFER;
} else {
of_node_put(np);
}
}
irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,

1
drivers/pinctrl/Kconfig
View File

@ -510,7 +510,6 @@ config PINCTRL_MLXBF3
select PINMUX
select GPIOLIB
select GPIOLIB_IRQCHIP
select GPIO_MLXBF3
help
Say Y to select the pinctrl driver for BlueField-3 SoCs.
This pin controller allows selecting the mux function for

2
drivers/pinctrl/Makefile
View File

@ -66,7 +66,7 @@ obj-y += nomadik/
obj-y += nuvoton/
obj-y += nxp/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-y += qcom/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/

6
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -376,10 +376,8 @@ static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
if (!pctldev)
return 0;
gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
gc->ngpio);
return 0;
return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
gc->ngpio);
}
static const struct gpio_chip bcm2835_gpio_chip = {

3
drivers/pinctrl/freescale/pinctrl-scu.c
View File

@ -90,7 +90,7 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
struct imx_sc_msg_req_pad_set msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
unsigned int mux = configs[0];
unsigned int conf = configs[1];
unsigned int conf;
unsigned int val;
int ret;
@ -115,6 +115,7 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
* Set mux and conf together in one IPC call
*/
WARN_ON(num_configs != 2);
conf = configs[1];
val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
val |= mux << BP_PAD_CTL_IFMUX;

108
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -18,6 +18,7 @@
#include <linux/pm_runtime.h>
#include <linux/property.h>
#include <linux/seq_file.h>
#include <linux/string_helpers.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@ -52,10 +53,9 @@
#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
#define BYT_PULL_ASSIGN_SHIFT 7
#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
#define BYT_PULL_ASSIGN_DOWN BIT(8)
#define BYT_PULL_ASSIGN_UP BIT(7)
#define BYT_PIN_MUX GENMASK(2, 0)
/* BYT_VAL_REG register bits */
@ -668,8 +668,7 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
dev_warn(vg->dev,
"Group %s, pin %i not muxed (no padcfg0)\n",
dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
@ -698,8 +697,7 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
dev_warn(vg->dev,
"Group %s, pin %i not muxed (no padcfg0)\n",
dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
@ -755,9 +753,7 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off
value = readl(reg);
/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
if (value & BYT_DIRECT_IRQ_EN)
/* nothing to do */ ;
else
if (!(value & BYT_DIRECT_IRQ_EN))
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
writel(value, reg);
@ -791,7 +787,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
value |= gpio_mux;
writel(value, reg);
dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
@ -823,7 +819,9 @@ static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
* themselves in the foot.
*/
if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
dev_info_once(vg->dev,
"Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
offset);
}
static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
@ -1026,9 +1024,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
dev_warn(vg->dev,
"pin %u forcibly set to input mode\n",
offset);
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
@ -1048,9 +1044,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
dev_warn(vg->dev,
"pin %u forcibly set to input mode\n",
offset);
dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
@ -1245,39 +1239,35 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
for (i = 0; i < vg->soc->npins; i++) {
const struct intel_community *comm;
void __iomem *conf_reg, *val_reg;
const char *pull_str = NULL;
const char *pull = NULL;
void __iomem *reg;
unsigned long flags;
const char *label;
unsigned int pin;
raw_spin_lock_irqsave(&byt_lock, flags);
pin = vg->soc->pins[i].number;
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i conf0 reg\n",
pin);
raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
conf0 = readl(reg);
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
if (!reg) {
seq_printf(s,
"Could not retrieve pin %i val reg\n", pin);
raw_spin_unlock_irqrestore(&byt_lock, flags);
conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!conf_reg) {
seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
continue;
}
val = readl(reg);
val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
if (!val_reg) {
seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
continue;
}
raw_spin_lock_irqsave(&byt_lock, flags);
conf0 = readl(conf_reg);
val = readl(val_reg);
raw_spin_unlock_irqrestore(&byt_lock, flags);
comm = byt_get_community(vg, pin);
if (!comm) {
seq_printf(s,
"Could not get community for pin %i\n", pin);
seq_printf(s, "Pin %i: can't retrieve community\n", pin);
continue;
}
label = gpiochip_is_requested(chip, i);
@ -1314,7 +1304,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
label,
val & BYT_INPUT_EN ? " " : "in",
val & BYT_OUTPUT_EN ? " " : "out",
val & BYT_LEVEL ? "hi" : "lo",
str_hi_lo(val & BYT_LEVEL),
comm->pad_map[i], comm->pad_map[i] * 16,
conf0 & 0x7,
conf0 & BYT_TRIG_NEG ? " fall" : " ",
@ -1429,7 +1419,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
"Bad pad config for io mode, force direct_irq_en bit clearing");
"Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
* are used to indicate high and low level triggering
@ -1476,9 +1466,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
dev_warn(vg->dev,
"Pin %i: could not retrieve interrupt status register\n",
base);
dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
@ -1501,7 +1489,7 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
sizeof(direct_irq_mux));
match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
if (!match) {
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
return false;
}
@ -1528,7 +1516,8 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
trig = conf0 & BYT_TRIG_MASK;
if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
dev_warn(vg->dev,
FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
pin, conf0);
return false;
}
@ -1555,9 +1544,7 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
dev_warn(vg->dev,
"Pin %i: could not retrieve conf0 register\n",
i);
dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
continue;
}
@ -1588,9 +1575,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
dev_warn(vg->dev,
"Pin %i: could not retrieve irq status reg\n",
base);
dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
@ -1600,7 +1585,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
value = readl(reg);
if (value)
dev_err(vg->dev,
"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
"GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
base / 32, value);
}
@ -1764,15 +1749,17 @@ static int byt_gpio_suspend(struct device *dev)
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
dev_warn(vg->dev,
"Pin %i: could not retrieve conf0 register\n",
i);
dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
vg->context.pads[i].conf0 = value;
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
if (!reg) {
dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
continue;
}
value = readl(reg) & BYT_VAL_RESTORE_MASK;
vg->context.pads[i].val = value;
}
@ -1796,9 +1783,7 @@ static int byt_gpio_resume(struct device *dev)
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
dev_warn(vg->dev,
"Pin %i: could not retrieve conf0 register\n",
i);
dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg);
@ -1807,10 +1792,14 @@ static int byt_gpio_resume(struct device *dev)
value &= ~BYT_CONF0_RESTORE_MASK;
value |= vg->context.pads[i].conf0;
writel(value, reg);
dev_info(dev, "restored pin %d conf0 %#08x", i, value);
dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
}
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
if (!reg) {
dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
continue;
}
value = readl(reg);
if ((value & BYT_VAL_RESTORE_MASK) !=
vg->context.pads[i].val) {
@ -1820,8 +1809,7 @@ static int byt_gpio_resume(struct device *dev)
v |= vg->context.pads[i].val;
if (v != value) {
writel(v, reg);
dev_dbg(dev, "restored pin %d val %#08x\n",
i, v);
dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
}
}
}

26
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -75,7 +75,7 @@ struct intel_pad_context {
u32 padctrl1;
};
#define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ)
#define CHV_INVALID_HWIRQ (~0U)
/**
* struct intel_community_context - community context for Cherryview
@ -949,11 +949,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
return -EINVAL;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
u32 cfg;
@ -963,6 +958,16 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (ctrl1 & CHV_PADCTRL1_ODEN)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
return -EINVAL;
break;
}
default:
@ -1408,8 +1413,10 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
raw_spin_lock_irqsave(&chv_lock, flags);
ret = chv_gpio_set_intr_line(pctrl, hwirq);
if (ret)
goto out_unlock;
if (ret) {
raw_spin_unlock_irqrestore(&chv_lock, flags);
return ret;
}
/*
* Pins which can be used as shared interrupt are configured in
@ -1450,10 +1457,9 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
out_unlock:
raw_spin_unlock_irqrestore(&chv_lock, flags);
return ret;
return 0;
}
static const struct irq_chip chv_gpio_irq_chip = {

54
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -55,12 +55,11 @@
/* Offset from pad_regs */
#define PADCFG0 0x000
#define PADCFG0_RXEVCFG_SHIFT 25
#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
#define PADCFG0_RXEVCFG_LEVEL 0
#define PADCFG0_RXEVCFG_EDGE 1
#define PADCFG0_RXEVCFG_DISABLED 2
#define PADCFG0_RXEVCFG_EDGE_BOTH 3
#define PADCFG0_RXEVCFG_LEVEL (0 << 25)
#define PADCFG0_RXEVCFG_EDGE (1 << 25)
#define PADCFG0_RXEVCFG_DISABLED (2 << 25)
#define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25)
#define PADCFG0_PREGFRXSEL BIT(24)
#define PADCFG0_RXINV BIT(23)
#define PADCFG0_GPIROUTIOXAPIC BIT(20)
@ -411,18 +410,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
/* Now enable the mux setting for each pin in the group */
for (i = 0; i < grp->grp.npins; i++) {
void __iomem *padcfg0;
u32 value;
u32 value, pmode;
padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
value = readl(padcfg0);
value = readl(padcfg0);
value &= ~PADCFG0_PMODE_MASK;
if (grp->modes)
value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
pmode = grp->modes[i];
else
value |= grp->mode << PADCFG0_PMODE_SHIFT;
pmode = grp->mode;
value |= pmode << PADCFG0_PMODE_SHIFT;
writel(value, padcfg0);
}
@ -1126,9 +1126,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
u32 rxevcfg, rxinv, value;
unsigned long flags;
void __iomem *reg;
u32 value;
reg = intel_get_padcfg(pctrl, pin, PADCFG0);
if (!reg)
@ -1144,27 +1144,31 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
return -EPERM;
}
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
} else if (type & IRQ_TYPE_EDGE_FALLING) {
rxevcfg = PADCFG0_RXEVCFG_EDGE;
} else if (type & IRQ_TYPE_EDGE_RISING) {
rxevcfg = PADCFG0_RXEVCFG_EDGE;
} else if (type & IRQ_TYPE_LEVEL_MASK) {
rxevcfg = PADCFG0_RXEVCFG_LEVEL;
} else {
rxevcfg = PADCFG0_RXEVCFG_DISABLED;
}
if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
rxinv = PADCFG0_RXINV;
else
rxinv = 0;
raw_spin_lock_irqsave(&pctrl->lock, flags);
intel_gpio_set_gpio_mode(reg);
value = readl(reg);
value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
} else if (type & IRQ_TYPE_EDGE_FALLING) {
value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
value |= PADCFG0_RXINV;
} else if (type & IRQ_TYPE_EDGE_RISING) {
value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
} else if (type & IRQ_TYPE_LEVEL_MASK) {
if (type & IRQ_TYPE_LEVEL_LOW)
value |= PADCFG0_RXINV;
} else {
value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
}
value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
value = (value & ~PADCFG0_RXINV) | rxinv;
writel(value, reg);

16
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@ -549,7 +549,7 @@ static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
}
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
if (!mode)
if (mode == BUFCFG_PINMODE_GPIO)
seq_puts(s, "GPIO ");
else
seq_printf(s, "mode %d ", mode);
@ -710,6 +710,11 @@ static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (value & BUFCFG_OD_EN)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(value & BUFCFG_OD_EN))
return -EINVAL;
@ -791,10 +796,14 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
mask |= BUFCFG_OD_EN;
bits &= ~BUFCFG_OD_EN;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
mask |= BUFCFG_OD_EN;
if (arg)
bits |= BUFCFG_OD_EN;
bits |= BUFCFG_OD_EN;
break;
case PIN_CONFIG_SLEW_RATE:
@ -826,6 +835,7 @@ static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_DRIVE_PUSH_PULL:
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
case PIN_CONFIG_SLEW_RATE:
ret = mrfld_config_set_pin(mp, pin, configs[i]);

212
drivers/pinctrl/intel/pinctrl-meteorlake.c
View File

@ -20,6 +20,12 @@
#define MTL_P_GPI_IS 0x200
#define MTL_P_GPI_IE 0x210
#define MTL_S_PAD_OWN 0x0b0
#define MTL_S_PADCFGLOCK 0x0f0
#define MTL_S_HOSTSW_OWN 0x110
#define MTL_S_GPI_IS 0x200
#define MTL_S_GPI_IE 0x210
#define MTL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
@ -28,9 +34,12 @@
.gpio_base = (g), \
}
#define MTL_COMMUNITY(b, s, e, g) \
#define MTL_P_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
#define MTL_S_COMMUNITY(b, s, e, g) \
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_S)
/* Meteor Lake-P */
static const struct pinctrl_pin_desc mtlp_pins[] = {
/* CPU */
@ -369,11 +378,11 @@ static const struct intel_padgroup mtlp_community5_gpps[] = {
};
static const struct intel_community mtlp_communities[] = {
MTL_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
MTL_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
MTL_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
MTL_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
MTL_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
MTL_P_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
MTL_P_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
MTL_P_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
MTL_P_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
MTL_P_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
};
static const struct intel_pinctrl_soc_data mtlp_soc_data = {
@ -383,8 +392,199 @@ static const struct intel_pinctrl_soc_data mtlp_soc_data = {
.ncommunities = ARRAY_SIZE(mtlp_communities),
};
/* Meteor Lake-S */
static const struct pinctrl_pin_desc mtls_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "DIR_ESPI_IO_0"),
PINCTRL_PIN(1, "DIR_ESPI_IO_1"),
PINCTRL_PIN(2, "DIR_ESPI_IO_2"),
PINCTRL_PIN(3, "DIR_ESPI_IO_3"),
PINCTRL_PIN(4, "DIR_ESPI_CS0_B"),
PINCTRL_PIN(5, "DIR_ESPI_CLK"),
PINCTRL_PIN(6, "DIR_ESPI_RCLK"),
PINCTRL_PIN(7, "DIR_ESPI_RESET_B"),
PINCTRL_PIN(8, "SLP_S0_B"),
PINCTRL_PIN(9, "DMI_PERSTB"),
PINCTRL_PIN(10, "CATERR_B"),
PINCTRL_PIN(11, "THERMTRIP_B"),
PINCTRL_PIN(12, "CPU_C10_GATE_B"),
PINCTRL_PIN(13, "PS_ONB"),
PINCTRL_PIN(14, "GPP_SA_14"),
PINCTRL_PIN(15, "GPP_SA_15"),
PINCTRL_PIN(16, "GPP_SA_16"),
PINCTRL_PIN(17, "GPP_SA_17"),
PINCTRL_PIN(18, "GPP_SA_18"),
PINCTRL_PIN(19, "GPP_SA_19"),
PINCTRL_PIN(20, "GPP_SA_20"),
PINCTRL_PIN(21, "GPP_SA_21"),
PINCTRL_PIN(22, "FUSA_DIAGTEST_EN"),
PINCTRL_PIN(23, "FUSA_DIAGTEST_MODE"),
PINCTRL_PIN(24, "RTCCLKIN"),
PINCTRL_PIN(25, "RESET_SYNC_B"),
PINCTRL_PIN(26, "PCH_PWROK"),
PINCTRL_PIN(27, "DIR_ESPI_CLK_LOOPBACK"),
/* vGPIO_0 */
PINCTRL_PIN(28, "LPC_ME_FTPM_ENABLE"),
PINCTRL_PIN(29, "LPC_DTFUS_CORE_SPITPM_DIS"),
PINCTRL_PIN(30, "LPC_SPI_STRAP_TOS"),
PINCTRL_PIN(31, "ITSS_KU1_SHTDWN"),
PINCTRL_PIN(32, "LPC_PRR_TS_OVR"),
PINCTRL_PIN(33, "ESPI_PMC_EC_SCI"),
PINCTRL_PIN(34, "ESPI_PMC_EC_SCI1"),
PINCTRL_PIN(35, "vGPIO_SPARE0"),
PINCTRL_PIN(36, "vGPIO_SPARE1"),
PINCTRL_PIN(37, "vGPIO_SPARE2"),
PINCTRL_PIN(38, "vGPIO_SPARE3"),
PINCTRL_PIN(39, "vGPIO_SPARE8"),
PINCTRL_PIN(40, "vGPIO_SPARE9"),
PINCTRL_PIN(41, "vGPIO_SPARE10"),
PINCTRL_PIN(42, "vGPIO_SPARE11"),
PINCTRL_PIN(43, "vGPIO_SPARE12"),
PINCTRL_PIN(44, "vGPIO_SPARE13"),
PINCTRL_PIN(45, "vGPIO_SPARE14"),
PINCTRL_PIN(46, "vGPIO_SPARE15"),
/* GPP_C */
PINCTRL_PIN(47, "GPP_SC_0"),
PINCTRL_PIN(48, "GPP_SC_1"),
PINCTRL_PIN(49, "GPP_SC_2"),
PINCTRL_PIN(50, "GPP_SC_3"),
PINCTRL_PIN(51, "GPP_SC_4"),
PINCTRL_PIN(52, "GPP_SC_5"),
PINCTRL_PIN(53, "GPP_SC_6"),
PINCTRL_PIN(54, "GPP_SC_7"),
PINCTRL_PIN(55, "GPP_SC_8"),
PINCTRL_PIN(56, "GPP_SC_9"),
PINCTRL_PIN(57, "GPP_SC_10"),
PINCTRL_PIN(58, "GPP_SC_11"),
PINCTRL_PIN(59, "GPP_SC_12"),
PINCTRL_PIN(60, "GPP_SC_13"),
PINCTRL_PIN(61, "GPP_SC_14"),
PINCTRL_PIN(62, "GPP_SC_15"),
PINCTRL_PIN(63, "GPP_SC_16"),
PINCTRL_PIN(64, "GPP_SC_17"),
PINCTRL_PIN(65, "GPP_SC_18"),
PINCTRL_PIN(66, "GPP_SC_19"),
PINCTRL_PIN(67, "GPP_SC_20"),
PINCTRL_PIN(68, "GPP_SC_21"),
PINCTRL_PIN(69, "GPP_SC_22"),
PINCTRL_PIN(70, "GPP_SC_23"),
PINCTRL_PIN(71, "GPP_SC_24"),
PINCTRL_PIN(72, "GPP_SC_25"),
PINCTRL_PIN(73, "GPP_SC_26"),
/* GPP_B */
PINCTRL_PIN(74, "GPP_SB_0"),
PINCTRL_PIN(75, "GPP_SB_1"),
PINCTRL_PIN(76, "GPP_SB_2"),
PINCTRL_PIN(77, "GPP_SB_3"),
PINCTRL_PIN(78, "GPP_SB_4"),
PINCTRL_PIN(79, "GPP_SB_5"),
PINCTRL_PIN(80, "GPP_SB_6"),
PINCTRL_PIN(81, "GPP_SB_7"),
PINCTRL_PIN(82, "GPP_SB_8"),
PINCTRL_PIN(83, "GPP_SB_9"),
PINCTRL_PIN(84, "GPP_SB_10"),
PINCTRL_PIN(85, "GPP_SB_11"),
PINCTRL_PIN(86, "GPP_SB_12"),
PINCTRL_PIN(87, "GPP_SB_13"),
PINCTRL_PIN(88, "GPP_SB_14"),
PINCTRL_PIN(89, "GPP_SB_15"),
PINCTRL_PIN(90, "GPP_SB_16"),
PINCTRL_PIN(91, "PROCHOT_B"),
PINCTRL_PIN(92, "BPKI3C_SDA"),
PINCTRL_PIN(93, "BPKI3C_SCL"),
/* vGPIO_3 */
PINCTRL_PIN(94, "TS0_IN_INT"),
PINCTRL_PIN(95, "TS1_IN_INT"),
/* GPP_D */
PINCTRL_PIN(96, "TIME_SYNC_0"),
PINCTRL_PIN(97, "TIME_SYNC_1"),
PINCTRL_PIN(98, "DSI_DE_TE_2_GENLOCK_REF"),
PINCTRL_PIN(99, "DSI_DE_TE_1_DISP_UTILS"),
PINCTRL_PIN(100, "DSI_GENLOCK_2"),
PINCTRL_PIN(101, "DSI_GENLOCK_3"),
PINCTRL_PIN(102, "SRCCLKREQ2_B"),
PINCTRL_PIN(103, "SRCCLKREQ3_B"),
PINCTRL_PIN(104, "GPP_SD_8"),
PINCTRL_PIN(105, "GPP_SD_9"),
PINCTRL_PIN(106, "GPP_SD_10"),
PINCTRL_PIN(107, "GPP_SD_11"),
PINCTRL_PIN(108, "GPP_SD_12"),
PINCTRL_PIN(109, "GPP_SD_13"),
PINCTRL_PIN(110, "GPP_SD_14"),
PINCTRL_PIN(111, "GPP_SD_15"),
PINCTRL_PIN(112, "GPP_SD_16"),
PINCTRL_PIN(113, "GPP_SD_17"),
PINCTRL_PIN(114, "BOOTHALT_B"),
PINCTRL_PIN(115, "GPP_SD_19"),
PINCTRL_PIN(116, "GPP_SD_20"),
PINCTRL_PIN(117, "AUDCLK"),
PINCTRL_PIN(118, "AUDIN"),
PINCTRL_PIN(119, "AUDOUT"),
/* JTAG_CPU */
PINCTRL_PIN(120, "PECI"),
PINCTRL_PIN(121, "VIDSOUT"),
PINCTRL_PIN(122, "VIDSCK"),
PINCTRL_PIN(123, "VIDALERT_B"),
PINCTRL_PIN(124, "JTAG_MBPB0"),
PINCTRL_PIN(125, "JTAG_MBPB1"),
PINCTRL_PIN(126, "JTAG_MBPB2"),
PINCTRL_PIN(127, "JTAG_MBPB3"),
PINCTRL_PIN(128, "JTAG_TDO"),
PINCTRL_PIN(129, "PRDY_B"),
PINCTRL_PIN(130, "PREQ_B"),
PINCTRL_PIN(131, "JTAG_TDI"),
PINCTRL_PIN(132, "JTAG_TMS"),
PINCTRL_PIN(133, "JTAG_TCK"),
PINCTRL_PIN(134, "DBG_PMODE"),
PINCTRL_PIN(135, "JTAG_TRST_B"),
/* vGPIO_4 */
PINCTRL_PIN(136, "ISCLK_ESPI_XTAL_CLKREQ"),
PINCTRL_PIN(137, "ESPI_ISCLK_XTAL_CLKACK"),
PINCTRL_PIN(138, "vGPIO_SPARE4"),
PINCTRL_PIN(139, "vGPIO_SPARE5"),
PINCTRL_PIN(140, "vGPIO_SPARE6"),
PINCTRL_PIN(141, "vGPIO_SPARE7"),
PINCTRL_PIN(142, "vGPIO_SPARE16"),
PINCTRL_PIN(143, "vGPIO_SPARE17"),
PINCTRL_PIN(144, "vGPIO_SPARE18"),
PINCTRL_PIN(145, "vGPIO_SPARE19"),
PINCTRL_PIN(146, "vGPIO_SPARE20"),
PINCTRL_PIN(147, "vGPIO_SPARE21"),
};
static const struct intel_padgroup mtls_community0_gpps[] = {
MTL_GPP(0, 0, 27, 0), /* GPP_A */
MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */
MTL_GPP(2, 47, 73, 64), /* GPP_C */
};
static const struct intel_padgroup mtls_community1_gpps[] = {
MTL_GPP(0, 74, 93, 96), /* GPP_B */
MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */
MTL_GPP(2, 96, 119, 160), /* GPP_D */
};
static const struct intel_padgroup mtls_community3_gpps[] = {
MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */
MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */
};
static const struct intel_community mtls_communities[] = {
MTL_S_COMMUNITY(0, 0, 73, mtls_community0_gpps),
MTL_S_COMMUNITY(1, 74, 119, mtls_community1_gpps),
MTL_S_COMMUNITY(2, 120, 147, mtls_community3_gpps),
};
static const struct intel_pinctrl_soc_data mtls_soc_data = {
.pins = mtls_pins,
.npins = ARRAY_SIZE(mtls_pins),
.communities = mtls_communities,
.ncommunities = ARRAY_SIZE(mtls_communities),
};
static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
{ "INTC1082", (kernel_ulong_t)&mtls_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);

16
drivers/pinctrl/intel/pinctrl-moorefield.c
View File

@ -504,7 +504,7 @@ static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
}
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
if (!mode)
if (mode == BUFCFG_PINMODE_GPIO)
seq_puts(s, "GPIO ");
else
seq_printf(s, "mode %d ", mode);
@ -661,6 +661,11 @@ static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (value & BUFCFG_OD_EN)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (!(value & BUFCFG_OD_EN))
return -EINVAL;
@ -734,10 +739,14 @@ static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin,
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
mask |= BUFCFG_OD_EN;
bits &= ~BUFCFG_OD_EN;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
mask |= BUFCFG_OD_EN;
if (arg)
bits |= BUFCFG_OD_EN;
bits |= BUFCFG_OD_EN;
break;
case PIN_CONFIG_SLEW_RATE:
@ -769,6 +778,7 @@ static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_DRIVE_PUSH_PULL:
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
case PIN_CONFIG_SLEW_RATE:
ret = mofld_config_set_pin(mp, pin, configs[i]);

2
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -1884,6 +1884,8 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
}
pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));
if (!pctrl->gpio_bank[id].base)
return -EINVAL;
ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,

14
drivers/pinctrl/nxp/pinctrl-s32.h
View File

@ -34,24 +34,28 @@ struct s32_pin_range {
unsigned int end;
};
struct s32_pinctrl_soc_info {
struct device *dev;
struct s32_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
unsigned int npins;
const struct s32_pin_range *mem_pin_ranges;
unsigned int mem_regions;
};
struct s32_pinctrl_soc_info {
struct device *dev;
const struct s32_pinctrl_soc_data *soc_data;
struct s32_pin_group *groups;
unsigned int ngroups;
struct pinfunction *functions;
unsigned int nfunctions;
unsigned int grp_index;
const struct s32_pin_range *mem_pin_ranges;
unsigned int mem_regions;
};
#define S32_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
#define S32_PIN_RANGE(_start, _end) { .start = _start, .end = _end }
int s32_pinctrl_probe(struct platform_device *pdev,
struct s32_pinctrl_soc_info *info);
const struct s32_pinctrl_soc_data *soc_data);
int s32_pinctrl_resume(struct device *dev);
int s32_pinctrl_suspend(struct device *dev);
#endif /* __DRIVERS_PINCTRL_S32_H */

42
drivers/pinctrl/nxp/pinctrl-s32cc.c
View File

@ -106,7 +106,7 @@ s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin)
{
struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct s32_pin_range *pin_range;
unsigned int mem_regions = ipctl->info->mem_regions;
unsigned int mem_regions = ipctl->info->soc_data->mem_regions;
unsigned int i;
for (i = 0; i < mem_regions; i++) {
@ -279,8 +279,10 @@ static int s32_dt_node_to_map(struct pinctrl_dev *pctldev,
ret = s32_dt_group_node_to_map(pctldev, np, map,
&reserved_maps, num_maps,
np_config->name);
if (ret < 0)
if (ret < 0) {
of_node_put(np);
break;
}
}
if (ret)
@ -688,8 +690,8 @@ int s32_pinctrl_suspend(struct device *dev)
int ret;
unsigned int config;
for (i = 0; i < info->npins; i++) {
pin = &info->pins[i];
for (i = 0; i < info->soc_data->npins; i++) {
pin = &info->soc_data->pins[i];
if (!s32_pinctrl_should_save(ipctl, pin->number))
continue;
@ -713,8 +715,8 @@ int s32_pinctrl_resume(struct device *dev)
struct s32_pinctrl_context *saved_context = &ipctl->saved_context;
int ret, i;
for (i = 0; i < info->npins; i++) {
pin = &info->pins[i];
for (i = 0; i < info->soc_data->npins; i++) {
pin = &info->soc_data->pins[i];
if (!s32_pinctrl_should_save(ipctl, pin->number))
continue;
@ -812,8 +814,10 @@ static int s32_pinctrl_parse_functions(struct device_node *np,
groups[i] = child->name;
grp = &info->groups[info->grp_index++];
ret = s32_pinctrl_parse_groups(child, grp, info);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
i++;
}
@ -831,7 +835,7 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
struct resource *res;
struct regmap *map;
void __iomem *base;
int mem_regions = info->mem_regions;
unsigned int mem_regions = info->soc_data->mem_regions;
int ret;
u32 nfuncs = 0;
u32 i = 0;
@ -869,7 +873,7 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
}
ipctl->regions[i].map = map;
ipctl->regions[i].pin_range = &info->mem_pin_ranges[i];
ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i];
}
nfuncs = of_get_child_count(np);
@ -896,28 +900,36 @@ static int s32_pinctrl_probe_dt(struct platform_device *pdev,
i = 0;
for_each_child_of_node(np, child) {
ret = s32_pinctrl_parse_functions(child, info, i++);
if (ret)
if (ret) {
of_node_put(child);
return ret;
}
}
return 0;
}
int s32_pinctrl_probe(struct platform_device *pdev,
struct s32_pinctrl_soc_info *info)
const struct s32_pinctrl_soc_data *soc_data)
{
struct s32_pinctrl *ipctl;
int ret;
struct pinctrl_desc *s32_pinctrl_desc;
struct s32_pinctrl_soc_info *info;
#ifdef CONFIG_PM_SLEEP
struct s32_pinctrl_context *saved_context;
#endif
if (!info || !info->pins || !info->npins) {
if (!soc_data || !soc_data->pins || !soc_data->npins) {
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
if (!info)
return -ENOMEM;
info->soc_data = soc_data;
info->dev = &pdev->dev;
/* Create state holders etc for this driver */
@ -938,8 +950,8 @@ int s32_pinctrl_probe(struct platform_device *pdev,
return -ENOMEM;
s32_pinctrl_desc->name = dev_name(&pdev->dev);
s32_pinctrl_desc->pins = info->pins;
s32_pinctrl_desc->npins = info->npins;
s32_pinctrl_desc->pins = info->soc_data->pins;
s32_pinctrl_desc->npins = info->soc_data->npins;
s32_pinctrl_desc->pctlops = &s32_pctrl_ops;
s32_pinctrl_desc->pmxops = &s32_pmx_ops;
s32_pinctrl_desc->confops = &s32_pinconf_ops;
@ -960,7 +972,7 @@ int s32_pinctrl_probe(struct platform_device *pdev,
#ifdef CONFIG_PM_SLEEP
saved_context = &ipctl->saved_context;
saved_context->pads =
devm_kcalloc(&pdev->dev, info->npins,
devm_kcalloc(&pdev->dev, info->soc_data->npins,
sizeof(*saved_context->pads),
GFP_KERNEL);
if (!saved_context->pads)

14
drivers/pinctrl/nxp/pinctrl-s32g2.c
View File

@ -721,7 +721,7 @@ static const struct s32_pin_range s32_pin_ranges_siul2[] = {
S32_PIN_RANGE(942, 1007),
};
static struct s32_pinctrl_soc_info s32_pinctrl_info = {
static const struct s32_pinctrl_soc_data s32_pinctrl_data = {
.pins = s32_pinctrl_pads_siul2,
.npins = ARRAY_SIZE(s32_pinctrl_pads_siul2),
.mem_pin_ranges = s32_pin_ranges_siul2,
@ -730,9 +730,8 @@ static struct s32_pinctrl_soc_info s32_pinctrl_info = {
static const struct of_device_id s32_pinctrl_of_match[] = {
{
.compatible = "nxp,s32g2-siul2-pinctrl",
.data = (void *) &s32_pinctrl_info,
.data = &s32_pinctrl_data,
},
{ /* sentinel */ }
};
@ -740,14 +739,11 @@ MODULE_DEVICE_TABLE(of, s32_pinctrl_of_match);
static int s32g_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(s32_pinctrl_of_match, &pdev->dev);
const struct s32_pinctrl_soc_data *soc_data;
if (!of_id)
return -ENODEV;
soc_data = of_device_get_match_data(&pdev->dev);
return s32_pinctrl_probe
(pdev, (struct s32_pinctrl_soc_info *) of_id->data);
return s32_pinctrl_probe(pdev, soc_data);
}
static const struct dev_pm_ops s32g_pinctrl_pm_ops = {

50
drivers/pinctrl/pinctrl-amd.c
View File

@ -126,6 +126,12 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
/* Use special handling for Pin0 debounce */
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
debounce = 0;
pin_reg = readl(gpio_dev->base + offset * 4);
if (debounce) {
@ -220,6 +226,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
char *debounce_enable;
char *wake_cntrlz;
seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
unsigned int time = 0;
unsigned int unit = 0;
@ -653,21 +660,21 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_domain_irq() above.
* If we didn't find a mapping for the interrupt,
* disable it in order to avoid a system hang caused
* by an interrupt storm.
* If the line is not an irq, disable it in order to
* avoid a system hang caused by an interrupt storm.
*/
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
regval = readl(regs + i);
if (irq == 0) {
regval &= ~BIT(INTERRUPT_ENABLE_OFF);
if (!gpiochip_line_is_irq(gc, irqnr + i)) {
regval &= ~BIT(INTERRUPT_MASK_OFF);
dev_dbg(&gpio_dev->pdev->dev,
"Disabling spurious GPIO IRQ %d\n",
irqnr + i);
} else {
ret = true;
}
writel(regval, regs + i);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
ret = true;
}
}
/* did not cause wake on resume context for shared IRQ */
@ -870,34 +877,6 @@ static const struct pinconf_ops amd_pinconf_ops = {
.pin_config_group_set = amd_pinconf_group_set,
};
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
{
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags;
u32 pin_reg, mask;
int i;
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
BIT(WAKE_CNTRL_OFF_S4);
for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number;
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
if (!pd)
continue;
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + i * 4);
pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + i * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
}
#ifdef CONFIG_PM_SLEEP
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
{
@ -1135,9 +1114,6 @@ static int amd_gpio_probe(struct platform_device *pdev)
return PTR_ERR(gpio_dev->pctrl);
}
/* Disable and mask interrupts */
amd_gpio_irq_init(gpio_dev);
girq = &gpio_dev->gc.irq;
gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
/* This will let us handle the parent IRQ in the driver */

1
drivers/pinctrl/pinctrl-amd.h
View File

@ -17,6 +17,7 @@
#define AMD_GPIO_PINS_BANK3 32
#define WAKE_INT_MASTER_REG 0xfc
#define INTERNAL_GPIO0_DEBOUNCE (1 << 15)
#define EOI_MASK (1 << 29)
#define WAKE_INT_STATUS_REG0 0x2f8

17
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -762,6 +762,11 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
if (res & ATMEL_PIO_OPD_MASK)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (!(res & ATMEL_PIO_SCHMITT_MASK))
return -EINVAL;
@ -827,10 +832,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
conf &= (~ATMEL_PIO_PUEN_MASK);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
if (arg == 0)
conf &= (~ATMEL_PIO_OPD_MASK);
else
conf |= ATMEL_PIO_OPD_MASK;
conf |= ATMEL_PIO_OPD_MASK;
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
conf &= ~ATMEL_PIO_OPD_MASK;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
if (arg == 0)
@ -948,6 +953,8 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, "%s ", "debounce");
if (conf & ATMEL_PIO_OPD_MASK)
seq_printf(s, "%s ", "open-drain");
else
seq_printf(s, "%s ", "push-pull");
if (conf & ATMEL_PIO_SCHMITT_MASK)
seq_printf(s, "%s ", "schmitt");
if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
@ -1146,6 +1153,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
/* Pin naming convention: P(bank_name)(bank_pin_number). */
pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%u",
bank + 'A', line);
if (!pin_desc[i].name)
return -ENOMEM;
group->name = group_names[i] = pin_desc[i].name;
group->pin = pin_desc[i].number;

8
drivers/pinctrl/pinctrl-at91.c
View File

@ -1389,8 +1389,8 @@ static int at91_pinctrl_probe(struct platform_device *pdev)
char **names;
names = devm_kasprintf_strarray(dev, "pio", MAX_NB_GPIO_PER_BANK);
if (!names)
return -ENOMEM;
if (IS_ERR(names))
return PTR_ERR(names);
for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
char *name = names[j];
@ -1870,8 +1870,8 @@ static int at91_gpio_probe(struct platform_device *pdev)
}
names = devm_kasprintf_strarray(dev, "pio", chip->ngpio);
if (!names)
return -ENOMEM;
if (IS_ERR(names))
return PTR_ERR(names);
for (i = 0; i < chip->ngpio; i++)
strreplace(names[i], '-', alias_idx + 'A');

42
drivers/pinctrl/pinctrl-axp209.c
View File

@ -30,6 +30,11 @@
#define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
#define AXP20X_GPIO_FUNCTION_INPUT 2
#define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
#define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
#define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
#define AXP20X_GPIO3_FUNCTION_INPUT 4
#define AXP20X_FUNC_GPIO_OUT 0
#define AXP20X_FUNC_GPIO_IN 1
#define AXP20X_FUNC_LDO 2
@ -73,6 +78,7 @@ static const struct pinctrl_pin_desc axp209_pins[] = {
PINCTRL_PIN(0, "GPIO0"),
PINCTRL_PIN(1, "GPIO1"),
PINCTRL_PIN(2, "GPIO2"),
PINCTRL_PIN(3, "GPIO3"),
};
static const struct pinctrl_pin_desc axp22x_pins[] = {
@ -130,6 +136,14 @@ static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
unsigned int val;
int ret;
/* AXP209 has GPIO3 status sharing the settings register */
if (offset == 3) {
ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
if (ret)
return ret;
return !!(val & BIT(0));
}
ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
if (ret)
return ret;
@ -144,6 +158,17 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
unsigned int val;
int reg, ret;
/* AXP209 GPIO3 settings have a different layout */
if (offset == 3) {
ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
if (ret)
return ret;
if (val & AXP20X_GPIO3_FUNCTION_INPUT)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;
@ -184,6 +209,15 @@ static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
int reg;
/* AXP209 has GPIO3 status sharing the settings register */
if (offset == 3) {
regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
AXP20X_GPIO3_FUNCTIONS,
value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
AXP20X_GPIO3_FUNCTION_OUT_LOW);
return;
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return;
@ -200,6 +234,14 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
int reg;
/* AXP209 GPIO3 settings have a different layout */
if (offset == 3) {
return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
AXP20X_GPIO3_FUNCTIONS,
config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
AXP20X_GPIO3_FUNCTION_INPUT);
}
reg = axp20x_gpio_get_reg(offset);
if (reg < 0)
return reg;

2
drivers/pinctrl/pinctrl-cy8c95x0.c
View File

@ -1442,7 +1442,7 @@ static struct i2c_driver cy8c95x0_driver = {
.of_match_table = cy8c95x0_dt_ids,
.acpi_match_table = cy8c95x0_acpi_ids,
},
.probe_new = cy8c95x0_probe,
.probe = cy8c95x0_probe,
.remove = cy8c95x0_remove,
.id_table = cy8c95x0_id,
.detect = cy8c95x0_detect,

1
drivers/pinctrl/pinctrl-falcon.c
View File

@ -14,7 +14,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>

2
drivers/pinctrl/pinctrl-mcp23s08_i2c.c
View File

@ -101,7 +101,7 @@ static struct i2c_driver mcp230xx_driver = {
.name = "mcp230xx",
.of_match_table = mcp23s08_i2c_of_match,
},
.probe_new = mcp230xx_probe,
.probe = mcp230xx_probe,
.id_table = mcp230xx_id,
};

5
drivers/pinctrl/pinctrl-microchip-sgpio.c
View File

@ -719,8 +719,6 @@ static void microchip_sgpio_irq_ack(struct irq_data *data)
static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
{
type &= IRQ_TYPE_SENSE_MASK;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
irq_set_handler_locked(data, handle_edge_irq);
@ -818,6 +816,9 @@ static int microchip_sgpio_register_bank(struct device *dev,
pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
dev_name(dev),
bank->is_input ? "in" : "out");
if (!pctl_desc->name)
return -ENOMEM;
pctl_desc->pctlops = &sgpio_pctl_ops;
pctl_desc->pmxops = &sgpio_pmx_ops;
pctl_desc->confops = &sgpio_confops;

2
drivers/pinctrl/pinctrl-sx150x.c
View File

@ -1262,7 +1262,7 @@ static struct i2c_driver sx150x_driver = {
.name = "sx150x-pinctrl",
.of_match_table = sx150x_of_match,
},
.probe_new = sx150x_probe,
.probe = sx150x_probe,
.id_table = sx150x_id,
};

2
drivers/pinctrl/pinctrl-xway.c
View File

@ -8,11 +8,11 @@
*/
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/device.h>

15
drivers/pinctrl/pinmux.c
View File

@ -677,7 +677,6 @@ void pinmux_show_setting(struct seq_file *s,
DEFINE_SHOW_ATTRIBUTE(pinmux_functions);
DEFINE_SHOW_ATTRIBUTE(pinmux_pins);
#define PINMUX_SELECT_MAX 128
static ssize_t pinmux_select(struct file *file, const char __user *user_buf,
size_t len, loff_t *ppos)
{
@ -689,17 +688,9 @@ static ssize_t pinmux_select(struct file *file, const char __user *user_buf,
unsigned int num_groups;
int fsel, gsel, ret;
if (len > PINMUX_SELECT_MAX)
return -ENOMEM;
buf = kzalloc(PINMUX_SELECT_MAX, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = strncpy_from_user(buf, user_buf, PINMUX_SELECT_MAX);
if (ret < 0)
goto exit_free_buf;
buf[len-1] = '\0';
buf = memdup_user_nul(user_buf, len);
if (IS_ERR(buf))
return PTR_ERR(buf);
/* remove leading and trailing spaces of input buffer */
gname = strstrip(buf);

537
drivers/pinctrl/qcom/Kconfig
View File

@ -4,6 +4,8 @@ if (ARCH_QCOM || COMPILE_TEST)
config PINCTRL_MSM
tristate "Qualcomm core pin controller driver"
depends on GPIOLIB
# OF for pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF
depends on OF
select QCOM_SCM
select PINMUX
select PINCONF
@ -12,231 +14,7 @@ config PINCTRL_MSM
select IRQ_DOMAIN_HIERARCHY
select IRQ_FASTEOI_HIERARCHY_HANDLERS
config PINCTRL_APQ8064
tristate "Qualcomm APQ8064 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
config PINCTRL_APQ8084
tristate "Qualcomm APQ8084 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
config PINCTRL_IPQ5332
tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc IPQ5332 platform.
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ8074 platform. Select this for
IPQ8074.
config PINCTRL_IPQ6018
tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ6018 platform. Select this for
IPQ6018.
config PINCTRL_IPQ9574
tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
depends on OF || COMPILE_TEST
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ9574 platform. Select this for
IPQ9574.
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc MSM8226 platform.
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8660 platform.
config PINCTRL_MSM8960
tristate "Qualcomm 8960 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform.
config PINCTRL_MDM9607
tristate "Qualcomm 9607 pin controller driver"
depends on GPIOLIB && OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9607 platform.
config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9615 platform.
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8974 platform.
config PINCTRL_MSM8909
tristate "Qualcomm 8909 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8909 platform.
config PINCTRL_MSM8916
tristate "Qualcomm 8916 pin controller driver"
depends on OF
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm 8916 platform.
config PINCTRL_MSM8953
tristate "Qualcomm 8953 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8953 platform.
The Qualcomm APQ8053, SDM450, SDM632 platforms are also
supported by this driver.
config PINCTRL_MSM8976
tristate "Qualcomm 8976 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8976 platform.
The Qualcomm MSM8956, APQ8056, APQ8076 platforms are also
supported by this driver.
config PINCTRL_MSM8994
tristate "Qualcomm 8994 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8994 platform. The
Qualcomm 8992 platform is also supported by this driver.
config PINCTRL_MSM8996
tristate "Qualcomm MSM8996 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
config PINCTRL_MSM8998
tristate "Qualcomm MSM8998 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
config PINCTRL_QCM2290
tristate "Qualcomm QCM2290 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
TLMM block found in the Qualcomm QCM2290 platform.
config PINCTRL_QCS404
tristate "Qualcomm QCS404 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
TLMM block found in the Qualcomm QCS404 platform.
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on ACPI
depends on PINCTRL_MSM
help
This is the GPIO driver for the TLMM block found on the
Qualcomm Technologies QDF2xxx SOCs.
source "drivers/pinctrl/qcom/Kconfig.msm"
config PINCTRL_QCOM_SPMI_PMIC
tristate "Qualcomm SPMI PMIC pin controller driver"
@ -245,7 +23,7 @@ config PINCTRL_QCOM_SPMI_PMIC
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB
select GPIOLIB_IRQCHIP
select IRQ_DOMAIN_HIERARCHY
help
@ -260,7 +38,7 @@ config PINCTRL_QCOM_SSBI_PMIC
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB
select GPIOLIB_IRQCHIP
select IRQ_DOMAIN_HIERARCHY
help
@ -269,265 +47,6 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
config PINCTRL_QDU1000
tristate "Qualcomm Tehcnologies Inc QDU1000/QRU1000 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf, and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc QDU1000 and QRU1000 platforms.
config PINCTRL_SA8775P
tristate "Qualcomm Technologies Inc SA8775P pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux and pinconf driver for the Qualcomm
TLMM block found on the Qualcomm SA8775P platforms.
config PINCTRL_SC7180
tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
config PINCTRL_SC7280
tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7280 platform.
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC8180x platform.
config PINCTRL_SC8280XP
tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC8280xp platform.
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM660 platform.
config PINCTRL_SDM670
tristate "Qualcomm Technologies Inc SDM670 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM670 platform.
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM845 platform.
config PINCTRL_SDX55
tristate "Qualcomm Technologies Inc SDX55 pin controller driver"
depends on OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX55 platform.
config PINCTRL_SM6115
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6115 and SM4250 platforms.
config PINCTRL_SM6125
tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6125 platform.
config PINCTRL_SM6350
tristate "Qualcomm Technologies Inc SM6350 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6350 platform.
config PINCTRL_SM6375
tristate "Qualcomm Technologies Inc SM6375 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6375 platform.
config PINCTRL_SDX65
tristate "Qualcomm Technologies Inc SDX65 pin controller driver"
depends on GPIOLIB && OF
depends on ARM || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX65 platform.
config PINCTRL_SM7150
tristate "Qualcomm Technologies Inc SM7150 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM7150 platform.
config PINCTRL_SM8150
tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8150 platform.
config PINCTRL_SM8250
tristate "Qualcomm Technologies Inc SM8250 pin controller driver"
depends on OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
config PINCTRL_SM8250_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
config PINCTRL_SM8350
tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8350 platform.
config PINCTRL_SM8450
tristate "Qualcomm Technologies Inc SM8450 pin controller driver"
depends on GPIOLIB && OF
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8450 platform.
config PINCTRL_SM8450_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform.
config PINCTRL_SC8280XP_LPASS_LPI
tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform.
config PINCTRL_SM8550
tristate "Qualcomm Technologies Inc SM8550 pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8550 platform.
config PINCTRL_SM8550_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver"
depends on GPIOLIB
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8550
platform.
config PINCTRL_LPASS_LPI
tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
select PINMUX
@ -540,4 +59,50 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
config PINCTRL_SC7280_LPASS_LPI
tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
config PINCTRL_SM8250_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
config PINCTRL_SM8450_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8450 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8450 platform.
config PINCTRL_SC8280XP_LPASS_LPI
tristate "Qualcomm Technologies Inc SC8280XP LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC8280XP platform.
config PINCTRL_SM8550_LPASS_LPI
tristate "Qualcomm Technologies Inc SM8550 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_LPASS_LPI
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8550
platform.
endif

369
drivers/pinctrl/qcom/Kconfig.msm Normal file
View File

@ -0,0 +1,369 @@
# SPDX-License-Identifier: GPL-2.0-only
if PINCTRL_MSM
config PINCTRL_APQ8064
tristate "Qualcomm APQ8064 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
config PINCTRL_APQ8084
tristate "Qualcomm APQ8084 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
config PINCTRL_IPQ5018
tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ5018 platform. Select this for
IPQ5018.
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
config PINCTRL_IPQ5332
tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc IPQ5332 platform.
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ8074 platform. Select this for
IPQ8074.
config PINCTRL_IPQ6018
tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ6018 platform. Select this for
IPQ6018.
config PINCTRL_IPQ9574
tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for
the Qualcomm Technologies Inc. TLMM block found on the
Qualcomm Technologies Inc. IPQ9574 platform. Select this for
IPQ9574.
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc MSM8226 platform.
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8660 platform.
config PINCTRL_MSM8960
tristate "Qualcomm 8960 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform.
config PINCTRL_MDM9607
tristate "Qualcomm 9607 pin controller driver"
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9607 platform.
config PINCTRL_MDM9615
tristate "Qualcomm 9615 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 9615 platform.
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8974 platform.
config PINCTRL_MSM8909
tristate "Qualcomm 8909 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8909 platform.
config PINCTRL_MSM8916
tristate "Qualcomm 8916 pin controller driver"
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm 8916 platform.
config PINCTRL_MSM8953
tristate "Qualcomm 8953 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8953 platform.
The Qualcomm APQ8053, SDM450, SDM632 platforms are also
supported by this driver.
config PINCTRL_MSM8976
tristate "Qualcomm 8976 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found on the Qualcomm MSM8976 platform.
The Qualcomm MSM8956, APQ8056, APQ8076 platforms are also
supported by this driver.
config PINCTRL_MSM8994
tristate "Qualcomm 8994 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8994 platform. The
Qualcomm 8992 platform is also supported by this driver.
config PINCTRL_MSM8996
tristate "Qualcomm MSM8996 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
config PINCTRL_MSM8998
tristate "Qualcomm MSM8998 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
config PINCTRL_QCM2290
tristate "Qualcomm QCM2290 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
TLMM block found in the Qualcomm QCM2290 platform.
config PINCTRL_QCS404
tristate "Qualcomm QCS404 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
TLMM block found in the Qualcomm QCS404 platform.
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on ACPI
help
This is the GPIO driver for the TLMM block found on the
Qualcomm Technologies QDF2xxx SOCs.
config PINCTRL_QDU1000
tristate "Qualcomm Technologies Inc QDU1000/QRU1000 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf, and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc QDU1000 and QRU1000 platforms.
config PINCTRL_SA8775P
tristate "Qualcomm Technologies Inc SA8775P pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux and pinconf driver for the Qualcomm
TLMM block found on the Qualcomm SA8775P platforms.
config PINCTRL_SC7180
tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
config PINCTRL_SC7280
tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7280 platform.
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC8180x platform.
config PINCTRL_SC8280XP
tristate "Qualcomm Technologies Inc SC8280xp pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC8280xp platform.
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM660 platform.
config PINCTRL_SDM670
tristate "Qualcomm Technologies Inc SDM670 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM670 platform.
config PINCTRL_SDM845
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
depends on (OF || ACPI)
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDM845 platform.
config PINCTRL_SDX55
tristate "Qualcomm Technologies Inc SDX55 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX55 platform.
config PINCTRL_SDX65
tristate "Qualcomm Technologies Inc SDX65 pin controller driver"
depends on ARM || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX65 platform.
config PINCTRL_SDX75
tristate "Qualcomm Technologies Inc SDX75 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SDX75 platform.
config PINCTRL_SM6115
tristate "Qualcomm Technologies Inc SM6115,SM4250 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6115 and SM4250 platforms.
config PINCTRL_SM6125
tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6125 platform.
config PINCTRL_SM6350
tristate "Qualcomm Technologies Inc SM6350 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6350 platform.
config PINCTRL_SM6375
tristate "Qualcomm Technologies Inc SM6375 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM6375 platform.
config PINCTRL_SM7150
tristate "Qualcomm Technologies Inc SM7150 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM7150 platform.
config PINCTRL_SM8150
tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8150 platform.
config PINCTRL_SM8250
tristate "Qualcomm Technologies Inc SM8250 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8250 platform.
config PINCTRL_SM8350
tristate "Qualcomm Technologies Inc SM8350 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8350 platform.
config PINCTRL_SM8450
tristate "Qualcomm Technologies Inc SM8450 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8450 platform.
config PINCTRL_SM8550
tristate "Qualcomm Technologies Inc SM8550 pin controller driver"
depends on ARM64 || COMPILE_TEST
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SM8550 platform.
endif

4
drivers/pinctrl/qcom/Makefile
View File

@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
@ -40,11 +41,12 @@ obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
obj-$(CONFIG_PINCTRL_SM6350) += pinctrl-sm6350.o
obj-$(CONFIG_PINCTRL_SM6375) += pinctrl-sm6375.o
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
obj-$(CONFIG_PINCTRL_SM7150) += pinctrl-sm7150.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o

104
drivers/pinctrl/qcom/pinctrl-apq8064.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -209,18 +208,11 @@ static const unsigned int sdc3_clk_pins[] = { 93 };
static const unsigned int sdc3_cmd_pins[] = { 94 };
static const unsigned int sdc3_data_pins[] = { 95 };
#define FUNCTION(fname) \
[APQ_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
@ -259,9 +251,9 @@ static const unsigned int sdc3_data_pins[] = { 95 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -464,48 +456,48 @@ static const char * const usb2_hsic_groups[] = {
"gpio88", "gpio89"
};
static const struct msm_function apq8064_functions[] = {
FUNCTION(cam_mclk),
FUNCTION(codec_mic_i2s),
FUNCTION(codec_spkr_i2s),
FUNCTION(gp_clk_0a),
FUNCTION(gp_clk_0b),
FUNCTION(gp_clk_1a),
FUNCTION(gp_clk_1b),
FUNCTION(gp_clk_2a),
FUNCTION(gp_clk_2b),
FUNCTION(gpio),
FUNCTION(gsbi1),
FUNCTION(gsbi2),
FUNCTION(gsbi3),
FUNCTION(gsbi4),
FUNCTION(gsbi4_cam_i2c),
FUNCTION(gsbi5),
FUNCTION(gsbi5_spi_cs1),
FUNCTION(gsbi5_spi_cs2),
FUNCTION(gsbi5_spi_cs3),
FUNCTION(gsbi6),
FUNCTION(gsbi6_spi_cs1),
FUNCTION(gsbi6_spi_cs2),
FUNCTION(gsbi6_spi_cs3),
FUNCTION(gsbi7),
FUNCTION(gsbi7_spi_cs1),
FUNCTION(gsbi7_spi_cs2),
FUNCTION(gsbi7_spi_cs3),
FUNCTION(gsbi_cam_i2c),
FUNCTION(hdmi),
FUNCTION(mi2s),
FUNCTION(riva_bt),
FUNCTION(riva_fm),
FUNCTION(riva_wlan),
FUNCTION(sdc2),
FUNCTION(sdc4),
FUNCTION(slimbus),
FUNCTION(spkr_i2s),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb2_hsic),
FUNCTION(ps_hold),
static const struct pinfunction apq8064_functions[] = {
APQ_PIN_FUNCTION(cam_mclk),
APQ_PIN_FUNCTION(codec_mic_i2s),
APQ_PIN_FUNCTION(codec_spkr_i2s),
APQ_PIN_FUNCTION(gp_clk_0a),
APQ_PIN_FUNCTION(gp_clk_0b),
APQ_PIN_FUNCTION(gp_clk_1a),
APQ_PIN_FUNCTION(gp_clk_1b),
APQ_PIN_FUNCTION(gp_clk_2a),
APQ_PIN_FUNCTION(gp_clk_2b),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(gsbi1),
APQ_PIN_FUNCTION(gsbi2),
APQ_PIN_FUNCTION(gsbi3),
APQ_PIN_FUNCTION(gsbi4),
APQ_PIN_FUNCTION(gsbi4_cam_i2c),
APQ_PIN_FUNCTION(gsbi5),
APQ_PIN_FUNCTION(gsbi5_spi_cs1),
APQ_PIN_FUNCTION(gsbi5_spi_cs2),
APQ_PIN_FUNCTION(gsbi5_spi_cs3),
APQ_PIN_FUNCTION(gsbi6),
APQ_PIN_FUNCTION(gsbi6_spi_cs1),
APQ_PIN_FUNCTION(gsbi6_spi_cs2),
APQ_PIN_FUNCTION(gsbi6_spi_cs3),
APQ_PIN_FUNCTION(gsbi7),
APQ_PIN_FUNCTION(gsbi7_spi_cs1),
APQ_PIN_FUNCTION(gsbi7_spi_cs2),
APQ_PIN_FUNCTION(gsbi7_spi_cs3),
APQ_PIN_FUNCTION(gsbi_cam_i2c),
APQ_PIN_FUNCTION(hdmi),
APQ_PIN_FUNCTION(mi2s),
APQ_PIN_FUNCTION(riva_bt),
APQ_PIN_FUNCTION(riva_fm),
APQ_PIN_FUNCTION(riva_wlan),
APQ_PIN_FUNCTION(sdc2),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(usb2_hsic),
APQ_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup apq8064_groups[] = {

264
drivers/pinctrl/qcom/pinctrl-apq8084.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -324,18 +323,11 @@ static const unsigned int sdc2_clk_pins[] = { 150 };
static const unsigned int sdc2_cmd_pins[] = { 151 };
static const unsigned int sdc2_data_pins[] = { 152 };
#define FUNCTION(fname) \
[APQ_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
APQ_MUX_gpio, \
APQ_MUX_##f1, \
@ -371,9 +363,9 @@ static const unsigned int sdc2_data_pins[] = { 152 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -906,128 +898,128 @@ static const char * const uim_groups[] = {
static const char * const uim_batt_alarm_groups[] = {
"gpio102"
};
static const struct msm_function apq8084_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(audio_ref),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_i2c9),
FUNCTION(blsp_i2c10),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_i2c12),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi3_cs1),
FUNCTION(blsp_spi3_cs2),
FUNCTION(blsp_spi3_cs3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_spi9),
FUNCTION(blsp_spi10),
FUNCTION(blsp_spi10_cs1),
FUNCTION(blsp_spi10_cs2),
FUNCTION(blsp_spi10_cs3),
FUNCTION(blsp_spi11),
FUNCTION(blsp_spi12),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(blsp_uart7),
FUNCTION(blsp_uart8),
FUNCTION(blsp_uart9),
FUNCTION(blsp_uart10),
FUNCTION(blsp_uart11),
FUNCTION(blsp_uart12),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim4),
FUNCTION(blsp_uim5),
FUNCTION(blsp_uim6),
FUNCTION(blsp_uim7),
FUNCTION(blsp_uim8),
FUNCTION(blsp_uim9),
FUNCTION(blsp_uim10),
FUNCTION(blsp_uim11),
FUNCTION(blsp_uim12),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cam_mclk2),
FUNCTION(cam_mclk3),
FUNCTION(cci_async),
FUNCTION(cci_async_in0),
FUNCTION(cci_i2c0),
FUNCTION(cci_i2c1),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(edp_hpd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_obt),
FUNCTION(gcc_vtt),
FUNCTION(gp_mn),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gp0_clk),
FUNCTION(gp1_clk),
FUNCTION(gpio),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc),
FUNCTION(hdmi_dtest),
FUNCTION(hdmi_hpd),
FUNCTION(hdmi_rcv),
FUNCTION(hsic),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(mdp_vsync),
FUNCTION(pci_e0),
FUNCTION(pci_e0_n),
FUNCTION(pci_e0_rst),
FUNCTION(pci_e1),
FUNCTION(pci_e1_rst),
FUNCTION(pci_e1_rst_n),
FUNCTION(pci_e1_clkreq_n),
FUNCTION(pri_mi2s),
FUNCTION(qua_mi2s),
FUNCTION(sata_act),
FUNCTION(sata_devsleep),
FUNCTION(sata_devsleep_n),
FUNCTION(sd_write),
FUNCTION(sdc_emmc_mode),
FUNCTION(sdc3),
FUNCTION(sdc4),
FUNCTION(sec_mi2s),
FUNCTION(slimbus),
FUNCTION(spdif_tx),
FUNCTION(spkr_i2s),
FUNCTION(spkr_i2s_ws),
FUNCTION(spss_geni),
FUNCTION(ter_mi2s),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(uim),
FUNCTION(uim_batt_alarm),
static const struct pinfunction apq8084_functions[] = {
APQ_PIN_FUNCTION(adsp_ext),
APQ_PIN_FUNCTION(audio_ref),
APQ_PIN_FUNCTION(blsp_i2c1),
APQ_PIN_FUNCTION(blsp_i2c2),
APQ_PIN_FUNCTION(blsp_i2c3),
APQ_PIN_FUNCTION(blsp_i2c4),
APQ_PIN_FUNCTION(blsp_i2c5),
APQ_PIN_FUNCTION(blsp_i2c6),
APQ_PIN_FUNCTION(blsp_i2c7),
APQ_PIN_FUNCTION(blsp_i2c8),
APQ_PIN_FUNCTION(blsp_i2c9),
APQ_PIN_FUNCTION(blsp_i2c10),
APQ_PIN_FUNCTION(blsp_i2c11),
APQ_PIN_FUNCTION(blsp_i2c12),
APQ_PIN_FUNCTION(blsp_spi1),
APQ_PIN_FUNCTION(blsp_spi1_cs1),
APQ_PIN_FUNCTION(blsp_spi1_cs2),
APQ_PIN_FUNCTION(blsp_spi1_cs3),
APQ_PIN_FUNCTION(blsp_spi2),
APQ_PIN_FUNCTION(blsp_spi3),
APQ_PIN_FUNCTION(blsp_spi3_cs1),
APQ_PIN_FUNCTION(blsp_spi3_cs2),
APQ_PIN_FUNCTION(blsp_spi3_cs3),
APQ_PIN_FUNCTION(blsp_spi4),
APQ_PIN_FUNCTION(blsp_spi5),
APQ_PIN_FUNCTION(blsp_spi6),
APQ_PIN_FUNCTION(blsp_spi7),
APQ_PIN_FUNCTION(blsp_spi8),
APQ_PIN_FUNCTION(blsp_spi9),
APQ_PIN_FUNCTION(blsp_spi10),
APQ_PIN_FUNCTION(blsp_spi10_cs1),
APQ_PIN_FUNCTION(blsp_spi10_cs2),
APQ_PIN_FUNCTION(blsp_spi10_cs3),
APQ_PIN_FUNCTION(blsp_spi11),
APQ_PIN_FUNCTION(blsp_spi12),
APQ_PIN_FUNCTION(blsp_uart1),
APQ_PIN_FUNCTION(blsp_uart2),
APQ_PIN_FUNCTION(blsp_uart3),
APQ_PIN_FUNCTION(blsp_uart4),
APQ_PIN_FUNCTION(blsp_uart5),
APQ_PIN_FUNCTION(blsp_uart6),
APQ_PIN_FUNCTION(blsp_uart7),
APQ_PIN_FUNCTION(blsp_uart8),
APQ_PIN_FUNCTION(blsp_uart9),
APQ_PIN_FUNCTION(blsp_uart10),
APQ_PIN_FUNCTION(blsp_uart11),
APQ_PIN_FUNCTION(blsp_uart12),
APQ_PIN_FUNCTION(blsp_uim1),
APQ_PIN_FUNCTION(blsp_uim2),
APQ_PIN_FUNCTION(blsp_uim3),
APQ_PIN_FUNCTION(blsp_uim4),
APQ_PIN_FUNCTION(blsp_uim5),
APQ_PIN_FUNCTION(blsp_uim6),
APQ_PIN_FUNCTION(blsp_uim7),
APQ_PIN_FUNCTION(blsp_uim8),
APQ_PIN_FUNCTION(blsp_uim9),
APQ_PIN_FUNCTION(blsp_uim10),
APQ_PIN_FUNCTION(blsp_uim11),
APQ_PIN_FUNCTION(blsp_uim12),
APQ_PIN_FUNCTION(cam_mclk0),
APQ_PIN_FUNCTION(cam_mclk1),
APQ_PIN_FUNCTION(cam_mclk2),
APQ_PIN_FUNCTION(cam_mclk3),
APQ_PIN_FUNCTION(cci_async),
APQ_PIN_FUNCTION(cci_async_in0),
APQ_PIN_FUNCTION(cci_i2c0),
APQ_PIN_FUNCTION(cci_i2c1),
APQ_PIN_FUNCTION(cci_timer0),
APQ_PIN_FUNCTION(cci_timer1),
APQ_PIN_FUNCTION(cci_timer2),
APQ_PIN_FUNCTION(cci_timer3),
APQ_PIN_FUNCTION(cci_timer4),
APQ_PIN_FUNCTION(edp_hpd),
APQ_PIN_FUNCTION(gcc_gp1),
APQ_PIN_FUNCTION(gcc_gp2),
APQ_PIN_FUNCTION(gcc_gp3),
APQ_PIN_FUNCTION(gcc_obt),
APQ_PIN_FUNCTION(gcc_vtt),
APQ_PIN_FUNCTION(gp_mn),
APQ_PIN_FUNCTION(gp_pdm0),
APQ_PIN_FUNCTION(gp_pdm1),
APQ_PIN_FUNCTION(gp_pdm2),
APQ_PIN_FUNCTION(gp0_clk),
APQ_PIN_FUNCTION(gp1_clk),
APQ_PIN_FUNCTION(gpio),
APQ_PIN_FUNCTION(hdmi_cec),
APQ_PIN_FUNCTION(hdmi_ddc),
APQ_PIN_FUNCTION(hdmi_dtest),
APQ_PIN_FUNCTION(hdmi_hpd),
APQ_PIN_FUNCTION(hdmi_rcv),
APQ_PIN_FUNCTION(hsic),
APQ_PIN_FUNCTION(ldo_en),
APQ_PIN_FUNCTION(ldo_update),
APQ_PIN_FUNCTION(mdp_vsync),
APQ_PIN_FUNCTION(pci_e0),
APQ_PIN_FUNCTION(pci_e0_n),
APQ_PIN_FUNCTION(pci_e0_rst),
APQ_PIN_FUNCTION(pci_e1),
APQ_PIN_FUNCTION(pci_e1_rst),
APQ_PIN_FUNCTION(pci_e1_rst_n),
APQ_PIN_FUNCTION(pci_e1_clkreq_n),
APQ_PIN_FUNCTION(pri_mi2s),
APQ_PIN_FUNCTION(qua_mi2s),
APQ_PIN_FUNCTION(sata_act),
APQ_PIN_FUNCTION(sata_devsleep),
APQ_PIN_FUNCTION(sata_devsleep_n),
APQ_PIN_FUNCTION(sd_write),
APQ_PIN_FUNCTION(sdc_emmc_mode),
APQ_PIN_FUNCTION(sdc3),
APQ_PIN_FUNCTION(sdc4),
APQ_PIN_FUNCTION(sec_mi2s),
APQ_PIN_FUNCTION(slimbus),
APQ_PIN_FUNCTION(spdif_tx),
APQ_PIN_FUNCTION(spkr_i2s),
APQ_PIN_FUNCTION(spkr_i2s_ws),
APQ_PIN_FUNCTION(spss_geni),
APQ_PIN_FUNCTION(ter_mi2s),
APQ_PIN_FUNCTION(tsif1),
APQ_PIN_FUNCTION(tsif2),
APQ_PIN_FUNCTION(uim),
APQ_PIN_FUNCTION(uim_batt_alarm),
};
static const struct msm_pingroup apq8084_groups[] = {

104
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -216,18 +215,11 @@ DECLARE_QCA_GPIO_PINS(97);
DECLARE_QCA_GPIO_PINS(98);
DECLARE_QCA_GPIO_PINS(99);
#define FUNCTION(fname) \
[qca_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
qca_mux_gpio, /* gpio mode */ \
qca_mux_##f1, \
@ -478,51 +470,51 @@ static const char * const wifi1_groups[] = {
"gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
};
static const struct msm_function ipq4019_functions[] = {
FUNCTION(aud_pin),
FUNCTION(audio_pwm),
FUNCTION(blsp_i2c0),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_spi0),
FUNCTION(blsp_spi1),
FUNCTION(blsp_uart0),
FUNCTION(blsp_uart1),
FUNCTION(chip_rst),
FUNCTION(gpio),
FUNCTION(i2s_rx),
FUNCTION(i2s_spdif_in),
FUNCTION(i2s_spdif_out),
FUNCTION(i2s_td),
FUNCTION(i2s_tx),
FUNCTION(jtag),
FUNCTION(led0),
FUNCTION(led1),
FUNCTION(led2),
FUNCTION(led3),
FUNCTION(led4),
FUNCTION(led5),
FUNCTION(led6),
FUNCTION(led7),
FUNCTION(led8),
FUNCTION(led9),
FUNCTION(led10),
FUNCTION(led11),
FUNCTION(mdc),
FUNCTION(mdio),
FUNCTION(pcie),
FUNCTION(pmu),
FUNCTION(prng_rosc),
FUNCTION(qpic),
FUNCTION(rgmii),
FUNCTION(rmii),
FUNCTION(sdio),
FUNCTION(smart0),
FUNCTION(smart1),
FUNCTION(smart2),
FUNCTION(smart3),
FUNCTION(tm),
FUNCTION(wifi0),
FUNCTION(wifi1),
static const struct pinfunction ipq4019_functions[] = {
QCA_PIN_FUNCTION(aud_pin),
QCA_PIN_FUNCTION(audio_pwm),
QCA_PIN_FUNCTION(blsp_i2c0),
QCA_PIN_FUNCTION(blsp_i2c1),
QCA_PIN_FUNCTION(blsp_spi0),
QCA_PIN_FUNCTION(blsp_spi1),
QCA_PIN_FUNCTION(blsp_uart0),
QCA_PIN_FUNCTION(blsp_uart1),
QCA_PIN_FUNCTION(chip_rst),
QCA_PIN_FUNCTION(gpio),
QCA_PIN_FUNCTION(i2s_rx),
QCA_PIN_FUNCTION(i2s_spdif_in),
QCA_PIN_FUNCTION(i2s_spdif_out),
QCA_PIN_FUNCTION(i2s_td),
QCA_PIN_FUNCTION(i2s_tx),
QCA_PIN_FUNCTION(jtag),
QCA_PIN_FUNCTION(led0),
QCA_PIN_FUNCTION(led1),
QCA_PIN_FUNCTION(led2),
QCA_PIN_FUNCTION(led3),
QCA_PIN_FUNCTION(led4),
QCA_PIN_FUNCTION(led5),
QCA_PIN_FUNCTION(led6),
QCA_PIN_FUNCTION(led7),
QCA_PIN_FUNCTION(led8),
QCA_PIN_FUNCTION(led9),
QCA_PIN_FUNCTION(led10),
QCA_PIN_FUNCTION(led11),
QCA_PIN_FUNCTION(mdc),
QCA_PIN_FUNCTION(mdio),
QCA_PIN_FUNCTION(pcie),
QCA_PIN_FUNCTION(pmu),
QCA_PIN_FUNCTION(prng_rosc),
QCA_PIN_FUNCTION(qpic),
QCA_PIN_FUNCTION(rgmii),
QCA_PIN_FUNCTION(rmii),
QCA_PIN_FUNCTION(sdio),
QCA_PIN_FUNCTION(smart0),
QCA_PIN_FUNCTION(smart1),
QCA_PIN_FUNCTION(smart2),
QCA_PIN_FUNCTION(smart3),
QCA_PIN_FUNCTION(tm),
QCA_PIN_FUNCTION(wifi0),
QCA_PIN_FUNCTION(wifi1),
};
static const struct msm_pingroup ipq4019_groups[] = {

783
drivers/pinctrl/qcom/pinctrl-ipq5018.c Normal file
View File

@ -0,0 +1,783 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9 \
}, \
.nfuncs = 10, \
.ctl_reg = REG_SIZE * id, \
.io_reg = 0x4 + REG_SIZE * id, \
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
.intr_status_reg = 0xc + REG_SIZE * id, \
.intr_target_reg = 0x8 + REG_SIZE * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 3, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
static const struct pinctrl_pin_desc ipq5018_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
};
#define DECLARE_MSM_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
enum ipq5018_functions {
msm_mux_atest_char,
msm_mux_audio_pdm0,
msm_mux_audio_pdm1,
msm_mux_audio_rxbclk,
msm_mux_audio_rxd,
msm_mux_audio_rxfsync,
msm_mux_audio_rxmclk,
msm_mux_audio_txbclk,
msm_mux_audio_txd,
msm_mux_audio_txfsync,
msm_mux_audio_txmclk,
msm_mux_blsp0_i2c,
msm_mux_blsp0_spi,
msm_mux_blsp0_uart0,
msm_mux_blsp0_uart1,
msm_mux_blsp1_i2c0,
msm_mux_blsp1_i2c1,
msm_mux_blsp1_spi0,
msm_mux_blsp1_spi1,
msm_mux_blsp1_uart0,
msm_mux_blsp1_uart1,
msm_mux_blsp1_uart2,
msm_mux_blsp2_i2c0,
msm_mux_blsp2_i2c1,
msm_mux_blsp2_spi,
msm_mux_blsp2_spi0,
msm_mux_blsp2_spi1,
msm_mux_btss,
msm_mux_burn0,
msm_mux_burn1,
msm_mux_cri_trng,
msm_mux_cri_trng0,
msm_mux_cri_trng1,
msm_mux_cxc_clk,
msm_mux_cxc_data,
msm_mux_dbg_out,
msm_mux_eud_gpio,
msm_mux_gcc_plltest,
msm_mux_gcc_tlmm,
msm_mux_gpio,
msm_mux_led0,
msm_mux_led2,
msm_mux_mac0,
msm_mux_mac1,
msm_mux_mdc,
msm_mux_mdio,
msm_mux_pcie0_clk,
msm_mux_pcie0_wake,
msm_mux_pcie1_clk,
msm_mux_pcie1_wake,
msm_mux_pll_test,
msm_mux_prng_rosc,
msm_mux_pwm0,
msm_mux_pwm1,
msm_mux_pwm2,
msm_mux_pwm3,
msm_mux_qdss_cti_trig_in_a0,
msm_mux_qdss_cti_trig_in_a1,
msm_mux_qdss_cti_trig_in_b0,
msm_mux_qdss_cti_trig_in_b1,
msm_mux_qdss_cti_trig_out_a0,
msm_mux_qdss_cti_trig_out_a1,
msm_mux_qdss_cti_trig_out_b0,
msm_mux_qdss_cti_trig_out_b1,
msm_mux_qdss_traceclk_a,
msm_mux_qdss_traceclk_b,
msm_mux_qdss_tracectl_a,
msm_mux_qdss_tracectl_b,
msm_mux_qdss_tracedata_a,
msm_mux_qdss_tracedata_b,
msm_mux_qspi_clk,
msm_mux_qspi_cs,
msm_mux_qspi_data,
msm_mux_reset_out,
msm_mux_sdc1_clk,
msm_mux_sdc1_cmd,
msm_mux_sdc1_data,
msm_mux_wci_txd,
msm_mux_wci_rxd,
msm_mux_wsa_swrm,
msm_mux_wsi_clk3,
msm_mux_wsi_data3,
msm_mux_wsis_reset,
msm_mux_xfem,
msm_mux__,
};
static const char * const atest_char_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio37",
};
static const char * const _groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46",
};
static const char * const wci_txd_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio42", "gpio43", "gpio44", "gpio45",
};
static const char * const wci_rxd_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio42", "gpio43", "gpio44", "gpio45",
};
static const char * const xfem_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
"gpio42", "gpio43", "gpio44", "gpio45",
};
static const char * const qdss_cti_trig_out_a0_groups[] = {
"gpio0",
};
static const char * const qdss_cti_trig_in_a0_groups[] = {
"gpio1",
};
static const char * const qdss_cti_trig_out_a1_groups[] = {
"gpio2",
};
static const char * const qdss_cti_trig_in_a1_groups[] = {
"gpio3",
};
static const char * const sdc1_data_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7",
};
static const char * const qspi_data_groups[] = {
"gpio4",
"gpio5",
"gpio6",
"gpio7",
};
static const char * const blsp1_spi1_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7",
};
static const char * const btss_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio17", "gpio18",
"gpio19", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
};
static const char * const dbg_out_groups[] = {
"gpio4",
};
static const char * const qdss_traceclk_a_groups[] = {
"gpio4",
};
static const char * const burn0_groups[] = {
"gpio4",
};
static const char * const cxc_clk_groups[] = {
"gpio5",
};
static const char * const blsp1_i2c1_groups[] = {
"gpio5", "gpio6",
};
static const char * const qdss_tracectl_a_groups[] = {
"gpio5",
};
static const char * const burn1_groups[] = {
"gpio5",
};
static const char * const cxc_data_groups[] = {
"gpio6",
};
static const char * const qdss_tracedata_a_groups[] = {
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12",
"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
"gpio20", "gpio21",
};
static const char * const mac0_groups[] = {
"gpio7",
};
static const char * const sdc1_cmd_groups[] = {
"gpio8",
};
static const char * const qspi_cs_groups[] = {
"gpio8",
};
static const char * const mac1_groups[] = {
"gpio8",
};
static const char * const sdc1_clk_groups[] = {
"gpio9",
};
static const char * const qspi_clk_groups[] = {
"gpio9",
};
static const char * const blsp0_spi_groups[] = {
"gpio10", "gpio11", "gpio12", "gpio13",
};
static const char * const blsp1_uart0_groups[] = {
"gpio10", "gpio11", "gpio12", "gpio13",
};
static const char * const gcc_plltest_groups[] = {
"gpio10", "gpio12",
};
static const char * const gcc_tlmm_groups[] = {
"gpio11",
};
static const char * const blsp0_i2c_groups[] = {
"gpio12", "gpio13",
};
static const char * const pcie0_clk_groups[] = {
"gpio14",
};
static const char * const cri_trng0_groups[] = {
"gpio14",
};
static const char * const cri_trng1_groups[] = {
"gpio15",
};
static const char * const pcie0_wake_groups[] = {
"gpio16",
};
static const char * const cri_trng_groups[] = {
"gpio16",
};
static const char * const pcie1_clk_groups[] = {
"gpio17",
};
static const char * const prng_rosc_groups[] = {
"gpio17",
};
static const char * const blsp1_spi0_groups[] = {
"gpio18", "gpio19", "gpio20", "gpio21",
};
static const char * const pcie1_wake_groups[] = {
"gpio19",
};
static const char * const blsp1_i2c0_groups[] = {
"gpio19", "gpio20",
};
static const char * const blsp0_uart0_groups[] = {
"gpio20", "gpio21",
};
static const char * const pll_test_groups[] = {
"gpio22",
};
static const char * const eud_gpio_groups[] = {
"gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
};
static const char * const audio_rxmclk_groups[] = {
"gpio23", "gpio23",
};
static const char * const audio_pdm0_groups[] = {
"gpio23", "gpio24",
};
static const char * const blsp2_spi1_groups[] = {
"gpio23", "gpio24", "gpio25", "gpio26",
};
static const char * const blsp1_uart2_groups[] = {
"gpio23", "gpio24", "gpio25", "gpio26",
};
static const char * const qdss_tracedata_b_groups[] = {
"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
"gpio37", "gpio38",
};
static const char * const audio_rxbclk_groups[] = {
"gpio24",
};
static const char * const audio_rxfsync_groups[] = {
"gpio25",
};
static const char * const audio_pdm1_groups[] = {
"gpio25", "gpio26",
};
static const char * const blsp2_i2c1_groups[] = {
"gpio25", "gpio26",
};
static const char * const audio_rxd_groups[] = {
"gpio26",
};
static const char * const audio_txmclk_groups[] = {
"gpio27", "gpio27",
};
static const char * const wsa_swrm_groups[] = {
"gpio27", "gpio28",
};
static const char * const blsp2_spi_groups[] = {
"gpio27",
};
static const char * const audio_txbclk_groups[] = {
"gpio28",
};
static const char * const blsp0_uart1_groups[] = {
"gpio28", "gpio29",
};
static const char * const audio_txfsync_groups[] = {
"gpio29",
};
static const char * const audio_txd_groups[] = {
"gpio30",
};
static const char * const wsis_reset_groups[] = {
"gpio30",
};
static const char * const blsp2_spi0_groups[] = {
"gpio31", "gpio32", "gpio33", "gpio34",
};
static const char * const blsp1_uart1_groups[] = {
"gpio31", "gpio32", "gpio33", "gpio34",
};
static const char * const blsp2_i2c0_groups[] = {
"gpio33", "gpio34",
};
static const char * const mdc_groups[] = {
"gpio36",
};
static const char * const wsi_clk3_groups[] = {
"gpio36",
};
static const char * const mdio_groups[] = {
"gpio37",
};
static const char * const wsi_data3_groups[] = {
"gpio37",
};
static const char * const qdss_traceclk_b_groups[] = {
"gpio39",
};
static const char * const reset_out_groups[] = {
"gpio40",
};
static const char * const qdss_tracectl_b_groups[] = {
"gpio40",
};
static const char * const pwm0_groups[] = {
"gpio42",
};
static const char * const qdss_cti_trig_out_b0_groups[] = {
"gpio42",
};
static const char * const pwm1_groups[] = {
"gpio43",
};
static const char * const qdss_cti_trig_in_b0_groups[] = {
"gpio43",
};
static const char * const pwm2_groups[] = {
"gpio44",
};
static const char * const qdss_cti_trig_out_b1_groups[] = {
"gpio44",
};
static const char * const pwm3_groups[] = {
"gpio45",
};
static const char * const qdss_cti_trig_in_b1_groups[] = {
"gpio45",
};
static const char * const led0_groups[] = {
"gpio46", "gpio30", "gpio10",
};
static const char * const led2_groups[] = {
"gpio30",
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46",
};
static const struct pinfunction ipq5018_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(audio_pdm0),
MSM_PIN_FUNCTION(audio_pdm1),
MSM_PIN_FUNCTION(audio_rxbclk),
MSM_PIN_FUNCTION(audio_rxd),
MSM_PIN_FUNCTION(audio_rxfsync),
MSM_PIN_FUNCTION(audio_rxmclk),
MSM_PIN_FUNCTION(audio_txbclk),
MSM_PIN_FUNCTION(audio_txd),
MSM_PIN_FUNCTION(audio_txfsync),
MSM_PIN_FUNCTION(audio_txmclk),
MSM_PIN_FUNCTION(blsp0_i2c),
MSM_PIN_FUNCTION(blsp0_spi),
MSM_PIN_FUNCTION(blsp0_uart0),
MSM_PIN_FUNCTION(blsp0_uart1),
MSM_PIN_FUNCTION(blsp1_i2c0),
MSM_PIN_FUNCTION(blsp1_i2c1),
MSM_PIN_FUNCTION(blsp1_spi0),
MSM_PIN_FUNCTION(blsp1_spi1),
MSM_PIN_FUNCTION(blsp1_uart0),
MSM_PIN_FUNCTION(blsp1_uart1),
MSM_PIN_FUNCTION(blsp1_uart2),
MSM_PIN_FUNCTION(blsp2_i2c0),
MSM_PIN_FUNCTION(blsp2_i2c1),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp2_spi0),
MSM_PIN_FUNCTION(blsp2_spi1),
MSM_PIN_FUNCTION(btss),
MSM_PIN_FUNCTION(burn0),
MSM_PIN_FUNCTION(burn1),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cxc_clk),
MSM_PIN_FUNCTION(cxc_data),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(eud_gpio),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(led0),
MSM_PIN_FUNCTION(led2),
MSM_PIN_FUNCTION(mac0),
MSM_PIN_FUNCTION(mac1),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(pcie1_clk),
MSM_PIN_FUNCTION(pcie1_wake),
MSM_PIN_FUNCTION(pll_test),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwm0),
MSM_PIN_FUNCTION(pwm1),
MSM_PIN_FUNCTION(pwm2),
MSM_PIN_FUNCTION(pwm3),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(reset_out),
MSM_PIN_FUNCTION(sdc1_clk),
MSM_PIN_FUNCTION(sdc1_cmd),
MSM_PIN_FUNCTION(sdc1_data),
MSM_PIN_FUNCTION(wci_txd),
MSM_PIN_FUNCTION(wci_rxd),
MSM_PIN_FUNCTION(wsa_swrm),
MSM_PIN_FUNCTION(wsi_clk3),
MSM_PIN_FUNCTION(wsi_data3),
MSM_PIN_FUNCTION(wsis_reset),
MSM_PIN_FUNCTION(xfem),
};
static const struct msm_pingroup ipq5018_groups[] = {
PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
PINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _),
PINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _),
PINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _),
PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _),
PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _),
PINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _),
PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _),
PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),
PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),
PINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _),
PINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _),
PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _),
PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _),
PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _),
PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),
PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _),
PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),
PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),
PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _),
PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),
PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),
PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),
PINGROUP(41, _, _, _, _, _, _, _, _, _),
PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
PINGROUP(46, led0, _, _, _, _, _, _, _, _),
};
static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
.pins = ipq5018_pins,
.npins = ARRAY_SIZE(ipq5018_pins),
.functions = ipq5018_functions,
.nfunctions = ARRAY_SIZE(ipq5018_functions),
.groups = ipq5018_groups,
.ngroups = ARRAY_SIZE(ipq5018_groups),
.ngpios = 47,
};
static int ipq5018_pinctrl_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &ipq5018_pinctrl);
}
static const struct of_device_id ipq5018_pinctrl_of_match[] = {
{ .compatible = "qcom,ipq5018-tlmm", },
{ }
};
MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);
static struct platform_driver ipq5018_pinctrl_driver = {
.driver = {
.name = "ipq5018-tlmm",
.of_match_table = ipq5018_pinctrl_of_match,
},
.probe = ipq5018_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init ipq5018_pinctrl_init(void)
{
return platform_driver_register(&ipq5018_pinctrl_driver);
}
arch_initcall(ipq5018_pinctrl_init);
static void __exit ipq5018_pinctrl_exit(void)
{
platform_driver_unregister(&ipq5018_pinctrl_driver);
}
module_exit(ipq5018_pinctrl_exit);
MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver");
MODULE_LICENSE("GPL");

206
drivers/pinctrl/qcom/pinctrl-ipq5332.c
View File

@ -6,23 +6,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -661,102 +653,102 @@ static const char * const xfem_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
};
static const struct msm_function ipq5332_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_tic),
FUNCTION(audio_pri),
FUNCTION(audio_pri0),
FUNCTION(audio_pri1),
FUNCTION(audio_sec),
FUNCTION(audio_sec0),
FUNCTION(audio_sec1),
FUNCTION(blsp0_i2c),
FUNCTION(blsp0_spi),
FUNCTION(blsp0_uart0),
FUNCTION(blsp0_uart1),
FUNCTION(blsp1_i2c0),
FUNCTION(blsp1_i2c1),
FUNCTION(blsp1_spi0),
FUNCTION(blsp1_spi1),
FUNCTION(blsp1_uart0),
FUNCTION(blsp1_uart1),
FUNCTION(blsp1_uart2),
FUNCTION(blsp2_i2c0),
FUNCTION(blsp2_i2c1),
FUNCTION(blsp2_spi),
FUNCTION(blsp2_spi0),
FUNCTION(blsp2_spi1),
FUNCTION(core_voltage),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(cri_trng2),
FUNCTION(cri_trng3),
FUNCTION(cxc_clk),
FUNCTION(cxc_data),
FUNCTION(dbg_out),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gpio),
FUNCTION(lock_det),
FUNCTION(mac0),
FUNCTION(mac1),
FUNCTION(mdc0),
FUNCTION(mdc1),
FUNCTION(mdio0),
FUNCTION(mdio1),
FUNCTION(pc),
FUNCTION(pcie0_clk),
FUNCTION(pcie0_wake),
FUNCTION(pcie1_clk),
FUNCTION(pcie1_wake),
FUNCTION(pcie2_clk),
FUNCTION(pcie2_wake),
FUNCTION(pll_test),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(pta),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(qspi_data),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(resout),
FUNCTION(rx0),
FUNCTION(rx1),
FUNCTION(sdc_data),
FUNCTION(sdc_clk),
FUNCTION(sdc_cmd),
FUNCTION(tsens_max),
FUNCTION(wci_txd),
FUNCTION(wci_rxd),
FUNCTION(wsi_clk),
FUNCTION(wsi_clk3),
FUNCTION(wsi_data),
FUNCTION(wsi_data3),
FUNCTION(wsis_reset),
FUNCTION(xfem),
static const struct pinfunction ipq5332_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_tic),
MSM_PIN_FUNCTION(audio_pri),
MSM_PIN_FUNCTION(audio_pri0),
MSM_PIN_FUNCTION(audio_pri1),
MSM_PIN_FUNCTION(audio_sec),
MSM_PIN_FUNCTION(audio_sec0),
MSM_PIN_FUNCTION(audio_sec1),
MSM_PIN_FUNCTION(blsp0_i2c),
MSM_PIN_FUNCTION(blsp0_spi),
MSM_PIN_FUNCTION(blsp0_uart0),
MSM_PIN_FUNCTION(blsp0_uart1),
MSM_PIN_FUNCTION(blsp1_i2c0),
MSM_PIN_FUNCTION(blsp1_i2c1),
MSM_PIN_FUNCTION(blsp1_spi0),
MSM_PIN_FUNCTION(blsp1_spi1),
MSM_PIN_FUNCTION(blsp1_uart0),
MSM_PIN_FUNCTION(blsp1_uart1),
MSM_PIN_FUNCTION(blsp1_uart2),
MSM_PIN_FUNCTION(blsp2_i2c0),
MSM_PIN_FUNCTION(blsp2_i2c1),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp2_spi0),
MSM_PIN_FUNCTION(blsp2_spi1),
MSM_PIN_FUNCTION(core_voltage),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cri_trng2),
MSM_PIN_FUNCTION(cri_trng3),
MSM_PIN_FUNCTION(cxc_clk),
MSM_PIN_FUNCTION(cxc_data),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(lock_det),
MSM_PIN_FUNCTION(mac0),
MSM_PIN_FUNCTION(mac1),
MSM_PIN_FUNCTION(mdc0),
MSM_PIN_FUNCTION(mdc1),
MSM_PIN_FUNCTION(mdio0),
MSM_PIN_FUNCTION(mdio1),
MSM_PIN_FUNCTION(pc),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(pcie1_clk),
MSM_PIN_FUNCTION(pcie1_wake),
MSM_PIN_FUNCTION(pcie2_clk),
MSM_PIN_FUNCTION(pcie2_wake),
MSM_PIN_FUNCTION(pll_test),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(pta),
MSM_PIN_FUNCTION(pwm0),
MSM_PIN_FUNCTION(pwm1),
MSM_PIN_FUNCTION(pwm2),
MSM_PIN_FUNCTION(pwm3),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(resout),
MSM_PIN_FUNCTION(rx0),
MSM_PIN_FUNCTION(rx1),
MSM_PIN_FUNCTION(sdc_data),
MSM_PIN_FUNCTION(sdc_clk),
MSM_PIN_FUNCTION(sdc_cmd),
MSM_PIN_FUNCTION(tsens_max),
MSM_PIN_FUNCTION(wci_txd),
MSM_PIN_FUNCTION(wci_rxd),
MSM_PIN_FUNCTION(wsi_clk),
MSM_PIN_FUNCTION(wsi_clk3),
MSM_PIN_FUNCTION(wsi_data),
MSM_PIN_FUNCTION(wsi_data3),
MSM_PIN_FUNCTION(wsis_reset),
MSM_PIN_FUNCTION(xfem),
};
static const struct msm_pingroup ipq5332_groups[] = {

260
drivers/pinctrl/qcom/pinctrl-ipq6018.c
View File

@ -6,23 +6,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -854,129 +846,129 @@ static const char * const gpio_groups[] = {
"gpio78", "gpio79",
};
static const struct msm_function ipq6018_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(audio0),
FUNCTION(audio1),
FUNCTION(audio2),
FUNCTION(audio3),
FUNCTION(audio_rxbclk),
FUNCTION(audio_rxfsync),
FUNCTION(audio_rxmclk),
FUNCTION(audio_rxmclkin),
FUNCTION(audio_txbclk),
FUNCTION(audio_txfsync),
FUNCTION(audio_txmclk),
FUNCTION(audio_txmclkin),
FUNCTION(blsp0_i2c),
FUNCTION(blsp0_spi),
FUNCTION(blsp0_uart),
FUNCTION(blsp1_i2c),
FUNCTION(blsp1_spi),
FUNCTION(blsp1_uart),
FUNCTION(blsp2_i2c),
FUNCTION(blsp2_spi),
FUNCTION(blsp2_uart),
FUNCTION(blsp3_i2c),
FUNCTION(blsp3_spi),
FUNCTION(blsp3_uart),
FUNCTION(blsp4_i2c),
FUNCTION(blsp4_spi),
FUNCTION(blsp4_uart),
FUNCTION(blsp5_i2c),
FUNCTION(blsp5_uart),
FUNCTION(burn0),
FUNCTION(burn1),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(cxc0),
FUNCTION(cxc1),
FUNCTION(dbg_out),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gpio),
FUNCTION(lpass_aud),
FUNCTION(lpass_aud0),
FUNCTION(lpass_aud1),
FUNCTION(lpass_aud2),
FUNCTION(lpass_pcm),
FUNCTION(lpass_pdm),
FUNCTION(mac00),
FUNCTION(mac01),
FUNCTION(mac10),
FUNCTION(mac11),
FUNCTION(mac12),
FUNCTION(mac13),
FUNCTION(mac20),
FUNCTION(mac21),
FUNCTION(mdc),
FUNCTION(mdio),
FUNCTION(pcie0_clk),
FUNCTION(pcie0_rst),
FUNCTION(pcie0_wake),
FUNCTION(prng_rosc),
FUNCTION(pta1_0),
FUNCTION(pta1_1),
FUNCTION(pta1_2),
FUNCTION(pta2_0),
FUNCTION(pta2_1),
FUNCTION(pta2_2),
FUNCTION(pwm00),
FUNCTION(pwm01),
FUNCTION(pwm02),
FUNCTION(pwm03),
FUNCTION(pwm04),
FUNCTION(pwm10),
FUNCTION(pwm11),
FUNCTION(pwm12),
FUNCTION(pwm13),
FUNCTION(pwm14),
FUNCTION(pwm20),
FUNCTION(pwm21),
FUNCTION(pwm22),
FUNCTION(pwm23),
FUNCTION(pwm24),
FUNCTION(pwm30),
FUNCTION(pwm31),
FUNCTION(pwm32),
FUNCTION(pwm33),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_b),
FUNCTION(qpic_pad),
FUNCTION(rx0),
FUNCTION(rx1),
FUNCTION(rx_swrm),
FUNCTION(rx_swrm0),
FUNCTION(rx_swrm1),
FUNCTION(sd_card),
FUNCTION(sd_write),
FUNCTION(tsens_max),
FUNCTION(tx_swrm),
FUNCTION(tx_swrm0),
FUNCTION(tx_swrm1),
FUNCTION(tx_swrm2),
FUNCTION(wci20),
FUNCTION(wci21),
FUNCTION(wci22),
FUNCTION(wci23),
FUNCTION(wsa_swrm),
static const struct pinfunction ipq6018_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(audio0),
MSM_PIN_FUNCTION(audio1),
MSM_PIN_FUNCTION(audio2),
MSM_PIN_FUNCTION(audio3),
MSM_PIN_FUNCTION(audio_rxbclk),
MSM_PIN_FUNCTION(audio_rxfsync),
MSM_PIN_FUNCTION(audio_rxmclk),
MSM_PIN_FUNCTION(audio_rxmclkin),
MSM_PIN_FUNCTION(audio_txbclk),
MSM_PIN_FUNCTION(audio_txfsync),
MSM_PIN_FUNCTION(audio_txmclk),
MSM_PIN_FUNCTION(audio_txmclkin),
MSM_PIN_FUNCTION(blsp0_i2c),
MSM_PIN_FUNCTION(blsp0_spi),
MSM_PIN_FUNCTION(blsp0_uart),
MSM_PIN_FUNCTION(blsp1_i2c),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp1_uart),
MSM_PIN_FUNCTION(blsp2_i2c),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp2_uart),
MSM_PIN_FUNCTION(blsp3_i2c),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(blsp3_uart),
MSM_PIN_FUNCTION(blsp4_i2c),
MSM_PIN_FUNCTION(blsp4_spi),
MSM_PIN_FUNCTION(blsp4_uart),
MSM_PIN_FUNCTION(blsp5_i2c),
MSM_PIN_FUNCTION(blsp5_uart),
MSM_PIN_FUNCTION(burn0),
MSM_PIN_FUNCTION(burn1),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cxc0),
MSM_PIN_FUNCTION(cxc1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(lpass_aud),
MSM_PIN_FUNCTION(lpass_aud0),
MSM_PIN_FUNCTION(lpass_aud1),
MSM_PIN_FUNCTION(lpass_aud2),
MSM_PIN_FUNCTION(lpass_pcm),
MSM_PIN_FUNCTION(lpass_pdm),
MSM_PIN_FUNCTION(mac00),
MSM_PIN_FUNCTION(mac01),
MSM_PIN_FUNCTION(mac10),
MSM_PIN_FUNCTION(mac11),
MSM_PIN_FUNCTION(mac12),
MSM_PIN_FUNCTION(mac13),
MSM_PIN_FUNCTION(mac20),
MSM_PIN_FUNCTION(mac21),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(pcie0_rst),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pta1_0),
MSM_PIN_FUNCTION(pta1_1),
MSM_PIN_FUNCTION(pta1_2),
MSM_PIN_FUNCTION(pta2_0),
MSM_PIN_FUNCTION(pta2_1),
MSM_PIN_FUNCTION(pta2_2),
MSM_PIN_FUNCTION(pwm00),
MSM_PIN_FUNCTION(pwm01),
MSM_PIN_FUNCTION(pwm02),
MSM_PIN_FUNCTION(pwm03),
MSM_PIN_FUNCTION(pwm04),
MSM_PIN_FUNCTION(pwm10),
MSM_PIN_FUNCTION(pwm11),
MSM_PIN_FUNCTION(pwm12),
MSM_PIN_FUNCTION(pwm13),
MSM_PIN_FUNCTION(pwm14),
MSM_PIN_FUNCTION(pwm20),
MSM_PIN_FUNCTION(pwm21),
MSM_PIN_FUNCTION(pwm22),
MSM_PIN_FUNCTION(pwm23),
MSM_PIN_FUNCTION(pwm24),
MSM_PIN_FUNCTION(pwm30),
MSM_PIN_FUNCTION(pwm31),
MSM_PIN_FUNCTION(pwm32),
MSM_PIN_FUNCTION(pwm33),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qpic_pad),
MSM_PIN_FUNCTION(rx0),
MSM_PIN_FUNCTION(rx1),
MSM_PIN_FUNCTION(rx_swrm),
MSM_PIN_FUNCTION(rx_swrm0),
MSM_PIN_FUNCTION(rx_swrm1),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(tsens_max),
MSM_PIN_FUNCTION(tx_swrm),
MSM_PIN_FUNCTION(tx_swrm0),
MSM_PIN_FUNCTION(tx_swrm1),
MSM_PIN_FUNCTION(tx_swrm2),
MSM_PIN_FUNCTION(wci20),
MSM_PIN_FUNCTION(wci21),
MSM_PIN_FUNCTION(wci22),
MSM_PIN_FUNCTION(wci23),
MSM_PIN_FUNCTION(wsa_swrm),
};
static const struct msm_pingroup ipq6018_groups[] = {

114
drivers/pinctrl/qcom/pinctrl-ipq8064.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -161,18 +160,11 @@ static const unsigned int sdc3_clk_pins[] = { 69 };
static const unsigned int sdc3_cmd_pins[] = { 70 };
static const unsigned int sdc3_data_pins[] = { 71 };
#define FUNCTION(fname) \
[IPQ_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
IPQ_MUX_gpio, \
IPQ_MUX_##f1, \
@ -211,9 +203,9 @@ static const unsigned int sdc3_data_pins[] = { 71 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -487,53 +479,53 @@ static const char * const ps_hold_groups[] = {
"gpio26",
};
static const struct msm_function ipq8064_functions[] = {
FUNCTION(gpio),
FUNCTION(mdio),
FUNCTION(ssbi),
FUNCTION(spmi),
FUNCTION(mi2s),
FUNCTION(pdm),
FUNCTION(audio_pcm),
FUNCTION(gsbi1),
FUNCTION(gsbi2),
FUNCTION(gsbi4),
FUNCTION(gsbi5),
FUNCTION(gsbi5_spi_cs1),
FUNCTION(gsbi5_spi_cs2),
FUNCTION(gsbi5_spi_cs3),
FUNCTION(gsbi6),
FUNCTION(gsbi7),
FUNCTION(nss_spi),
FUNCTION(sdc1),
FUNCTION(spdif),
FUNCTION(nand),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb_fs_n),
FUNCTION(usb_fs),
FUNCTION(usb2_hsic),
FUNCTION(rgmii2),
FUNCTION(sata),
FUNCTION(pcie1_rst),
FUNCTION(pcie1_prsnt),
FUNCTION(pcie1_pwren_n),
FUNCTION(pcie1_pwren),
FUNCTION(pcie1_pwrflt),
FUNCTION(pcie1_clk_req),
FUNCTION(pcie2_rst),
FUNCTION(pcie2_prsnt),
FUNCTION(pcie2_pwren_n),
FUNCTION(pcie2_pwren),
FUNCTION(pcie2_pwrflt),
FUNCTION(pcie2_clk_req),
FUNCTION(pcie3_rst),
FUNCTION(pcie3_prsnt),
FUNCTION(pcie3_pwren_n),
FUNCTION(pcie3_pwren),
FUNCTION(pcie3_pwrflt),
FUNCTION(pcie3_clk_req),
FUNCTION(ps_hold),
static const struct pinfunction ipq8064_functions[] = {
IPQ_PIN_FUNCTION(gpio),
IPQ_PIN_FUNCTION(mdio),
IPQ_PIN_FUNCTION(ssbi),
IPQ_PIN_FUNCTION(spmi),
IPQ_PIN_FUNCTION(mi2s),
IPQ_PIN_FUNCTION(pdm),
IPQ_PIN_FUNCTION(audio_pcm),
IPQ_PIN_FUNCTION(gsbi1),
IPQ_PIN_FUNCTION(gsbi2),
IPQ_PIN_FUNCTION(gsbi4),
IPQ_PIN_FUNCTION(gsbi5),
IPQ_PIN_FUNCTION(gsbi5_spi_cs1),
IPQ_PIN_FUNCTION(gsbi5_spi_cs2),
IPQ_PIN_FUNCTION(gsbi5_spi_cs3),
IPQ_PIN_FUNCTION(gsbi6),
IPQ_PIN_FUNCTION(gsbi7),
IPQ_PIN_FUNCTION(nss_spi),
IPQ_PIN_FUNCTION(sdc1),
IPQ_PIN_FUNCTION(spdif),
IPQ_PIN_FUNCTION(nand),
IPQ_PIN_FUNCTION(tsif1),
IPQ_PIN_FUNCTION(tsif2),
IPQ_PIN_FUNCTION(usb_fs_n),
IPQ_PIN_FUNCTION(usb_fs),
IPQ_PIN_FUNCTION(usb2_hsic),
IPQ_PIN_FUNCTION(rgmii2),
IPQ_PIN_FUNCTION(sata),
IPQ_PIN_FUNCTION(pcie1_rst),
IPQ_PIN_FUNCTION(pcie1_prsnt),
IPQ_PIN_FUNCTION(pcie1_pwren_n),
IPQ_PIN_FUNCTION(pcie1_pwren),
IPQ_PIN_FUNCTION(pcie1_pwrflt),
IPQ_PIN_FUNCTION(pcie1_clk_req),
IPQ_PIN_FUNCTION(pcie2_rst),
IPQ_PIN_FUNCTION(pcie2_prsnt),
IPQ_PIN_FUNCTION(pcie2_pwren_n),
IPQ_PIN_FUNCTION(pcie2_pwren),
IPQ_PIN_FUNCTION(pcie2_pwrflt),
IPQ_PIN_FUNCTION(pcie2_clk_req),
IPQ_PIN_FUNCTION(pcie3_rst),
IPQ_PIN_FUNCTION(pcie3_prsnt),
IPQ_PIN_FUNCTION(pcie3_pwren_n),
IPQ_PIN_FUNCTION(pcie3_pwren),
IPQ_PIN_FUNCTION(pcie3_pwrflt),
IPQ_PIN_FUNCTION(pcie3_clk_req),
IPQ_PIN_FUNCTION(ps_hold),
};
static const struct msm_pingroup ipq8064_groups[] = {

240
drivers/pinctrl/qcom/pinctrl-ipq8074.c
View File

@ -6,23 +6,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -797,119 +789,119 @@ static const char * const gpio_groups[] = {
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
};
static const struct msm_function ipq8074_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(audio_rxbclk),
FUNCTION(audio_rxd),
FUNCTION(audio_rxfsync),
FUNCTION(audio_rxmclk),
FUNCTION(audio_txbclk),
FUNCTION(audio_txd),
FUNCTION(audio_txfsync),
FUNCTION(audio_txmclk),
FUNCTION(blsp0_i2c),
FUNCTION(blsp0_spi),
FUNCTION(blsp0_uart),
FUNCTION(blsp1_i2c),
FUNCTION(blsp1_spi),
FUNCTION(blsp1_uart),
FUNCTION(blsp2_i2c),
FUNCTION(blsp2_spi),
FUNCTION(blsp2_uart),
FUNCTION(blsp3_i2c),
FUNCTION(blsp3_spi),
FUNCTION(blsp3_spi0),
FUNCTION(blsp3_spi1),
FUNCTION(blsp3_spi2),
FUNCTION(blsp3_spi3),
FUNCTION(blsp3_uart),
FUNCTION(blsp4_i2c0),
FUNCTION(blsp4_i2c1),
FUNCTION(blsp4_spi0),
FUNCTION(blsp4_spi1),
FUNCTION(blsp4_uart0),
FUNCTION(blsp4_uart1),
FUNCTION(blsp5_i2c),
FUNCTION(blsp5_spi),
FUNCTION(blsp5_uart),
FUNCTION(burn0),
FUNCTION(burn1),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(cxc0),
FUNCTION(cxc1),
FUNCTION(dbg_out),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gpio),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(led0),
FUNCTION(led1),
FUNCTION(led2),
FUNCTION(mac0_sa0),
FUNCTION(mac0_sa1),
FUNCTION(mac1_sa0),
FUNCTION(mac1_sa1),
FUNCTION(mac1_sa2),
FUNCTION(mac1_sa3),
FUNCTION(mac2_sa0),
FUNCTION(mac2_sa1),
FUNCTION(mdc),
FUNCTION(mdio),
FUNCTION(pcie0_clk),
FUNCTION(pcie0_rst),
FUNCTION(pcie0_wake),
FUNCTION(pcie1_clk),
FUNCTION(pcie1_rst),
FUNCTION(pcie1_wake),
FUNCTION(pcm_drx),
FUNCTION(pcm_dtx),
FUNCTION(pcm_fsync),
FUNCTION(pcm_pclk),
FUNCTION(pcm_zsi0),
FUNCTION(pcm_zsi1),
FUNCTION(prng_rosc),
FUNCTION(pta1_0),
FUNCTION(pta1_1),
FUNCTION(pta1_2),
FUNCTION(pta2_0),
FUNCTION(pta2_1),
FUNCTION(pta2_2),
FUNCTION(pwm0),
FUNCTION(pwm1),
FUNCTION(pwm2),
FUNCTION(pwm3),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(qpic),
FUNCTION(rx0),
FUNCTION(rx1),
FUNCTION(rx2),
FUNCTION(sd_card),
FUNCTION(sd_write),
FUNCTION(tsens_max),
FUNCTION(wci2a),
FUNCTION(wci2b),
FUNCTION(wci2c),
FUNCTION(wci2d),
static const struct pinfunction ipq8074_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(audio_rxbclk),
MSM_PIN_FUNCTION(audio_rxd),
MSM_PIN_FUNCTION(audio_rxfsync),
MSM_PIN_FUNCTION(audio_rxmclk),
MSM_PIN_FUNCTION(audio_txbclk),
MSM_PIN_FUNCTION(audio_txd),
MSM_PIN_FUNCTION(audio_txfsync),
MSM_PIN_FUNCTION(audio_txmclk),
MSM_PIN_FUNCTION(blsp0_i2c),
MSM_PIN_FUNCTION(blsp0_spi),
MSM_PIN_FUNCTION(blsp0_uart),
MSM_PIN_FUNCTION(blsp1_i2c),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp1_uart),
MSM_PIN_FUNCTION(blsp2_i2c),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp2_uart),
MSM_PIN_FUNCTION(blsp3_i2c),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(blsp3_spi0),
MSM_PIN_FUNCTION(blsp3_spi1),
MSM_PIN_FUNCTION(blsp3_spi2),
MSM_PIN_FUNCTION(blsp3_spi3),
MSM_PIN_FUNCTION(blsp3_uart),
MSM_PIN_FUNCTION(blsp4_i2c0),
MSM_PIN_FUNCTION(blsp4_i2c1),
MSM_PIN_FUNCTION(blsp4_spi0),
MSM_PIN_FUNCTION(blsp4_spi1),
MSM_PIN_FUNCTION(blsp4_uart0),
MSM_PIN_FUNCTION(blsp4_uart1),
MSM_PIN_FUNCTION(blsp5_i2c),
MSM_PIN_FUNCTION(blsp5_spi),
MSM_PIN_FUNCTION(blsp5_uart),
MSM_PIN_FUNCTION(burn0),
MSM_PIN_FUNCTION(burn1),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cxc0),
MSM_PIN_FUNCTION(cxc1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(led0),
MSM_PIN_FUNCTION(led1),
MSM_PIN_FUNCTION(led2),
MSM_PIN_FUNCTION(mac0_sa0),
MSM_PIN_FUNCTION(mac0_sa1),
MSM_PIN_FUNCTION(mac1_sa0),
MSM_PIN_FUNCTION(mac1_sa1),
MSM_PIN_FUNCTION(mac1_sa2),
MSM_PIN_FUNCTION(mac1_sa3),
MSM_PIN_FUNCTION(mac2_sa0),
MSM_PIN_FUNCTION(mac2_sa1),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(pcie0_rst),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(pcie1_clk),
MSM_PIN_FUNCTION(pcie1_rst),
MSM_PIN_FUNCTION(pcie1_wake),
MSM_PIN_FUNCTION(pcm_drx),
MSM_PIN_FUNCTION(pcm_dtx),
MSM_PIN_FUNCTION(pcm_fsync),
MSM_PIN_FUNCTION(pcm_pclk),
MSM_PIN_FUNCTION(pcm_zsi0),
MSM_PIN_FUNCTION(pcm_zsi1),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pta1_0),
MSM_PIN_FUNCTION(pta1_1),
MSM_PIN_FUNCTION(pta1_2),
MSM_PIN_FUNCTION(pta2_0),
MSM_PIN_FUNCTION(pta2_1),
MSM_PIN_FUNCTION(pta2_2),
MSM_PIN_FUNCTION(pwm0),
MSM_PIN_FUNCTION(pwm1),
MSM_PIN_FUNCTION(pwm2),
MSM_PIN_FUNCTION(pwm3),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qpic),
MSM_PIN_FUNCTION(rx0),
MSM_PIN_FUNCTION(rx1),
MSM_PIN_FUNCTION(rx2),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(tsens_max),
MSM_PIN_FUNCTION(wci2a),
MSM_PIN_FUNCTION(wci2b),
MSM_PIN_FUNCTION(wci2c),
MSM_PIN_FUNCTION(wci2d),
};
static const struct msm_pingroup ipq8074_groups[] = {

176
drivers/pinctrl/qcom/pinctrl-ipq9574.c
View File

@ -6,23 +6,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -623,87 +615,87 @@ static const char * const tsens_max_groups[] = {
"gpio64",
};
static const struct msm_function ipq9574_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(audio_pdm0),
FUNCTION(audio_pdm1),
FUNCTION(audio_pri),
FUNCTION(audio_sec),
FUNCTION(blsp0_spi),
FUNCTION(blsp0_uart),
FUNCTION(blsp1_i2c),
FUNCTION(blsp1_spi),
FUNCTION(blsp1_uart),
FUNCTION(blsp2_i2c),
FUNCTION(blsp2_spi),
FUNCTION(blsp2_uart),
FUNCTION(blsp3_i2c),
FUNCTION(blsp3_spi),
FUNCTION(blsp3_uart),
FUNCTION(blsp4_i2c),
FUNCTION(blsp4_spi),
FUNCTION(blsp4_uart),
FUNCTION(blsp5_i2c),
FUNCTION(blsp5_uart),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(cri_trng2),
FUNCTION(cri_trng3),
FUNCTION(cxc0),
FUNCTION(cxc1),
FUNCTION(dbg_out),
FUNCTION(dwc_ddrphy),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gpio),
FUNCTION(mac),
FUNCTION(mdc),
FUNCTION(mdio),
FUNCTION(pcie0_clk),
FUNCTION(pcie0_wake),
FUNCTION(pcie1_clk),
FUNCTION(pcie1_wake),
FUNCTION(pcie2_clk),
FUNCTION(pcie2_wake),
FUNCTION(pcie3_clk),
FUNCTION(pcie3_wake),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(pta),
FUNCTION(pwm),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(qspi_data),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(rx0),
FUNCTION(rx1),
FUNCTION(sdc_data),
FUNCTION(sdc_clk),
FUNCTION(sdc_cmd),
FUNCTION(sdc_rclk),
FUNCTION(tsens_max),
FUNCTION(wci20),
FUNCTION(wci21),
FUNCTION(wsa_swrm),
static const struct pinfunction ipq9574_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(audio_pdm0),
MSM_PIN_FUNCTION(audio_pdm1),
MSM_PIN_FUNCTION(audio_pri),
MSM_PIN_FUNCTION(audio_sec),
MSM_PIN_FUNCTION(blsp0_spi),
MSM_PIN_FUNCTION(blsp0_uart),
MSM_PIN_FUNCTION(blsp1_i2c),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp1_uart),
MSM_PIN_FUNCTION(blsp2_i2c),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp2_uart),
MSM_PIN_FUNCTION(blsp3_i2c),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(blsp3_uart),
MSM_PIN_FUNCTION(blsp4_i2c),
MSM_PIN_FUNCTION(blsp4_spi),
MSM_PIN_FUNCTION(blsp4_uart),
MSM_PIN_FUNCTION(blsp5_i2c),
MSM_PIN_FUNCTION(blsp5_uart),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(cri_trng2),
MSM_PIN_FUNCTION(cri_trng3),
MSM_PIN_FUNCTION(cxc0),
MSM_PIN_FUNCTION(cxc1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(dwc_ddrphy),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(mac),
MSM_PIN_FUNCTION(mdc),
MSM_PIN_FUNCTION(mdio),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(pcie0_wake),
MSM_PIN_FUNCTION(pcie1_clk),
MSM_PIN_FUNCTION(pcie1_wake),
MSM_PIN_FUNCTION(pcie2_clk),
MSM_PIN_FUNCTION(pcie2_wake),
MSM_PIN_FUNCTION(pcie3_clk),
MSM_PIN_FUNCTION(pcie3_wake),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(pta),
MSM_PIN_FUNCTION(pwm),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(rx0),
MSM_PIN_FUNCTION(rx1),
MSM_PIN_FUNCTION(sdc_data),
MSM_PIN_FUNCTION(sdc_clk),
MSM_PIN_FUNCTION(sdc_cmd),
MSM_PIN_FUNCTION(sdc_rclk),
MSM_PIN_FUNCTION(tsens_max),
MSM_PIN_FUNCTION(wci20),
MSM_PIN_FUNCTION(wci21),
MSM_PIN_FUNCTION(wsa_swrm),
};
static const struct msm_pingroup ipq9574_groups[] = {

276
drivers/pinctrl/qcom/pinctrl-mdm9607.c
View File

@ -8,7 +8,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -204,18 +203,11 @@ static const unsigned int qdsd_data1_pins[] = { 89 };
static const unsigned int qdsd_data2_pins[] = { 90 };
static const unsigned int qdsd_data3_pins[] = { 91 };
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, \
msm_mux_##f1, \
@ -252,9 +244,9 @@ static const unsigned int qdsd_data3_pins[] = { 91 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -806,134 +798,134 @@ static const char * const pwr_crypto_enabled_b_groups[] = {
"gpio79",
};
static const struct msm_function mdm9607_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_combodac_to_gpio_native),
FUNCTION(atest_gpsadc_dtest0_native),
FUNCTION(atest_gpsadc_dtest1_native),
FUNCTION(atest_tsens),
FUNCTION(backlight_en_b),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp1_spi),
FUNCTION(blsp2_spi),
FUNCTION(blsp3_spi),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(codec_int),
FUNCTION(codec_rst),
FUNCTION(coex_uart),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ebi0_wrcdc),
FUNCTION(ebi2_a),
FUNCTION(ebi2_a_d_8_b),
FUNCTION(ebi2_lcd),
FUNCTION(ebi2_lcd_cs_n_b),
FUNCTION(ebi2_lcd_te_b),
FUNCTION(eth_irq),
FUNCTION(eth_rst),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gmac_mdio),
FUNCTION(gpio),
FUNCTION(gsm0_tx),
FUNCTION(lcd_rst),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(modem_tsync),
FUNCTION(nav_ptp_pps_in_a),
FUNCTION(nav_ptp_pps_in_b),
FUNCTION(nav_tsync_out_a),
FUNCTION(nav_tsync_out_b),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pri_mi2s_data0_a),
FUNCTION(pri_mi2s_data1_a),
FUNCTION(pri_mi2s_mclk_a),
FUNCTION(pri_mi2s_sck_a),
FUNCTION(pri_mi2s_ws_a),
FUNCTION(prng_rosc),
FUNCTION(ptp_pps_out_a),
FUNCTION(ptp_pps_out_b),
FUNCTION(pwr_crypto_enabled_a),
FUNCTION(pwr_crypto_enabled_b),
FUNCTION(pwr_modem_enabled_a),
FUNCTION(pwr_modem_enabled_b),
FUNCTION(pwr_nav_enabled_a),
FUNCTION(pwr_nav_enabled_b),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(rcm_marker1),
FUNCTION(rcm_marker2),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(sensor_en),
FUNCTION(sensor_int2),
FUNCTION(sensor_int3),
FUNCTION(sensor_rst),
FUNCTION(ssbi1),
FUNCTION(ssbi2),
FUNCTION(touch_rst),
FUNCTION(ts_int),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(wlan_en1)
static const struct pinfunction mdm9607_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest_bbrx0),
MSM_PIN_FUNCTION(atest_bbrx1),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_combodac_to_gpio_native),
MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native),
MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(backlight_en_b),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(codec_int),
MSM_PIN_FUNCTION(codec_rst),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(ebi2_a_d_8_b),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(ebi2_lcd_cs_n_b),
MSM_PIN_FUNCTION(ebi2_lcd_te_b),
MSM_PIN_FUNCTION(eth_irq),
MSM_PIN_FUNCTION(eth_rst),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gmac_mdio),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(lcd_rst),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(nav_ptp_pps_in_a),
MSM_PIN_FUNCTION(nav_ptp_pps_in_b),
MSM_PIN_FUNCTION(nav_tsync_out_a),
MSM_PIN_FUNCTION(nav_tsync_out_b),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs0),
MSM_PIN_FUNCTION(pbs1),
MSM_PIN_FUNCTION(pbs2),
MSM_PIN_FUNCTION(pri_mi2s_data0_a),
MSM_PIN_FUNCTION(pri_mi2s_data1_a),
MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
MSM_PIN_FUNCTION(pri_mi2s_sck_a),
MSM_PIN_FUNCTION(pri_mi2s_ws_a),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(ptp_pps_out_a),
MSM_PIN_FUNCTION(ptp_pps_out_b),
MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
MSM_PIN_FUNCTION(pwr_modem_enabled_a),
MSM_PIN_FUNCTION(pwr_modem_enabled_b),
MSM_PIN_FUNCTION(pwr_nav_enabled_a),
MSM_PIN_FUNCTION(pwr_nav_enabled_b),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(rcm_marker1),
MSM_PIN_FUNCTION(rcm_marker2),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sensor_en),
MSM_PIN_FUNCTION(sensor_int2),
MSM_PIN_FUNCTION(sensor_int3),
MSM_PIN_FUNCTION(sensor_rst),
MSM_PIN_FUNCTION(ssbi1),
MSM_PIN_FUNCTION(ssbi2),
MSM_PIN_FUNCTION(touch_rst),
MSM_PIN_FUNCTION(ts_int),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(wlan_en1)
};
static const struct msm_pingroup mdm9607_groups[] = {

90
drivers/pinctrl/qcom/pinctrl-mdm9615.c
View File

@ -8,7 +8,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-msm.h"
@ -195,31 +194,24 @@ DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
MSM_MUX_##f8, \
MSM_MUX_##f9, \
MSM_MUX_##f10, \
MSM_MUX_##f11 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
msm_mux_##f11 \
}, \
.nfuncs = 12, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -245,19 +237,19 @@ DECLARE_MSM_GPIO_PINS(87);
}
enum mdm9615_functions {
MSM_MUX_gpio,
MSM_MUX_gsbi2_i2c,
MSM_MUX_gsbi3,
MSM_MUX_gsbi4,
MSM_MUX_gsbi5_i2c,
MSM_MUX_gsbi5_uart,
MSM_MUX_sdc2,
MSM_MUX_ebi2_lcdc,
MSM_MUX_ps_hold,
MSM_MUX_prim_audio,
MSM_MUX_sec_audio,
MSM_MUX_cdc_mclk,
MSM_MUX_NA,
msm_mux_gpio,
msm_mux_gsbi2_i2c,
msm_mux_gsbi3,
msm_mux_gsbi4,
msm_mux_gsbi5_i2c,
msm_mux_gsbi5_uart,
msm_mux_sdc2,
msm_mux_ebi2_lcdc,
msm_mux_ps_hold,
msm_mux_prim_audio,
msm_mux_sec_audio,
msm_mux_cdc_mclk,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -320,19 +312,19 @@ static const char * const cdc_mclk_groups[] = {
"gpio24",
};
static const struct msm_function mdm9615_functions[] = {
FUNCTION(gpio),
FUNCTION(gsbi2_i2c),
FUNCTION(gsbi3),
FUNCTION(gsbi4),
FUNCTION(gsbi5_i2c),
FUNCTION(gsbi5_uart),
FUNCTION(sdc2),
FUNCTION(ebi2_lcdc),
FUNCTION(ps_hold),
FUNCTION(prim_audio),
FUNCTION(sec_audio),
FUNCTION(cdc_mclk),
static const struct pinfunction mdm9615_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsbi2_i2c),
MSM_PIN_FUNCTION(gsbi3),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi5_i2c),
MSM_PIN_FUNCTION(gsbi5_uart),
MSM_PIN_FUNCTION(sdc2),
MSM_PIN_FUNCTION(ebi2_lcdc),
MSM_PIN_FUNCTION(ps_hold),
MSM_PIN_FUNCTION(prim_audio),
MSM_PIN_FUNCTION(sec_audio),
MSM_PIN_FUNCTION(cdc_mclk),
};
static const struct msm_pingroup mdm9615_groups[] = {

13
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -23,7 +23,6 @@
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/soc/qcom/irq.h>
@ -121,7 +120,7 @@ static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
{
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].name;
return pctrl->soc->groups[group].grp.name;
}
static int msm_get_group_pins(struct pinctrl_dev *pctldev,
@ -131,8 +130,8 @@ static int msm_get_group_pins(struct pinctrl_dev *pctldev,
{
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].pins;
*num_pins = pctrl->soc->groups[group].npins;
*pins = pctrl->soc->groups[group].grp.pins;
*num_pins = pctrl->soc->groups[group].grp.npins;
return 0;
}
@ -706,11 +705,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
val = !!(io_reg & BIT(g->in_bit));
if (egpio_enable) {
seq_printf(s, " %-8s: egpio\n", g->name);
seq_printf(s, " %-8s: egpio\n", g->grp.name);
return;
}
seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
if (pctrl->soc->pull_no_keeper)
@ -1442,7 +1441,7 @@ static void msm_ps_hold_poweroff(void)
static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
{
int i;
const struct msm_function *func = pctrl->soc->functions;
const struct pinfunction *func = pctrl->soc->functions;
for (i = 0; i < pctrl->soc->nfunctions; i++)
if (!strcmp(func[i].name, "ps_hold")) {

42
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -8,27 +8,35 @@
#include <linux/pm.h>
#include <linux/types.h>
#include <linux/pinctrl/pinctrl.h>
struct platform_device;
struct pinctrl_pin_desc;
/**
* struct msm_function - a pinmux function
* @name: Name of the pinmux function.
* @groups: List of pingroups for this function.
* @ngroups: Number of entries in @groups.
*/
struct msm_function {
const char *name;
const char * const *groups;
unsigned ngroups;
};
#define APQ_PIN_FUNCTION(fname) \
[APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define IPQ_PIN_FUNCTION(fname) \
[IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define MSM_PIN_FUNCTION(fname) \
[msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
#define QCA_PIN_FUNCTION(fname) \
[qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
fname##_groups, \
ARRAY_SIZE(fname##_groups))
/**
* struct msm_pingroup - Qualcomm pingroup definition
* @name: Name of the pingroup.
* @pins: A list of pins assigned to this pingroup.
* @npins: Number of entries in @pins.
* @grp: Generic data of the pin group (name and pins)
* @funcs: A list of pinmux functions that can be selected for
* this group. The index of the selected function is used
* for programming the function selector.
@ -61,9 +69,7 @@ struct msm_function {
* otherwise 1.
*/
struct msm_pingroup {
const char *name;
const unsigned *pins;
unsigned npins;
struct pingroup grp;
unsigned *funcs;
unsigned nfuncs;
@ -138,7 +144,7 @@ struct msm_gpio_wakeirq_map {
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
unsigned npins;
const struct msm_function *functions;
const struct pinfunction *functions;
unsigned nfunctions;
const struct msm_pingroup *groups;
unsigned ngroups;

156
drivers/pinctrl/qcom/pinctrl-msm8226.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -263,27 +262,20 @@ static const unsigned int sdc2_clk_pins[] = { 120 };
static const unsigned int sdc2_cmd_pins[] = { 121 };
static const unsigned int sdc2_data_pins[] = { 122 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7 \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -309,9 +301,9 @@ static const unsigned int sdc2_data_pins[] = { 122 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -338,36 +330,36 @@ static const unsigned int sdc2_data_pins[] = { 122 };
* the pingroup table below.
*/
enum msm8226_functions {
MSM_MUX_audio_pcm,
MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
MSM_MUX_blsp_i2c3,
MSM_MUX_blsp_i2c4,
MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi2,
MSM_MUX_blsp_spi3,
MSM_MUX_blsp_spi4,
MSM_MUX_blsp_spi5,
MSM_MUX_blsp_uart1,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart3,
MSM_MUX_blsp_uart4,
MSM_MUX_blsp_uart5,
MSM_MUX_blsp_uim1,
MSM_MUX_blsp_uim2,
MSM_MUX_blsp_uim3,
MSM_MUX_blsp_uim4,
MSM_MUX_blsp_uim5,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_cci_i2c0,
MSM_MUX_gp0_clk,
MSM_MUX_gp1_clk,
MSM_MUX_gpio,
MSM_MUX_sdc3,
MSM_MUX_wlan,
MSM_MUX_NA,
msm_mux_audio_pcm,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_spi1,
msm_mux_blsp_spi2,
msm_mux_blsp_spi3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uart3,
msm_mux_blsp_uart4,
msm_mux_blsp_uart5,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_blsp_uim3,
msm_mux_blsp_uim4,
msm_mux_blsp_uim5,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cci_i2c0,
msm_mux_gp0_clk,
msm_mux_gp1_clk,
msm_mux_gpio,
msm_mux_sdc3,
msm_mux_wlan,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -460,36 +452,36 @@ static const char * const wlan_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};
static const struct msm_function msm8226_functions[] = {
FUNCTION(audio_pcm),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim4),
FUNCTION(blsp_uim5),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cci_i2c0),
FUNCTION(gp0_clk),
FUNCTION(gp1_clk),
FUNCTION(gpio),
FUNCTION(sdc3),
FUNCTION(wlan),
static const struct pinfunction msm8226_functions[] = {
MSM_PIN_FUNCTION(audio_pcm),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cci_i2c0),
MSM_PIN_FUNCTION(gp0_clk),
MSM_PIN_FUNCTION(gp1_clk),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(sdc3),
MSM_PIN_FUNCTION(wlan),
};
static const struct msm_pingroup msm8226_groups[] = {

252
drivers/pinctrl/qcom/pinctrl-msm8660.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -375,27 +374,20 @@ static const unsigned int sdc3_clk_pins[] = { 176 };
static const unsigned int sdc3_cmd_pins[] = { 177 };
static const unsigned int sdc3_data_pins[] = { 178 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -422,9 +414,9 @@ static const unsigned int sdc3_data_pins[] = { 178 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -447,60 +439,60 @@ static const unsigned int sdc3_data_pins[] = { 178 };
}
enum msm8660_functions {
MSM_MUX_gpio,
MSM_MUX_cam_mclk,
MSM_MUX_dsub,
MSM_MUX_ext_gps,
MSM_MUX_gp_clk_0a,
MSM_MUX_gp_clk_0b,
MSM_MUX_gp_clk_1a,
MSM_MUX_gp_clk_1b,
MSM_MUX_gp_clk_2a,
MSM_MUX_gp_clk_2b,
MSM_MUX_gp_mn,
MSM_MUX_gsbi1,
MSM_MUX_gsbi1_spi_cs1_n,
MSM_MUX_gsbi1_spi_cs2a_n,
MSM_MUX_gsbi1_spi_cs2b_n,
MSM_MUX_gsbi1_spi_cs3_n,
MSM_MUX_gsbi2,
MSM_MUX_gsbi2_spi_cs1_n,
MSM_MUX_gsbi2_spi_cs2_n,
MSM_MUX_gsbi2_spi_cs3_n,
MSM_MUX_gsbi3,
MSM_MUX_gsbi3_spi_cs1_n,
MSM_MUX_gsbi3_spi_cs2_n,
MSM_MUX_gsbi3_spi_cs3_n,
MSM_MUX_gsbi4,
MSM_MUX_gsbi5,
MSM_MUX_gsbi6,
MSM_MUX_gsbi7,
MSM_MUX_gsbi8,
MSM_MUX_gsbi9,
MSM_MUX_gsbi10,
MSM_MUX_gsbi11,
MSM_MUX_gsbi12,
MSM_MUX_hdmi,
MSM_MUX_i2s,
MSM_MUX_lcdc,
MSM_MUX_mdp_vsync,
MSM_MUX_mi2s,
MSM_MUX_pcm,
MSM_MUX_ps_hold,
MSM_MUX_sdc1,
MSM_MUX_sdc2,
MSM_MUX_sdc5,
MSM_MUX_tsif1,
MSM_MUX_tsif2,
MSM_MUX_usb_fs1,
MSM_MUX_usb_fs1_oe_n,
MSM_MUX_usb_fs2,
MSM_MUX_usb_fs2_oe_n,
MSM_MUX_vfe,
MSM_MUX_vsens_alarm,
MSM_MUX_ebi2cs,
MSM_MUX_ebi2,
MSM_MUX__,
msm_mux_gpio,
msm_mux_cam_mclk,
msm_mux_dsub,
msm_mux_ext_gps,
msm_mux_gp_clk_0a,
msm_mux_gp_clk_0b,
msm_mux_gp_clk_1a,
msm_mux_gp_clk_1b,
msm_mux_gp_clk_2a,
msm_mux_gp_clk_2b,
msm_mux_gp_mn,
msm_mux_gsbi1,
msm_mux_gsbi1_spi_cs1_n,
msm_mux_gsbi1_spi_cs2a_n,
msm_mux_gsbi1_spi_cs2b_n,
msm_mux_gsbi1_spi_cs3_n,
msm_mux_gsbi2,
msm_mux_gsbi2_spi_cs1_n,
msm_mux_gsbi2_spi_cs2_n,
msm_mux_gsbi2_spi_cs3_n,
msm_mux_gsbi3,
msm_mux_gsbi3_spi_cs1_n,
msm_mux_gsbi3_spi_cs2_n,
msm_mux_gsbi3_spi_cs3_n,
msm_mux_gsbi4,
msm_mux_gsbi5,
msm_mux_gsbi6,
msm_mux_gsbi7,
msm_mux_gsbi8,
msm_mux_gsbi9,
msm_mux_gsbi10,
msm_mux_gsbi11,
msm_mux_gsbi12,
msm_mux_hdmi,
msm_mux_i2s,
msm_mux_lcdc,
msm_mux_mdp_vsync,
msm_mux_mi2s,
msm_mux_pcm,
msm_mux_ps_hold,
msm_mux_sdc1,
msm_mux_sdc2,
msm_mux_sdc5,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_usb_fs1,
msm_mux_usb_fs1_oe_n,
msm_mux_usb_fs2,
msm_mux_usb_fs2_oe_n,
msm_mux_vfe,
msm_mux_vsens_alarm,
msm_mux_ebi2cs,
msm_mux_ebi2,
msm_mux__,
};
static const char * const gpio_groups[] = {
@ -721,60 +713,60 @@ static const char * const ebi2_groups[] = {
"gpio158", /* busy */
};
static const struct msm_function msm8660_functions[] = {
FUNCTION(gpio),
FUNCTION(cam_mclk),
FUNCTION(dsub),
FUNCTION(ext_gps),
FUNCTION(gp_clk_0a),
FUNCTION(gp_clk_0b),
FUNCTION(gp_clk_1a),
FUNCTION(gp_clk_1b),
FUNCTION(gp_clk_2a),
FUNCTION(gp_clk_2b),
FUNCTION(gp_mn),
FUNCTION(gsbi1),
FUNCTION(gsbi1_spi_cs1_n),
FUNCTION(gsbi1_spi_cs2a_n),
FUNCTION(gsbi1_spi_cs2b_n),
FUNCTION(gsbi1_spi_cs3_n),
FUNCTION(gsbi2),
FUNCTION(gsbi2_spi_cs1_n),
FUNCTION(gsbi2_spi_cs2_n),
FUNCTION(gsbi2_spi_cs3_n),
FUNCTION(gsbi3),
FUNCTION(gsbi3_spi_cs1_n),
FUNCTION(gsbi3_spi_cs2_n),
FUNCTION(gsbi3_spi_cs3_n),
FUNCTION(gsbi4),
FUNCTION(gsbi5),
FUNCTION(gsbi6),
FUNCTION(gsbi7),
FUNCTION(gsbi8),
FUNCTION(gsbi9),
FUNCTION(gsbi10),
FUNCTION(gsbi11),
FUNCTION(gsbi12),
FUNCTION(hdmi),
FUNCTION(i2s),
FUNCTION(lcdc),
FUNCTION(mdp_vsync),
FUNCTION(mi2s),
FUNCTION(pcm),
FUNCTION(ps_hold),
FUNCTION(sdc1),
FUNCTION(sdc2),
FUNCTION(sdc5),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb_fs1),
FUNCTION(usb_fs1_oe_n),
FUNCTION(usb_fs2),
FUNCTION(usb_fs2_oe_n),
FUNCTION(vfe),
FUNCTION(vsens_alarm),
FUNCTION(ebi2cs), /* for EBI2 chip selects */
FUNCTION(ebi2), /* for general EBI2 pins */
static const struct pinfunction msm8660_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(dsub),
MSM_PIN_FUNCTION(ext_gps),
MSM_PIN_FUNCTION(gp_clk_0a),
MSM_PIN_FUNCTION(gp_clk_0b),
MSM_PIN_FUNCTION(gp_clk_1a),
MSM_PIN_FUNCTION(gp_clk_1b),
MSM_PIN_FUNCTION(gp_clk_2a),
MSM_PIN_FUNCTION(gp_clk_2b),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi1_spi_cs1_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs2a_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs2b_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi2_spi_cs1_n),
MSM_PIN_FUNCTION(gsbi2_spi_cs2_n),
MSM_PIN_FUNCTION(gsbi2_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi3),
MSM_PIN_FUNCTION(gsbi3_spi_cs1_n),
MSM_PIN_FUNCTION(gsbi3_spi_cs2_n),
MSM_PIN_FUNCTION(gsbi3_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(gsbi8),
MSM_PIN_FUNCTION(gsbi9),
MSM_PIN_FUNCTION(gsbi10),
MSM_PIN_FUNCTION(gsbi11),
MSM_PIN_FUNCTION(gsbi12),
MSM_PIN_FUNCTION(hdmi),
MSM_PIN_FUNCTION(i2s),
MSM_PIN_FUNCTION(lcdc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(pcm),
MSM_PIN_FUNCTION(ps_hold),
MSM_PIN_FUNCTION(sdc1),
MSM_PIN_FUNCTION(sdc2),
MSM_PIN_FUNCTION(sdc5),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(usb_fs1),
MSM_PIN_FUNCTION(usb_fs1_oe_n),
MSM_PIN_FUNCTION(usb_fs2),
MSM_PIN_FUNCTION(usb_fs2_oe_n),
MSM_PIN_FUNCTION(vfe),
MSM_PIN_FUNCTION(vsens_alarm),
MSM_PIN_FUNCTION(ebi2cs), /* for EBI2 chip selects */
MSM_PIN_FUNCTION(ebi2), /* for general EBI2 pins */
};
static const struct msm_pingroup msm8660_groups[] = {

268
drivers/pinctrl/qcom/pinctrl-msm8909.c
View File

@ -7,23 +7,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -643,130 +635,130 @@ static const char * const wcss_wlan_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};
static const struct msm_function msm8909_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_combodac),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_wlan0),
FUNCTION(atest_wlan1),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi2_cs1),
FUNCTION(blsp_spi2_cs2),
FUNCTION(blsp_spi2_cs3),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi3_cs1),
FUNCTION(blsp_spi3_cs2),
FUNCTION(blsp_spi3_cs3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cdc_pdm0),
FUNCTION(dbg_out),
FUNCTION(dmic0_clk),
FUNCTION(dmic0_data),
FUNCTION(ebi0_wrcdc),
FUNCTION(ebi2_a),
FUNCTION(ebi2_lcd),
FUNCTION(ext_lpass),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gcc_plltest),
FUNCTION(gpio),
FUNCTION(gsm0_tx),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(modem_tsync),
FUNCTION(nav_pps),
FUNCTION(nav_tsync),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pri_mi2s_data0_a),
FUNCTION(pri_mi2s_data0_b),
FUNCTION(pri_mi2s_data1_a),
FUNCTION(pri_mi2s_data1_b),
FUNCTION(pri_mi2s_mclk_a),
FUNCTION(pri_mi2s_mclk_b),
FUNCTION(pri_mi2s_sck_a),
FUNCTION(pri_mi2s_sck_b),
FUNCTION(pri_mi2s_ws_a),
FUNCTION(pri_mi2s_ws_b),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto_enabled_a),
FUNCTION(pwr_crypto_enabled_b),
FUNCTION(pwr_modem_enabled_a),
FUNCTION(pwr_modem_enabled_b),
FUNCTION(pwr_nav_enabled_a),
FUNCTION(pwr_nav_enabled_b),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(smb_int),
FUNCTION(ssbi0),
FUNCTION(ssbi1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim3_clk),
FUNCTION(uim3_data),
FUNCTION(uim3_present),
FUNCTION(uim3_reset),
FUNCTION(uim_batt),
FUNCTION(wcss_bt),
FUNCTION(wcss_fm),
FUNCTION(wcss_wlan),
static const struct pinfunction msm8909_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest_bbrx0),
MSM_PIN_FUNCTION(atest_bbrx1),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_combodac),
MSM_PIN_FUNCTION(atest_gpsadc0),
MSM_PIN_FUNCTION(atest_gpsadc1),
MSM_PIN_FUNCTION(atest_wlan0),
MSM_PIN_FUNCTION(atest_wlan1),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi2_cs1),
MSM_PIN_FUNCTION(blsp_spi2_cs2),
MSM_PIN_FUNCTION(blsp_spi2_cs3),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi3_cs1),
MSM_PIN_FUNCTION(blsp_spi3_cs2),
MSM_PIN_FUNCTION(blsp_spi3_cs3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cdc_pdm0),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(dmic0_clk),
MSM_PIN_FUNCTION(dmic0_data),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(ext_lpass),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(nav_tsync),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs0),
MSM_PIN_FUNCTION(pbs1),
MSM_PIN_FUNCTION(pbs2),
MSM_PIN_FUNCTION(pri_mi2s_data0_a),
MSM_PIN_FUNCTION(pri_mi2s_data0_b),
MSM_PIN_FUNCTION(pri_mi2s_data1_a),
MSM_PIN_FUNCTION(pri_mi2s_data1_b),
MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
MSM_PIN_FUNCTION(pri_mi2s_mclk_b),
MSM_PIN_FUNCTION(pri_mi2s_sck_a),
MSM_PIN_FUNCTION(pri_mi2s_sck_b),
MSM_PIN_FUNCTION(pri_mi2s_ws_a),
MSM_PIN_FUNCTION(pri_mi2s_ws_b),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
MSM_PIN_FUNCTION(pwr_modem_enabled_a),
MSM_PIN_FUNCTION(pwr_modem_enabled_b),
MSM_PIN_FUNCTION(pwr_nav_enabled_a),
MSM_PIN_FUNCTION(pwr_nav_enabled_b),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(smb_int),
MSM_PIN_FUNCTION(ssbi0),
MSM_PIN_FUNCTION(ssbi1),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim3_clk),
MSM_PIN_FUNCTION(uim3_data),
MSM_PIN_FUNCTION(uim3_present),
MSM_PIN_FUNCTION(uim3_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(wcss_bt),
MSM_PIN_FUNCTION(wcss_fm),
MSM_PIN_FUNCTION(wcss_wlan),
};
static const struct msm_pingroup msm8909_groups[] = {

556
drivers/pinctrl/qcom/pinctrl-msm8916.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -286,29 +285,22 @@ static const unsigned int qdsd_data1_pins[] = { 131 };
static const unsigned int qdsd_data2_pins[] = { 132 };
static const unsigned int qdsd_data3_pins[] = { 133 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
MSM_MUX_##f8, \
MSM_MUX_##f9 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9 \
}, \
.nfuncs = 10, \
.ctl_reg = 0x1000 * id, \
@ -334,9 +326,9 @@ static const unsigned int qdsd_data3_pins[] = { 133 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -359,135 +351,135 @@ static const unsigned int qdsd_data3_pins[] = { 133 };
}
enum msm8916_functions {
MSM_MUX_adsp_ext,
MSM_MUX_alsp_int,
MSM_MUX_atest_bbrx0,
MSM_MUX_atest_bbrx1,
MSM_MUX_atest_char,
MSM_MUX_atest_char0,
MSM_MUX_atest_char1,
MSM_MUX_atest_char2,
MSM_MUX_atest_char3,
MSM_MUX_atest_combodac,
MSM_MUX_atest_gpsadc0,
MSM_MUX_atest_gpsadc1,
MSM_MUX_atest_tsens,
MSM_MUX_atest_wlan0,
MSM_MUX_atest_wlan1,
MSM_MUX_backlight_en,
MSM_MUX_bimc_dte0,
MSM_MUX_bimc_dte1,
MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
MSM_MUX_blsp_i2c3,
MSM_MUX_blsp_i2c4,
MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_i2c6,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi1_cs1,
MSM_MUX_blsp_spi1_cs2,
MSM_MUX_blsp_spi1_cs3,
MSM_MUX_blsp_spi2,
MSM_MUX_blsp_spi2_cs1,
MSM_MUX_blsp_spi2_cs2,
MSM_MUX_blsp_spi2_cs3,
MSM_MUX_blsp_spi3,
MSM_MUX_blsp_spi3_cs1,
MSM_MUX_blsp_spi3_cs2,
MSM_MUX_blsp_spi3_cs3,
MSM_MUX_blsp_spi4,
MSM_MUX_blsp_spi5,
MSM_MUX_blsp_spi6,
MSM_MUX_blsp_uart1,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uim1,
MSM_MUX_blsp_uim2,
MSM_MUX_cam1_rst,
MSM_MUX_cam1_standby,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_cci_async,
MSM_MUX_cci_i2c,
MSM_MUX_cci_timer0,
MSM_MUX_cci_timer1,
MSM_MUX_cci_timer2,
MSM_MUX_cdc_pdm0,
MSM_MUX_codec_mad,
MSM_MUX_dbg_out,
MSM_MUX_display_5v,
MSM_MUX_dmic0_clk,
MSM_MUX_dmic0_data,
MSM_MUX_dsi_rst,
MSM_MUX_ebi0_wrcdc,
MSM_MUX_euro_us,
MSM_MUX_ext_lpass,
MSM_MUX_flash_strobe,
MSM_MUX_gcc_gp1_clk_a,
MSM_MUX_gcc_gp1_clk_b,
MSM_MUX_gcc_gp2_clk_a,
MSM_MUX_gcc_gp2_clk_b,
MSM_MUX_gcc_gp3_clk_a,
MSM_MUX_gcc_gp3_clk_b,
MSM_MUX_gpio,
MSM_MUX_gsm0_tx0,
MSM_MUX_gsm0_tx1,
MSM_MUX_gsm1_tx0,
MSM_MUX_gsm1_tx1,
MSM_MUX_gyro_accl,
MSM_MUX_kpsns0,
MSM_MUX_kpsns1,
MSM_MUX_kpsns2,
MSM_MUX_ldo_en,
MSM_MUX_ldo_update,
MSM_MUX_mag_int,
MSM_MUX_mdp_vsync,
MSM_MUX_modem_tsync,
MSM_MUX_m_voc,
MSM_MUX_nav_pps,
MSM_MUX_nav_tsync,
MSM_MUX_pa_indicator,
MSM_MUX_pbs0,
MSM_MUX_pbs1,
MSM_MUX_pbs2,
MSM_MUX_pri_mi2s,
MSM_MUX_pri_mi2s_ws,
MSM_MUX_prng_rosc,
MSM_MUX_pwr_crypto_enabled_a,
MSM_MUX_pwr_crypto_enabled_b,
MSM_MUX_pwr_modem_enabled_a,
MSM_MUX_pwr_modem_enabled_b,
MSM_MUX_pwr_nav_enabled_a,
MSM_MUX_pwr_nav_enabled_b,
MSM_MUX_qdss_ctitrig_in_a0,
MSM_MUX_qdss_ctitrig_in_a1,
MSM_MUX_qdss_ctitrig_in_b0,
MSM_MUX_qdss_ctitrig_in_b1,
MSM_MUX_qdss_ctitrig_out_a0,
MSM_MUX_qdss_ctitrig_out_a1,
MSM_MUX_qdss_ctitrig_out_b0,
MSM_MUX_qdss_ctitrig_out_b1,
MSM_MUX_qdss_traceclk_a,
MSM_MUX_qdss_traceclk_b,
MSM_MUX_qdss_tracectl_a,
MSM_MUX_qdss_tracectl_b,
MSM_MUX_qdss_tracedata_a,
MSM_MUX_qdss_tracedata_b,
MSM_MUX_reset_n,
MSM_MUX_sd_card,
MSM_MUX_sd_write,
MSM_MUX_sec_mi2s,
MSM_MUX_smb_int,
MSM_MUX_ssbi_wtr0,
MSM_MUX_ssbi_wtr1,
MSM_MUX_uim1,
MSM_MUX_uim2,
MSM_MUX_uim3,
MSM_MUX_uim_batt,
MSM_MUX_wcss_bt,
MSM_MUX_wcss_fm,
MSM_MUX_wcss_wlan,
MSM_MUX_webcam1_rst,
MSM_MUX_NA,
msm_mux_adsp_ext,
msm_mux_alsp_int,
msm_mux_atest_bbrx0,
msm_mux_atest_bbrx1,
msm_mux_atest_char,
msm_mux_atest_char0,
msm_mux_atest_char1,
msm_mux_atest_char2,
msm_mux_atest_char3,
msm_mux_atest_combodac,
msm_mux_atest_gpsadc0,
msm_mux_atest_gpsadc1,
msm_mux_atest_tsens,
msm_mux_atest_wlan0,
msm_mux_atest_wlan1,
msm_mux_backlight_en,
msm_mux_bimc_dte0,
msm_mux_bimc_dte1,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi2_cs1,
msm_mux_blsp_spi2_cs2,
msm_mux_blsp_spi2_cs3,
msm_mux_blsp_spi3,
msm_mux_blsp_spi3_cs1,
msm_mux_blsp_spi3_cs2,
msm_mux_blsp_spi3_cs3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_cam1_rst,
msm_mux_cam1_standby,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cci_async,
msm_mux_cci_i2c,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cdc_pdm0,
msm_mux_codec_mad,
msm_mux_dbg_out,
msm_mux_display_5v,
msm_mux_dmic0_clk,
msm_mux_dmic0_data,
msm_mux_dsi_rst,
msm_mux_ebi0_wrcdc,
msm_mux_euro_us,
msm_mux_ext_lpass,
msm_mux_flash_strobe,
msm_mux_gcc_gp1_clk_a,
msm_mux_gcc_gp1_clk_b,
msm_mux_gcc_gp2_clk_a,
msm_mux_gcc_gp2_clk_b,
msm_mux_gcc_gp3_clk_a,
msm_mux_gcc_gp3_clk_b,
msm_mux_gpio,
msm_mux_gsm0_tx0,
msm_mux_gsm0_tx1,
msm_mux_gsm1_tx0,
msm_mux_gsm1_tx1,
msm_mux_gyro_accl,
msm_mux_kpsns0,
msm_mux_kpsns1,
msm_mux_kpsns2,
msm_mux_ldo_en,
msm_mux_ldo_update,
msm_mux_mag_int,
msm_mux_mdp_vsync,
msm_mux_modem_tsync,
msm_mux_m_voc,
msm_mux_nav_pps,
msm_mux_nav_tsync,
msm_mux_pa_indicator,
msm_mux_pbs0,
msm_mux_pbs1,
msm_mux_pbs2,
msm_mux_pri_mi2s,
msm_mux_pri_mi2s_ws,
msm_mux_prng_rosc,
msm_mux_pwr_crypto_enabled_a,
msm_mux_pwr_crypto_enabled_b,
msm_mux_pwr_modem_enabled_a,
msm_mux_pwr_modem_enabled_b,
msm_mux_pwr_nav_enabled_a,
msm_mux_pwr_nav_enabled_b,
msm_mux_qdss_ctitrig_in_a0,
msm_mux_qdss_ctitrig_in_a1,
msm_mux_qdss_ctitrig_in_b0,
msm_mux_qdss_ctitrig_in_b1,
msm_mux_qdss_ctitrig_out_a0,
msm_mux_qdss_ctitrig_out_a1,
msm_mux_qdss_ctitrig_out_b0,
msm_mux_qdss_ctitrig_out_b1,
msm_mux_qdss_traceclk_a,
msm_mux_qdss_traceclk_b,
msm_mux_qdss_tracectl_a,
msm_mux_qdss_tracectl_b,
msm_mux_qdss_tracedata_a,
msm_mux_qdss_tracedata_b,
msm_mux_reset_n,
msm_mux_sd_card,
msm_mux_sd_write,
msm_mux_sec_mi2s,
msm_mux_smb_int,
msm_mux_ssbi_wtr0,
msm_mux_ssbi_wtr1,
msm_mux_uim1,
msm_mux_uim2,
msm_mux_uim3,
msm_mux_uim_batt,
msm_mux_wcss_bt,
msm_mux_wcss_fm,
msm_mux_wcss_wlan,
msm_mux_webcam1_rst,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -681,135 +673,135 @@ static const char * const wcss_wlan_groups[] = {
};
static const char * const webcam1_rst_groups[] = { "gpio28" };
static const struct msm_function msm8916_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(alsp_int),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_combodac),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_tsens),
FUNCTION(atest_wlan0),
FUNCTION(atest_wlan1),
FUNCTION(backlight_en),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi2_cs1),
FUNCTION(blsp_spi2_cs2),
FUNCTION(blsp_spi2_cs3),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi3_cs1),
FUNCTION(blsp_spi3_cs2),
FUNCTION(blsp_spi3_cs3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(cam1_rst),
FUNCTION(cam1_standby),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cdc_pdm0),
FUNCTION(codec_mad),
FUNCTION(dbg_out),
FUNCTION(display_5v),
FUNCTION(dmic0_clk),
FUNCTION(dmic0_data),
FUNCTION(dsi_rst),
FUNCTION(ebi0_wrcdc),
FUNCTION(euro_us),
FUNCTION(ext_lpass),
FUNCTION(flash_strobe),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gpio),
FUNCTION(gsm0_tx0),
FUNCTION(gsm0_tx1),
FUNCTION(gsm1_tx0),
FUNCTION(gsm1_tx1),
FUNCTION(gyro_accl),
FUNCTION(kpsns0),
FUNCTION(kpsns1),
FUNCTION(kpsns2),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(mag_int),
FUNCTION(mdp_vsync),
FUNCTION(modem_tsync),
FUNCTION(m_voc),
FUNCTION(nav_pps),
FUNCTION(nav_tsync),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto_enabled_a),
FUNCTION(pwr_crypto_enabled_b),
FUNCTION(pwr_modem_enabled_a),
FUNCTION(pwr_modem_enabled_b),
FUNCTION(pwr_nav_enabled_a),
FUNCTION(pwr_nav_enabled_b),
FUNCTION(qdss_ctitrig_in_a0),
FUNCTION(qdss_ctitrig_in_a1),
FUNCTION(qdss_ctitrig_in_b0),
FUNCTION(qdss_ctitrig_in_b1),
FUNCTION(qdss_ctitrig_out_a0),
FUNCTION(qdss_ctitrig_out_a1),
FUNCTION(qdss_ctitrig_out_b0),
FUNCTION(qdss_ctitrig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(reset_n),
FUNCTION(sd_card),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(smb_int),
FUNCTION(ssbi_wtr0),
FUNCTION(ssbi_wtr1),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim3),
FUNCTION(uim_batt),
FUNCTION(wcss_bt),
FUNCTION(wcss_fm),
FUNCTION(wcss_wlan),
FUNCTION(webcam1_rst)
static const struct pinfunction msm8916_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(alsp_int),
MSM_PIN_FUNCTION(atest_bbrx0),
MSM_PIN_FUNCTION(atest_bbrx1),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_combodac),
MSM_PIN_FUNCTION(atest_gpsadc0),
MSM_PIN_FUNCTION(atest_gpsadc1),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_wlan0),
MSM_PIN_FUNCTION(atest_wlan1),
MSM_PIN_FUNCTION(backlight_en),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi2_cs1),
MSM_PIN_FUNCTION(blsp_spi2_cs2),
MSM_PIN_FUNCTION(blsp_spi2_cs3),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi3_cs1),
MSM_PIN_FUNCTION(blsp_spi3_cs2),
MSM_PIN_FUNCTION(blsp_spi3_cs3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(cam1_rst),
MSM_PIN_FUNCTION(cam1_standby),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cdc_pdm0),
MSM_PIN_FUNCTION(codec_mad),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(display_5v),
MSM_PIN_FUNCTION(dmic0_clk),
MSM_PIN_FUNCTION(dmic0_data),
MSM_PIN_FUNCTION(dsi_rst),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(euro_us),
MSM_PIN_FUNCTION(ext_lpass),
MSM_PIN_FUNCTION(flash_strobe),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsm0_tx0),
MSM_PIN_FUNCTION(gsm0_tx1),
MSM_PIN_FUNCTION(gsm1_tx0),
MSM_PIN_FUNCTION(gsm1_tx1),
MSM_PIN_FUNCTION(gyro_accl),
MSM_PIN_FUNCTION(kpsns0),
MSM_PIN_FUNCTION(kpsns1),
MSM_PIN_FUNCTION(kpsns2),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(mag_int),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(nav_tsync),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs0),
MSM_PIN_FUNCTION(pbs1),
MSM_PIN_FUNCTION(pbs2),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
MSM_PIN_FUNCTION(pwr_modem_enabled_a),
MSM_PIN_FUNCTION(pwr_modem_enabled_b),
MSM_PIN_FUNCTION(pwr_nav_enabled_a),
MSM_PIN_FUNCTION(pwr_nav_enabled_b),
MSM_PIN_FUNCTION(qdss_ctitrig_in_a0),
MSM_PIN_FUNCTION(qdss_ctitrig_in_a1),
MSM_PIN_FUNCTION(qdss_ctitrig_in_b0),
MSM_PIN_FUNCTION(qdss_ctitrig_in_b1),
MSM_PIN_FUNCTION(qdss_ctitrig_out_a0),
MSM_PIN_FUNCTION(qdss_ctitrig_out_a1),
MSM_PIN_FUNCTION(qdss_ctitrig_out_b0),
MSM_PIN_FUNCTION(qdss_ctitrig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(reset_n),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(smb_int),
MSM_PIN_FUNCTION(ssbi_wtr0),
MSM_PIN_FUNCTION(ssbi_wtr1),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim3),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(wcss_bt),
MSM_PIN_FUNCTION(wcss_fm),
MSM_PIN_FUNCTION(wcss_wlan),
MSM_PIN_FUNCTION(webcam1_rst)
};
static const struct msm_pingroup msm8916_groups[] = {

424
drivers/pinctrl/qcom/pinctrl-msm8953.c
View File

@ -4,22 +4,14 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -56,9 +48,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -1431,208 +1423,208 @@ static const char * const wsa_irq_groups[] = {
"gpio97",
};
static const struct msm_function msm8953_functions[] = {
FUNCTION(accel_int),
FUNCTION(adsp_ext),
FUNCTION(alsp_int),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_gpsadc_dtest0_native),
FUNCTION(atest_gpsadc_dtest1_native),
FUNCTION(atest_tsens),
FUNCTION(atest_wlan0),
FUNCTION(atest_wlan1),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp1_spi),
FUNCTION(blsp3_spi),
FUNCTION(blsp6_spi),
FUNCTION(blsp7_spi),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(cam0_ldo),
FUNCTION(cam1_ldo),
FUNCTION(cam1_rst),
FUNCTION(cam1_standby),
FUNCTION(cam2_rst),
FUNCTION(cam2_standby),
FUNCTION(cam3_rst),
FUNCTION(cam3_standby),
FUNCTION(cam_irq),
FUNCTION(cam_mclk),
FUNCTION(cap_int),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cdc_pdm0),
FUNCTION(codec_int1),
FUNCTION(codec_int2),
FUNCTION(codec_reset),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dac_calib0),
FUNCTION(dac_calib1),
FUNCTION(dac_calib10),
FUNCTION(dac_calib11),
FUNCTION(dac_calib12),
FUNCTION(dac_calib13),
FUNCTION(dac_calib14),
FUNCTION(dac_calib15),
FUNCTION(dac_calib16),
FUNCTION(dac_calib17),
FUNCTION(dac_calib18),
FUNCTION(dac_calib19),
FUNCTION(dac_calib2),
FUNCTION(dac_calib20),
FUNCTION(dac_calib21),
FUNCTION(dac_calib22),
FUNCTION(dac_calib23),
FUNCTION(dac_calib24),
FUNCTION(dac_calib25),
FUNCTION(dac_calib3),
FUNCTION(dac_calib4),
FUNCTION(dac_calib5),
FUNCTION(dac_calib6),
FUNCTION(dac_calib7),
FUNCTION(dac_calib8),
FUNCTION(dac_calib9),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(dmic0_clk),
FUNCTION(dmic0_data),
FUNCTION(ebi_cdc),
FUNCTION(ebi_ch0),
FUNCTION(ext_lpass),
FUNCTION(flash_strobe),
FUNCTION(fp_int),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gcc_plltest),
FUNCTION(gcc_tlmm),
FUNCTION(gpio),
FUNCTION(gsm0_tx),
FUNCTION(gsm1_tx),
FUNCTION(gyro_int),
FUNCTION(hall_int),
FUNCTION(hdmi_int),
FUNCTION(key_focus),
FUNCTION(key_home),
FUNCTION(key_snapshot),
FUNCTION(key_volp),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_slimbus),
FUNCTION(lpass_slimbus0),
FUNCTION(lpass_slimbus1),
FUNCTION(m_voc),
FUNCTION(mag_int),
FUNCTION(mdp_vsync),
FUNCTION(mipi_dsi0),
FUNCTION(modem_tsync),
FUNCTION(mss_lte),
FUNCTION(nav_pps),
FUNCTION(nav_pps_in_a),
FUNCTION(nav_pps_in_b),
FUNCTION(nav_tsync),
FUNCTION(nfc_disable),
FUNCTION(nfc_dwl),
FUNCTION(nfc_irq),
FUNCTION(ois_sync),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pressure_int),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_mclk_a),
FUNCTION(pri_mi2s_mclk_b),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto_enabled_a),
FUNCTION(pwr_crypto_enabled_b),
FUNCTION(pwr_down),
FUNCTION(pwr_modem_enabled_a),
FUNCTION(pwr_modem_enabled_b),
FUNCTION(pwr_nav_enabled_a),
FUNCTION(pwr_nav_enabled_b),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(sd_write),
FUNCTION(sdcard_det),
FUNCTION(sec_mi2s),
FUNCTION(sec_mi2s_mclk_a),
FUNCTION(sec_mi2s_mclk_b),
FUNCTION(smb_int),
FUNCTION(ss_switch),
FUNCTION(ssbi_wtr1),
FUNCTION(ts_resout),
FUNCTION(ts_sample),
FUNCTION(ts_xvdd),
FUNCTION(tsens_max),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(us_emitter),
FUNCTION(us_euro),
FUNCTION(wcss_bt),
FUNCTION(wcss_fm),
FUNCTION(wcss_wlan),
FUNCTION(wcss_wlan0),
FUNCTION(wcss_wlan1),
FUNCTION(wcss_wlan2),
FUNCTION(wsa_en),
FUNCTION(wsa_io),
FUNCTION(wsa_irq),
static const struct pinfunction msm8953_functions[] = {
MSM_PIN_FUNCTION(accel_int),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(alsp_int),
MSM_PIN_FUNCTION(atest_bbrx0),
MSM_PIN_FUNCTION(atest_bbrx1),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native),
MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_wlan0),
MSM_PIN_FUNCTION(atest_wlan1),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(blsp6_spi),
MSM_PIN_FUNCTION(blsp7_spi),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(cam0_ldo),
MSM_PIN_FUNCTION(cam1_ldo),
MSM_PIN_FUNCTION(cam1_rst),
MSM_PIN_FUNCTION(cam1_standby),
MSM_PIN_FUNCTION(cam2_rst),
MSM_PIN_FUNCTION(cam2_standby),
MSM_PIN_FUNCTION(cam3_rst),
MSM_PIN_FUNCTION(cam3_standby),
MSM_PIN_FUNCTION(cam_irq),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cap_int),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cdc_pdm0),
MSM_PIN_FUNCTION(codec_int1),
MSM_PIN_FUNCTION(codec_int2),
MSM_PIN_FUNCTION(codec_reset),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dac_calib0),
MSM_PIN_FUNCTION(dac_calib1),
MSM_PIN_FUNCTION(dac_calib10),
MSM_PIN_FUNCTION(dac_calib11),
MSM_PIN_FUNCTION(dac_calib12),
MSM_PIN_FUNCTION(dac_calib13),
MSM_PIN_FUNCTION(dac_calib14),
MSM_PIN_FUNCTION(dac_calib15),
MSM_PIN_FUNCTION(dac_calib16),
MSM_PIN_FUNCTION(dac_calib17),
MSM_PIN_FUNCTION(dac_calib18),
MSM_PIN_FUNCTION(dac_calib19),
MSM_PIN_FUNCTION(dac_calib2),
MSM_PIN_FUNCTION(dac_calib20),
MSM_PIN_FUNCTION(dac_calib21),
MSM_PIN_FUNCTION(dac_calib22),
MSM_PIN_FUNCTION(dac_calib23),
MSM_PIN_FUNCTION(dac_calib24),
MSM_PIN_FUNCTION(dac_calib25),
MSM_PIN_FUNCTION(dac_calib3),
MSM_PIN_FUNCTION(dac_calib4),
MSM_PIN_FUNCTION(dac_calib5),
MSM_PIN_FUNCTION(dac_calib6),
MSM_PIN_FUNCTION(dac_calib7),
MSM_PIN_FUNCTION(dac_calib8),
MSM_PIN_FUNCTION(dac_calib9),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(dmic0_clk),
MSM_PIN_FUNCTION(dmic0_data),
MSM_PIN_FUNCTION(ebi_cdc),
MSM_PIN_FUNCTION(ebi_ch0),
MSM_PIN_FUNCTION(ext_lpass),
MSM_PIN_FUNCTION(flash_strobe),
MSM_PIN_FUNCTION(fp_int),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(gsm1_tx),
MSM_PIN_FUNCTION(gyro_int),
MSM_PIN_FUNCTION(hall_int),
MSM_PIN_FUNCTION(hdmi_int),
MSM_PIN_FUNCTION(key_focus),
MSM_PIN_FUNCTION(key_home),
MSM_PIN_FUNCTION(key_snapshot),
MSM_PIN_FUNCTION(key_volp),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(lpass_slimbus0),
MSM_PIN_FUNCTION(lpass_slimbus1),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mag_int),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mipi_dsi0),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(nav_pps_in_a),
MSM_PIN_FUNCTION(nav_pps_in_b),
MSM_PIN_FUNCTION(nav_tsync),
MSM_PIN_FUNCTION(nfc_disable),
MSM_PIN_FUNCTION(nfc_dwl),
MSM_PIN_FUNCTION(nfc_irq),
MSM_PIN_FUNCTION(ois_sync),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs0),
MSM_PIN_FUNCTION(pbs1),
MSM_PIN_FUNCTION(pbs2),
MSM_PIN_FUNCTION(pressure_int),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
MSM_PIN_FUNCTION(pri_mi2s_mclk_b),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto_enabled_a),
MSM_PIN_FUNCTION(pwr_crypto_enabled_b),
MSM_PIN_FUNCTION(pwr_down),
MSM_PIN_FUNCTION(pwr_modem_enabled_a),
MSM_PIN_FUNCTION(pwr_modem_enabled_b),
MSM_PIN_FUNCTION(pwr_nav_enabled_a),
MSM_PIN_FUNCTION(pwr_nav_enabled_b),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdcard_det),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sec_mi2s_mclk_a),
MSM_PIN_FUNCTION(sec_mi2s_mclk_b),
MSM_PIN_FUNCTION(smb_int),
MSM_PIN_FUNCTION(ss_switch),
MSM_PIN_FUNCTION(ssbi_wtr1),
MSM_PIN_FUNCTION(ts_resout),
MSM_PIN_FUNCTION(ts_sample),
MSM_PIN_FUNCTION(ts_xvdd),
MSM_PIN_FUNCTION(tsens_max),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(us_emitter),
MSM_PIN_FUNCTION(us_euro),
MSM_PIN_FUNCTION(wcss_bt),
MSM_PIN_FUNCTION(wcss_fm),
MSM_PIN_FUNCTION(wcss_wlan),
MSM_PIN_FUNCTION(wcss_wlan0),
MSM_PIN_FUNCTION(wcss_wlan1),
MSM_PIN_FUNCTION(wcss_wlan2),
MSM_PIN_FUNCTION(wsa_en),
MSM_PIN_FUNCTION(wsa_io),
MSM_PIN_FUNCTION(wsa_irq),
};
static const struct msm_pingroup msm8953_groups[] = {

464
drivers/pinctrl/qcom/pinctrl-msm8960.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include "pinctrl-msm.h"
@ -334,31 +333,24 @@ static const unsigned int sdc3_clk_pins[] = { 155 };
static const unsigned int sdc3_cmd_pins[] = { 156 };
static const unsigned int sdc3_data_pins[] = { 157 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
MSM_MUX_##f8, \
MSM_MUX_##f9, \
MSM_MUX_##f10, \
MSM_MUX_##f11 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
msm_mux_##f11 \
}, \
.nfuncs = 12, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -385,9 +377,9 @@ static const unsigned int sdc3_data_pins[] = { 157 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -410,111 +402,111 @@ static const unsigned int sdc3_data_pins[] = { 157 };
}
enum msm8960_functions {
MSM_MUX_audio_pcm,
MSM_MUX_bt,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_cam_mclk2,
MSM_MUX_codec_mic_i2s,
MSM_MUX_codec_spkr_i2s,
MSM_MUX_ext_gps,
MSM_MUX_fm,
MSM_MUX_gps_blanking,
MSM_MUX_gps_pps_in,
MSM_MUX_gps_pps_out,
MSM_MUX_gp_clk_0a,
MSM_MUX_gp_clk_0b,
MSM_MUX_gp_clk_1a,
MSM_MUX_gp_clk_1b,
MSM_MUX_gp_clk_2a,
MSM_MUX_gp_clk_2b,
MSM_MUX_gp_mn,
MSM_MUX_gp_pdm_0a,
MSM_MUX_gp_pdm_0b,
MSM_MUX_gp_pdm_1a,
MSM_MUX_gp_pdm_1b,
MSM_MUX_gp_pdm_2a,
MSM_MUX_gp_pdm_2b,
MSM_MUX_gpio,
MSM_MUX_gsbi1,
MSM_MUX_gsbi1_spi_cs1_n,
MSM_MUX_gsbi1_spi_cs2a_n,
MSM_MUX_gsbi1_spi_cs2b_n,
MSM_MUX_gsbi1_spi_cs3_n,
MSM_MUX_gsbi2,
MSM_MUX_gsbi2_spi_cs1_n,
MSM_MUX_gsbi2_spi_cs2_n,
MSM_MUX_gsbi2_spi_cs3_n,
MSM_MUX_gsbi3,
MSM_MUX_gsbi4,
MSM_MUX_gsbi4_3d_cam_i2c_l,
MSM_MUX_gsbi4_3d_cam_i2c_r,
MSM_MUX_gsbi5,
MSM_MUX_gsbi5_3d_cam_i2c_l,
MSM_MUX_gsbi5_3d_cam_i2c_r,
MSM_MUX_gsbi6,
MSM_MUX_gsbi7,
MSM_MUX_gsbi8,
MSM_MUX_gsbi9,
MSM_MUX_gsbi10,
MSM_MUX_gsbi11,
MSM_MUX_gsbi11_spi_cs1a_n,
MSM_MUX_gsbi11_spi_cs1b_n,
MSM_MUX_gsbi11_spi_cs2a_n,
MSM_MUX_gsbi11_spi_cs2b_n,
MSM_MUX_gsbi11_spi_cs3_n,
MSM_MUX_gsbi12,
MSM_MUX_hdmi_cec,
MSM_MUX_hdmi_ddc_clock,
MSM_MUX_hdmi_ddc_data,
MSM_MUX_hdmi_hot_plug_detect,
MSM_MUX_hsic,
MSM_MUX_mdp_vsync,
MSM_MUX_mi2s,
MSM_MUX_mic_i2s,
MSM_MUX_pmb_clk,
MSM_MUX_pmb_ext_ctrl,
MSM_MUX_ps_hold,
MSM_MUX_rpm_wdog,
MSM_MUX_sdc2,
MSM_MUX_sdc4,
MSM_MUX_sdc5,
MSM_MUX_slimbus1,
MSM_MUX_slimbus2,
MSM_MUX_spkr_i2s,
MSM_MUX_ssbi1,
MSM_MUX_ssbi2,
MSM_MUX_ssbi_ext_gps,
MSM_MUX_ssbi_pmic2,
MSM_MUX_ssbi_qpa1,
MSM_MUX_ssbi_ts,
MSM_MUX_tsif1,
MSM_MUX_tsif2,
MSM_MUX_ts_eoc,
MSM_MUX_usb_fs1,
MSM_MUX_usb_fs1_oe,
MSM_MUX_usb_fs1_oe_n,
MSM_MUX_usb_fs2,
MSM_MUX_usb_fs2_oe,
MSM_MUX_usb_fs2_oe_n,
MSM_MUX_vfe_camif_timer1_a,
MSM_MUX_vfe_camif_timer1_b,
MSM_MUX_vfe_camif_timer2,
MSM_MUX_vfe_camif_timer3_a,
MSM_MUX_vfe_camif_timer3_b,
MSM_MUX_vfe_camif_timer4_a,
MSM_MUX_vfe_camif_timer4_b,
MSM_MUX_vfe_camif_timer4_c,
MSM_MUX_vfe_camif_timer5_a,
MSM_MUX_vfe_camif_timer5_b,
MSM_MUX_vfe_camif_timer6_a,
MSM_MUX_vfe_camif_timer6_b,
MSM_MUX_vfe_camif_timer6_c,
MSM_MUX_vfe_camif_timer7_a,
MSM_MUX_vfe_camif_timer7_b,
MSM_MUX_vfe_camif_timer7_c,
MSM_MUX_wlan,
MSM_MUX_NA,
msm_mux_audio_pcm,
msm_mux_bt,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cam_mclk2,
msm_mux_codec_mic_i2s,
msm_mux_codec_spkr_i2s,
msm_mux_ext_gps,
msm_mux_fm,
msm_mux_gps_blanking,
msm_mux_gps_pps_in,
msm_mux_gps_pps_out,
msm_mux_gp_clk_0a,
msm_mux_gp_clk_0b,
msm_mux_gp_clk_1a,
msm_mux_gp_clk_1b,
msm_mux_gp_clk_2a,
msm_mux_gp_clk_2b,
msm_mux_gp_mn,
msm_mux_gp_pdm_0a,
msm_mux_gp_pdm_0b,
msm_mux_gp_pdm_1a,
msm_mux_gp_pdm_1b,
msm_mux_gp_pdm_2a,
msm_mux_gp_pdm_2b,
msm_mux_gpio,
msm_mux_gsbi1,
msm_mux_gsbi1_spi_cs1_n,
msm_mux_gsbi1_spi_cs2a_n,
msm_mux_gsbi1_spi_cs2b_n,
msm_mux_gsbi1_spi_cs3_n,
msm_mux_gsbi2,
msm_mux_gsbi2_spi_cs1_n,
msm_mux_gsbi2_spi_cs2_n,
msm_mux_gsbi2_spi_cs3_n,
msm_mux_gsbi3,
msm_mux_gsbi4,
msm_mux_gsbi4_3d_cam_i2c_l,
msm_mux_gsbi4_3d_cam_i2c_r,
msm_mux_gsbi5,
msm_mux_gsbi5_3d_cam_i2c_l,
msm_mux_gsbi5_3d_cam_i2c_r,
msm_mux_gsbi6,
msm_mux_gsbi7,
msm_mux_gsbi8,
msm_mux_gsbi9,
msm_mux_gsbi10,
msm_mux_gsbi11,
msm_mux_gsbi11_spi_cs1a_n,
msm_mux_gsbi11_spi_cs1b_n,
msm_mux_gsbi11_spi_cs2a_n,
msm_mux_gsbi11_spi_cs2b_n,
msm_mux_gsbi11_spi_cs3_n,
msm_mux_gsbi12,
msm_mux_hdmi_cec,
msm_mux_hdmi_ddc_clock,
msm_mux_hdmi_ddc_data,
msm_mux_hdmi_hot_plug_detect,
msm_mux_hsic,
msm_mux_mdp_vsync,
msm_mux_mi2s,
msm_mux_mic_i2s,
msm_mux_pmb_clk,
msm_mux_pmb_ext_ctrl,
msm_mux_ps_hold,
msm_mux_rpm_wdog,
msm_mux_sdc2,
msm_mux_sdc4,
msm_mux_sdc5,
msm_mux_slimbus1,
msm_mux_slimbus2,
msm_mux_spkr_i2s,
msm_mux_ssbi1,
msm_mux_ssbi2,
msm_mux_ssbi_ext_gps,
msm_mux_ssbi_pmic2,
msm_mux_ssbi_qpa1,
msm_mux_ssbi_ts,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_ts_eoc,
msm_mux_usb_fs1,
msm_mux_usb_fs1_oe,
msm_mux_usb_fs1_oe_n,
msm_mux_usb_fs2,
msm_mux_usb_fs2_oe,
msm_mux_usb_fs2_oe_n,
msm_mux_vfe_camif_timer1_a,
msm_mux_vfe_camif_timer1_b,
msm_mux_vfe_camif_timer2,
msm_mux_vfe_camif_timer3_a,
msm_mux_vfe_camif_timer3_b,
msm_mux_vfe_camif_timer4_a,
msm_mux_vfe_camif_timer4_b,
msm_mux_vfe_camif_timer4_c,
msm_mux_vfe_camif_timer5_a,
msm_mux_vfe_camif_timer5_b,
msm_mux_vfe_camif_timer6_a,
msm_mux_vfe_camif_timer6_b,
msm_mux_vfe_camif_timer6_c,
msm_mux_vfe_camif_timer7_a,
msm_mux_vfe_camif_timer7_b,
msm_mux_vfe_camif_timer7_c,
msm_mux_wlan,
msm_mux_NA,
};
static const char * const audio_pcm_groups[] = {
@ -956,111 +948,111 @@ static const char * const wlan_groups[] = {
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88"
};
static const struct msm_function msm8960_functions[] = {
FUNCTION(audio_pcm),
FUNCTION(bt),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cam_mclk2),
FUNCTION(codec_mic_i2s),
FUNCTION(codec_spkr_i2s),
FUNCTION(ext_gps),
FUNCTION(fm),
FUNCTION(gps_blanking),
FUNCTION(gps_pps_in),
FUNCTION(gps_pps_out),
FUNCTION(gp_clk_0a),
FUNCTION(gp_clk_0b),
FUNCTION(gp_clk_1a),
FUNCTION(gp_clk_1b),
FUNCTION(gp_clk_2a),
FUNCTION(gp_clk_2b),
FUNCTION(gp_mn),
FUNCTION(gp_pdm_0a),
FUNCTION(gp_pdm_0b),
FUNCTION(gp_pdm_1a),
FUNCTION(gp_pdm_1b),
FUNCTION(gp_pdm_2a),
FUNCTION(gp_pdm_2b),
FUNCTION(gpio),
FUNCTION(gsbi1),
FUNCTION(gsbi1_spi_cs1_n),
FUNCTION(gsbi1_spi_cs2a_n),
FUNCTION(gsbi1_spi_cs2b_n),
FUNCTION(gsbi1_spi_cs3_n),
FUNCTION(gsbi2),
FUNCTION(gsbi2_spi_cs1_n),
FUNCTION(gsbi2_spi_cs2_n),
FUNCTION(gsbi2_spi_cs3_n),
FUNCTION(gsbi3),
FUNCTION(gsbi4),
FUNCTION(gsbi4_3d_cam_i2c_l),
FUNCTION(gsbi4_3d_cam_i2c_r),
FUNCTION(gsbi5),
FUNCTION(gsbi5_3d_cam_i2c_l),
FUNCTION(gsbi5_3d_cam_i2c_r),
FUNCTION(gsbi6),
FUNCTION(gsbi7),
FUNCTION(gsbi8),
FUNCTION(gsbi9),
FUNCTION(gsbi10),
FUNCTION(gsbi11),
FUNCTION(gsbi11_spi_cs1a_n),
FUNCTION(gsbi11_spi_cs1b_n),
FUNCTION(gsbi11_spi_cs2a_n),
FUNCTION(gsbi11_spi_cs2b_n),
FUNCTION(gsbi11_spi_cs3_n),
FUNCTION(gsbi12),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc_clock),
FUNCTION(hdmi_ddc_data),
FUNCTION(hdmi_hot_plug_detect),
FUNCTION(hsic),
FUNCTION(mdp_vsync),
FUNCTION(mi2s),
FUNCTION(mic_i2s),
FUNCTION(pmb_clk),
FUNCTION(pmb_ext_ctrl),
FUNCTION(ps_hold),
FUNCTION(rpm_wdog),
FUNCTION(sdc2),
FUNCTION(sdc4),
FUNCTION(sdc5),
FUNCTION(slimbus1),
FUNCTION(slimbus2),
FUNCTION(spkr_i2s),
FUNCTION(ssbi1),
FUNCTION(ssbi2),
FUNCTION(ssbi_ext_gps),
FUNCTION(ssbi_pmic2),
FUNCTION(ssbi_qpa1),
FUNCTION(ssbi_ts),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(ts_eoc),
FUNCTION(usb_fs1),
FUNCTION(usb_fs1_oe),
FUNCTION(usb_fs1_oe_n),
FUNCTION(usb_fs2),
FUNCTION(usb_fs2_oe),
FUNCTION(usb_fs2_oe_n),
FUNCTION(vfe_camif_timer1_a),
FUNCTION(vfe_camif_timer1_b),
FUNCTION(vfe_camif_timer2),
FUNCTION(vfe_camif_timer3_a),
FUNCTION(vfe_camif_timer3_b),
FUNCTION(vfe_camif_timer4_a),
FUNCTION(vfe_camif_timer4_b),
FUNCTION(vfe_camif_timer4_c),
FUNCTION(vfe_camif_timer5_a),
FUNCTION(vfe_camif_timer5_b),
FUNCTION(vfe_camif_timer6_a),
FUNCTION(vfe_camif_timer6_b),
FUNCTION(vfe_camif_timer6_c),
FUNCTION(vfe_camif_timer7_a),
FUNCTION(vfe_camif_timer7_b),
FUNCTION(vfe_camif_timer7_c),
FUNCTION(wlan),
static const struct pinfunction msm8960_functions[] = {
MSM_PIN_FUNCTION(audio_pcm),
MSM_PIN_FUNCTION(bt),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(codec_mic_i2s),
MSM_PIN_FUNCTION(codec_spkr_i2s),
MSM_PIN_FUNCTION(ext_gps),
MSM_PIN_FUNCTION(fm),
MSM_PIN_FUNCTION(gps_blanking),
MSM_PIN_FUNCTION(gps_pps_in),
MSM_PIN_FUNCTION(gps_pps_out),
MSM_PIN_FUNCTION(gp_clk_0a),
MSM_PIN_FUNCTION(gp_clk_0b),
MSM_PIN_FUNCTION(gp_clk_1a),
MSM_PIN_FUNCTION(gp_clk_1b),
MSM_PIN_FUNCTION(gp_clk_2a),
MSM_PIN_FUNCTION(gp_clk_2b),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(gp_pdm_0a),
MSM_PIN_FUNCTION(gp_pdm_0b),
MSM_PIN_FUNCTION(gp_pdm_1a),
MSM_PIN_FUNCTION(gp_pdm_1b),
MSM_PIN_FUNCTION(gp_pdm_2a),
MSM_PIN_FUNCTION(gp_pdm_2b),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsbi1),
MSM_PIN_FUNCTION(gsbi1_spi_cs1_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs2a_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs2b_n),
MSM_PIN_FUNCTION(gsbi1_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi2),
MSM_PIN_FUNCTION(gsbi2_spi_cs1_n),
MSM_PIN_FUNCTION(gsbi2_spi_cs2_n),
MSM_PIN_FUNCTION(gsbi2_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi3),
MSM_PIN_FUNCTION(gsbi4),
MSM_PIN_FUNCTION(gsbi4_3d_cam_i2c_l),
MSM_PIN_FUNCTION(gsbi4_3d_cam_i2c_r),
MSM_PIN_FUNCTION(gsbi5),
MSM_PIN_FUNCTION(gsbi5_3d_cam_i2c_l),
MSM_PIN_FUNCTION(gsbi5_3d_cam_i2c_r),
MSM_PIN_FUNCTION(gsbi6),
MSM_PIN_FUNCTION(gsbi7),
MSM_PIN_FUNCTION(gsbi8),
MSM_PIN_FUNCTION(gsbi9),
MSM_PIN_FUNCTION(gsbi10),
MSM_PIN_FUNCTION(gsbi11),
MSM_PIN_FUNCTION(gsbi11_spi_cs1a_n),
MSM_PIN_FUNCTION(gsbi11_spi_cs1b_n),
MSM_PIN_FUNCTION(gsbi11_spi_cs2a_n),
MSM_PIN_FUNCTION(gsbi11_spi_cs2b_n),
MSM_PIN_FUNCTION(gsbi11_spi_cs3_n),
MSM_PIN_FUNCTION(gsbi12),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc_clock),
MSM_PIN_FUNCTION(hdmi_ddc_data),
MSM_PIN_FUNCTION(hdmi_hot_plug_detect),
MSM_PIN_FUNCTION(hsic),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mi2s),
MSM_PIN_FUNCTION(mic_i2s),
MSM_PIN_FUNCTION(pmb_clk),
MSM_PIN_FUNCTION(pmb_ext_ctrl),
MSM_PIN_FUNCTION(ps_hold),
MSM_PIN_FUNCTION(rpm_wdog),
MSM_PIN_FUNCTION(sdc2),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sdc5),
MSM_PIN_FUNCTION(slimbus1),
MSM_PIN_FUNCTION(slimbus2),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ssbi1),
MSM_PIN_FUNCTION(ssbi2),
MSM_PIN_FUNCTION(ssbi_ext_gps),
MSM_PIN_FUNCTION(ssbi_pmic2),
MSM_PIN_FUNCTION(ssbi_qpa1),
MSM_PIN_FUNCTION(ssbi_ts),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(ts_eoc),
MSM_PIN_FUNCTION(usb_fs1),
MSM_PIN_FUNCTION(usb_fs1_oe),
MSM_PIN_FUNCTION(usb_fs1_oe_n),
MSM_PIN_FUNCTION(usb_fs2),
MSM_PIN_FUNCTION(usb_fs2_oe),
MSM_PIN_FUNCTION(usb_fs2_oe_n),
MSM_PIN_FUNCTION(vfe_camif_timer1_a),
MSM_PIN_FUNCTION(vfe_camif_timer1_b),
MSM_PIN_FUNCTION(vfe_camif_timer2),
MSM_PIN_FUNCTION(vfe_camif_timer3_a),
MSM_PIN_FUNCTION(vfe_camif_timer3_b),
MSM_PIN_FUNCTION(vfe_camif_timer4_a),
MSM_PIN_FUNCTION(vfe_camif_timer4_b),
MSM_PIN_FUNCTION(vfe_camif_timer4_c),
MSM_PIN_FUNCTION(vfe_camif_timer5_a),
MSM_PIN_FUNCTION(vfe_camif_timer5_b),
MSM_PIN_FUNCTION(vfe_camif_timer6_a),
MSM_PIN_FUNCTION(vfe_camif_timer6_b),
MSM_PIN_FUNCTION(vfe_camif_timer6_c),
MSM_PIN_FUNCTION(vfe_camif_timer7_a),
MSM_PIN_FUNCTION(vfe_camif_timer7_b),
MSM_PIN_FUNCTION(vfe_camif_timer7_c),
MSM_PIN_FUNCTION(wlan),
};
static const struct msm_pingroup msm8960_groups[] = {

212
drivers/pinctrl/qcom/pinctrl-msm8976.c
View File

@ -8,24 +8,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x0
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -62,9 +54,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -819,102 +811,102 @@ static const char * const ss_switch_groups[] = {
"gpio139",
};
static const struct msm_function msm8976_functions[] = {
FUNCTION(gpio),
FUNCTION(blsp_spi1),
FUNCTION(smb_int),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_i2c2),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(blsp_spi3),
FUNCTION(qdss_tracedata_b),
FUNCTION(blsp_i2c3),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(blsp_spi4),
FUNCTION(cap_int),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_uart5),
FUNCTION(qdss_traceclk_a),
FUNCTION(m_voc),
FUNCTION(blsp_i2c5),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracedata_a),
FUNCTION(blsp_spi6),
FUNCTION(blsp_uart6),
FUNCTION(qdss_tracectl_b),
FUNCTION(blsp_i2c6),
FUNCTION(qdss_traceclk_b),
FUNCTION(mdp_vsync),
FUNCTION(pri_mi2s_mclk_a),
FUNCTION(sec_mi2s_mclk_a),
FUNCTION(cam_mclk),
FUNCTION(cci0_i2c),
FUNCTION(cci1_i2c),
FUNCTION(blsp1_spi),
FUNCTION(blsp3_spi),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(uim_batt),
FUNCTION(sd_write),
FUNCTION(uim1_data),
FUNCTION(uim1_clk),
FUNCTION(uim1_reset),
FUNCTION(uim1_present),
FUNCTION(uim2_data),
FUNCTION(uim2_clk),
FUNCTION(uim2_reset),
FUNCTION(uim2_present),
FUNCTION(ts_xvdd),
FUNCTION(mipi_dsi0),
FUNCTION(us_euro),
FUNCTION(ts_resout),
FUNCTION(ts_sample),
FUNCTION(sec_mi2s_mclk_b),
FUNCTION(pri_mi2s),
FUNCTION(codec_reset),
FUNCTION(cdc_pdm0),
FUNCTION(us_emitter),
FUNCTION(pri_mi2s_mclk_b),
FUNCTION(pri_mi2s_mclk_c),
FUNCTION(lpass_slimbus),
FUNCTION(lpass_slimbus0),
FUNCTION(lpass_slimbus1),
FUNCTION(codec_int1),
FUNCTION(codec_int2),
FUNCTION(wcss_bt),
FUNCTION(sdc3),
FUNCTION(wcss_wlan2),
FUNCTION(wcss_wlan1),
FUNCTION(wcss_wlan0),
FUNCTION(wcss_wlan),
FUNCTION(wcss_fm),
FUNCTION(key_volp),
FUNCTION(key_snapshot),
FUNCTION(key_focus),
FUNCTION(key_home),
FUNCTION(pwr_down),
FUNCTION(dmic0_clk),
FUNCTION(hdmi_int),
FUNCTION(dmic0_data),
FUNCTION(wsa_vi),
FUNCTION(wsa_en),
FUNCTION(blsp_spi8),
FUNCTION(wsa_irq),
FUNCTION(blsp_i2c8),
FUNCTION(pa_indicator),
FUNCTION(modem_tsync),
FUNCTION(ssbi_wtr1),
FUNCTION(gsm1_tx),
FUNCTION(gsm0_tx),
FUNCTION(sdcard_det),
FUNCTION(sec_mi2s),
FUNCTION(ss_switch),
static const struct pinfunction msm8976_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(smb_int),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(cap_int),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(pri_mi2s_mclk_a),
MSM_PIN_FUNCTION(sec_mi2s_mclk_a),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci0_i2c),
MSM_PIN_FUNCTION(cci1_i2c),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp3_spi),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(ts_xvdd),
MSM_PIN_FUNCTION(mipi_dsi0),
MSM_PIN_FUNCTION(us_euro),
MSM_PIN_FUNCTION(ts_resout),
MSM_PIN_FUNCTION(ts_sample),
MSM_PIN_FUNCTION(sec_mi2s_mclk_b),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(codec_reset),
MSM_PIN_FUNCTION(cdc_pdm0),
MSM_PIN_FUNCTION(us_emitter),
MSM_PIN_FUNCTION(pri_mi2s_mclk_b),
MSM_PIN_FUNCTION(pri_mi2s_mclk_c),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(lpass_slimbus0),
MSM_PIN_FUNCTION(lpass_slimbus1),
MSM_PIN_FUNCTION(codec_int1),
MSM_PIN_FUNCTION(codec_int2),
MSM_PIN_FUNCTION(wcss_bt),
MSM_PIN_FUNCTION(sdc3),
MSM_PIN_FUNCTION(wcss_wlan2),
MSM_PIN_FUNCTION(wcss_wlan1),
MSM_PIN_FUNCTION(wcss_wlan0),
MSM_PIN_FUNCTION(wcss_wlan),
MSM_PIN_FUNCTION(wcss_fm),
MSM_PIN_FUNCTION(key_volp),
MSM_PIN_FUNCTION(key_snapshot),
MSM_PIN_FUNCTION(key_focus),
MSM_PIN_FUNCTION(key_home),
MSM_PIN_FUNCTION(pwr_down),
MSM_PIN_FUNCTION(dmic0_clk),
MSM_PIN_FUNCTION(hdmi_int),
MSM_PIN_FUNCTION(dmic0_data),
MSM_PIN_FUNCTION(wsa_vi),
MSM_PIN_FUNCTION(wsa_en),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(wsa_irq),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(ssbi_wtr1),
MSM_PIN_FUNCTION(gsm1_tx),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(sdcard_det),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(ss_switch),
};
static const struct msm_pingroup msm8976_groups[] = {

564
drivers/pinctrl/qcom/pinctrl-msm8994.c
View File

@ -6,35 +6,27 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7, \
MSM_MUX_##f8, \
MSM_MUX_##f9, \
MSM_MUX_##f10, \
MSM_MUX_##f11 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7, \
msm_mux_##f8, \
msm_mux_##f9, \
msm_mux_##f10, \
msm_mux_##f11 \
}, \
.nfuncs = 12, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -60,9 +52,9 @@
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -403,136 +395,136 @@ static const unsigned int sdc3_cmd_pins[] = { 154 };
static const unsigned int sdc3_data_pins[] = { 155 };
enum msm8994_functions {
MSM_MUX_audio_ref_clk,
MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
MSM_MUX_blsp_i2c3,
MSM_MUX_blsp_i2c4,
MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_i2c6,
MSM_MUX_blsp_i2c7,
MSM_MUX_blsp_i2c8,
MSM_MUX_blsp_i2c9,
MSM_MUX_blsp_i2c10,
MSM_MUX_blsp_i2c11,
MSM_MUX_blsp_i2c12,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi1_cs1,
MSM_MUX_blsp_spi1_cs2,
MSM_MUX_blsp_spi1_cs3,
MSM_MUX_blsp_spi2,
MSM_MUX_blsp_spi2_cs1,
MSM_MUX_blsp_spi2_cs2,
MSM_MUX_blsp_spi2_cs3,
MSM_MUX_blsp_spi3,
MSM_MUX_blsp_spi4,
MSM_MUX_blsp_spi5,
MSM_MUX_blsp_spi6,
MSM_MUX_blsp_spi7,
MSM_MUX_blsp_spi8,
MSM_MUX_blsp_spi9,
MSM_MUX_blsp_spi10,
MSM_MUX_blsp_spi10_cs1,
MSM_MUX_blsp_spi10_cs2,
MSM_MUX_blsp_spi10_cs3,
MSM_MUX_blsp_spi11,
MSM_MUX_blsp_spi12,
MSM_MUX_blsp_uart1,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart3,
MSM_MUX_blsp_uart4,
MSM_MUX_blsp_uart5,
MSM_MUX_blsp_uart6,
MSM_MUX_blsp_uart7,
MSM_MUX_blsp_uart8,
MSM_MUX_blsp_uart9,
MSM_MUX_blsp_uart10,
MSM_MUX_blsp_uart11,
MSM_MUX_blsp_uart12,
MSM_MUX_blsp_uim1,
MSM_MUX_blsp_uim2,
MSM_MUX_blsp_uim3,
MSM_MUX_blsp_uim4,
MSM_MUX_blsp_uim5,
MSM_MUX_blsp_uim6,
MSM_MUX_blsp_uim7,
MSM_MUX_blsp_uim8,
MSM_MUX_blsp_uim9,
MSM_MUX_blsp_uim10,
MSM_MUX_blsp_uim11,
MSM_MUX_blsp_uim12,
MSM_MUX_blsp11_i2c_scl_b,
MSM_MUX_blsp11_i2c_sda_b,
MSM_MUX_blsp11_uart_rx_b,
MSM_MUX_blsp11_uart_tx_b,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_cam_mclk2,
MSM_MUX_cam_mclk3,
MSM_MUX_cci_async_in0,
MSM_MUX_cci_async_in1,
MSM_MUX_cci_async_in2,
MSM_MUX_cci_i2c0,
MSM_MUX_cci_i2c1,
MSM_MUX_cci_timer0,
MSM_MUX_cci_timer1,
MSM_MUX_cci_timer2,
MSM_MUX_cci_timer3,
MSM_MUX_cci_timer4,
MSM_MUX_gcc_gp1_clk_a,
MSM_MUX_gcc_gp1_clk_b,
MSM_MUX_gcc_gp2_clk_a,
MSM_MUX_gcc_gp2_clk_b,
MSM_MUX_gcc_gp3_clk_a,
MSM_MUX_gcc_gp3_clk_b,
MSM_MUX_gp_mn,
MSM_MUX_gp_pdm0,
MSM_MUX_gp_pdm1,
MSM_MUX_gp_pdm2,
MSM_MUX_gp0_clk,
MSM_MUX_gp1_clk,
MSM_MUX_gps_tx,
MSM_MUX_gsm_tx,
MSM_MUX_hdmi_cec,
MSM_MUX_hdmi_ddc,
MSM_MUX_hdmi_hpd,
MSM_MUX_hdmi_rcv,
MSM_MUX_mdp_vsync,
MSM_MUX_mss_lte,
MSM_MUX_nav_pps,
MSM_MUX_nav_tsync,
MSM_MUX_qdss_cti_trig_in_a,
MSM_MUX_qdss_cti_trig_in_b,
MSM_MUX_qdss_cti_trig_in_c,
MSM_MUX_qdss_cti_trig_in_d,
MSM_MUX_qdss_cti_trig_out_a,
MSM_MUX_qdss_cti_trig_out_b,
MSM_MUX_qdss_cti_trig_out_c,
MSM_MUX_qdss_cti_trig_out_d,
MSM_MUX_qdss_traceclk_a,
MSM_MUX_qdss_traceclk_b,
MSM_MUX_qdss_tracectl_a,
MSM_MUX_qdss_tracectl_b,
MSM_MUX_qdss_tracedata_a,
MSM_MUX_qdss_tracedata_b,
MSM_MUX_qua_mi2s,
MSM_MUX_pci_e0,
MSM_MUX_pci_e1,
MSM_MUX_pri_mi2s,
MSM_MUX_sdc4,
MSM_MUX_sec_mi2s,
MSM_MUX_slimbus,
MSM_MUX_spkr_i2s,
MSM_MUX_ter_mi2s,
MSM_MUX_tsif1,
MSM_MUX_tsif2,
MSM_MUX_uim1,
MSM_MUX_uim2,
MSM_MUX_uim3,
MSM_MUX_uim4,
MSM_MUX_uim_batt_alarm,
MSM_MUX_gpio,
MSM_MUX_NA,
msm_mux_audio_ref_clk,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_i2c7,
msm_mux_blsp_i2c8,
msm_mux_blsp_i2c9,
msm_mux_blsp_i2c10,
msm_mux_blsp_i2c11,
msm_mux_blsp_i2c12,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi2_cs1,
msm_mux_blsp_spi2_cs2,
msm_mux_blsp_spi2_cs3,
msm_mux_blsp_spi3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_spi7,
msm_mux_blsp_spi8,
msm_mux_blsp_spi9,
msm_mux_blsp_spi10,
msm_mux_blsp_spi10_cs1,
msm_mux_blsp_spi10_cs2,
msm_mux_blsp_spi10_cs3,
msm_mux_blsp_spi11,
msm_mux_blsp_spi12,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uart3,
msm_mux_blsp_uart4,
msm_mux_blsp_uart5,
msm_mux_blsp_uart6,
msm_mux_blsp_uart7,
msm_mux_blsp_uart8,
msm_mux_blsp_uart9,
msm_mux_blsp_uart10,
msm_mux_blsp_uart11,
msm_mux_blsp_uart12,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_blsp_uim3,
msm_mux_blsp_uim4,
msm_mux_blsp_uim5,
msm_mux_blsp_uim6,
msm_mux_blsp_uim7,
msm_mux_blsp_uim8,
msm_mux_blsp_uim9,
msm_mux_blsp_uim10,
msm_mux_blsp_uim11,
msm_mux_blsp_uim12,
msm_mux_blsp11_i2c_scl_b,
msm_mux_blsp11_i2c_sda_b,
msm_mux_blsp11_uart_rx_b,
msm_mux_blsp11_uart_tx_b,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cam_mclk2,
msm_mux_cam_mclk3,
msm_mux_cci_async_in0,
msm_mux_cci_async_in1,
msm_mux_cci_async_in2,
msm_mux_cci_i2c0,
msm_mux_cci_i2c1,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cci_timer3,
msm_mux_cci_timer4,
msm_mux_gcc_gp1_clk_a,
msm_mux_gcc_gp1_clk_b,
msm_mux_gcc_gp2_clk_a,
msm_mux_gcc_gp2_clk_b,
msm_mux_gcc_gp3_clk_a,
msm_mux_gcc_gp3_clk_b,
msm_mux_gp_mn,
msm_mux_gp_pdm0,
msm_mux_gp_pdm1,
msm_mux_gp_pdm2,
msm_mux_gp0_clk,
msm_mux_gp1_clk,
msm_mux_gps_tx,
msm_mux_gsm_tx,
msm_mux_hdmi_cec,
msm_mux_hdmi_ddc,
msm_mux_hdmi_hpd,
msm_mux_hdmi_rcv,
msm_mux_mdp_vsync,
msm_mux_mss_lte,
msm_mux_nav_pps,
msm_mux_nav_tsync,
msm_mux_qdss_cti_trig_in_a,
msm_mux_qdss_cti_trig_in_b,
msm_mux_qdss_cti_trig_in_c,
msm_mux_qdss_cti_trig_in_d,
msm_mux_qdss_cti_trig_out_a,
msm_mux_qdss_cti_trig_out_b,
msm_mux_qdss_cti_trig_out_c,
msm_mux_qdss_cti_trig_out_d,
msm_mux_qdss_traceclk_a,
msm_mux_qdss_traceclk_b,
msm_mux_qdss_tracectl_a,
msm_mux_qdss_tracectl_b,
msm_mux_qdss_tracedata_a,
msm_mux_qdss_tracedata_b,
msm_mux_qua_mi2s,
msm_mux_pci_e0,
msm_mux_pci_e1,
msm_mux_pri_mi2s,
msm_mux_sdc4,
msm_mux_sec_mi2s,
msm_mux_slimbus,
msm_mux_spkr_i2s,
msm_mux_ter_mi2s,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_uim1,
msm_mux_uim2,
msm_mux_uim3,
msm_mux_uim4,
msm_mux_uim_batt_alarm,
msm_mux_gpio,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -950,136 +942,136 @@ static const char * const mss_lte_groups[] = {
"gpio134", "gpio135"
};
static const struct msm_function msm8994_functions[] = {
FUNCTION(audio_ref_clk),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_i2c9),
FUNCTION(blsp_i2c10),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_i2c12),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi2_cs1),
FUNCTION(blsp_spi2_cs2),
FUNCTION(blsp_spi2_cs3),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_spi9),
FUNCTION(blsp_spi10),
FUNCTION(blsp_spi10_cs1),
FUNCTION(blsp_spi10_cs2),
FUNCTION(blsp_spi10_cs3),
FUNCTION(blsp_spi11),
FUNCTION(blsp_spi12),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(blsp_uart7),
FUNCTION(blsp_uart8),
FUNCTION(blsp_uart9),
FUNCTION(blsp_uart10),
FUNCTION(blsp_uart11),
FUNCTION(blsp_uart12),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim4),
FUNCTION(blsp_uim5),
FUNCTION(blsp_uim6),
FUNCTION(blsp_uim7),
FUNCTION(blsp_uim8),
FUNCTION(blsp_uim9),
FUNCTION(blsp_uim10),
FUNCTION(blsp_uim11),
FUNCTION(blsp_uim12),
FUNCTION(blsp11_i2c_scl_b),
FUNCTION(blsp11_i2c_sda_b),
FUNCTION(blsp11_uart_rx_b),
FUNCTION(blsp11_uart_tx_b),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cam_mclk2),
FUNCTION(cam_mclk3),
FUNCTION(cci_async_in0),
FUNCTION(cci_async_in1),
FUNCTION(cci_async_in2),
FUNCTION(cci_i2c0),
FUNCTION(cci_i2c1),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gp_mn),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gp0_clk),
FUNCTION(gp1_clk),
FUNCTION(gps_tx),
FUNCTION(gsm_tx),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc),
FUNCTION(hdmi_hpd),
FUNCTION(hdmi_rcv),
FUNCTION(mdp_vsync),
FUNCTION(mss_lte),
FUNCTION(nav_pps),
FUNCTION(nav_tsync),
FUNCTION(qdss_cti_trig_in_a),
FUNCTION(qdss_cti_trig_in_b),
FUNCTION(qdss_cti_trig_in_c),
FUNCTION(qdss_cti_trig_in_d),
FUNCTION(qdss_cti_trig_out_a),
FUNCTION(qdss_cti_trig_out_b),
FUNCTION(qdss_cti_trig_out_c),
FUNCTION(qdss_cti_trig_out_d),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(qua_mi2s),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(pri_mi2s),
FUNCTION(sdc4),
FUNCTION(sec_mi2s),
FUNCTION(slimbus),
FUNCTION(spkr_i2s),
FUNCTION(ter_mi2s),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(uim_batt_alarm),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim3),
FUNCTION(uim4),
FUNCTION(gpio),
static const struct pinfunction msm8994_functions[] = {
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi2_cs1),
MSM_PIN_FUNCTION(blsp_spi2_cs2),
MSM_PIN_FUNCTION(blsp_spi2_cs3),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi10_cs1),
MSM_PIN_FUNCTION(blsp_spi10_cs2),
MSM_PIN_FUNCTION(blsp_spi10_cs3),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uart7),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart9),
MSM_PIN_FUNCTION(blsp_uart10),
MSM_PIN_FUNCTION(blsp_uart11),
MSM_PIN_FUNCTION(blsp_uart12),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(blsp_uim7),
MSM_PIN_FUNCTION(blsp_uim8),
MSM_PIN_FUNCTION(blsp_uim9),
MSM_PIN_FUNCTION(blsp_uim10),
MSM_PIN_FUNCTION(blsp_uim11),
MSM_PIN_FUNCTION(blsp_uim12),
MSM_PIN_FUNCTION(blsp11_i2c_scl_b),
MSM_PIN_FUNCTION(blsp11_i2c_sda_b),
MSM_PIN_FUNCTION(blsp11_uart_rx_b),
MSM_PIN_FUNCTION(blsp11_uart_tx_b),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(cam_mclk3),
MSM_PIN_FUNCTION(cci_async_in0),
MSM_PIN_FUNCTION(cci_async_in1),
MSM_PIN_FUNCTION(cci_async_in2),
MSM_PIN_FUNCTION(cci_i2c0),
MSM_PIN_FUNCTION(cci_i2c1),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gp0_clk),
MSM_PIN_FUNCTION(gp1_clk),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(gsm_tx),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_hpd),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(nav_tsync),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b),
MSM_PIN_FUNCTION(qdss_cti_trig_in_c),
MSM_PIN_FUNCTION(qdss_cti_trig_in_d),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b),
MSM_PIN_FUNCTION(qdss_cti_trig_out_c),
MSM_PIN_FUNCTION(qdss_cti_trig_out_d),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(uim_batt_alarm),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim3),
MSM_PIN_FUNCTION(uim4),
MSM_PIN_FUNCTION(gpio),
};
static const struct msm_pingroup msm8994_groups[] = {

508
drivers/pinctrl/qcom/pinctrl-msm8996.c
View File

@ -6,24 +6,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x0
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -1409,250 +1401,250 @@ static const char * const qspi3_groups[] = {
"gpio149",
};
static const struct msm_function msm8996_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(atest_bbrx0),
FUNCTION(atest_bbrx1),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb2),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(audio_ref),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp10_spi),
FUNCTION(blsp11_i2c_scl_b),
FUNCTION(blsp11_i2c_sda_b),
FUNCTION(blsp11_uart_rx_b),
FUNCTION(blsp11_uart_tx_b),
FUNCTION(blsp1_spi),
FUNCTION(blsp2_spi),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c10),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_i2c12),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_i2c9),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi10),
FUNCTION(blsp_spi11),
FUNCTION(blsp_spi12),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_spi9),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart10),
FUNCTION(blsp_uart11),
FUNCTION(blsp_uart12),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(blsp_uart7),
FUNCTION(blsp_uart8),
FUNCTION(blsp_uart9),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim10),
FUNCTION(blsp_uim11),
FUNCTION(blsp_uim12),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim4),
FUNCTION(blsp_uim5),
FUNCTION(blsp_uim6),
FUNCTION(blsp_uim7),
FUNCTION(blsp_uim8),
FUNCTION(blsp_uim9),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dac_calib0),
FUNCTION(dac_calib1),
FUNCTION(dac_calib10),
FUNCTION(dac_calib11),
FUNCTION(dac_calib12),
FUNCTION(dac_calib13),
FUNCTION(dac_calib14),
FUNCTION(dac_calib15),
FUNCTION(dac_calib16),
FUNCTION(dac_calib17),
FUNCTION(dac_calib18),
FUNCTION(dac_calib19),
FUNCTION(dac_calib2),
FUNCTION(dac_calib20),
FUNCTION(dac_calib21),
FUNCTION(dac_calib22),
FUNCTION(dac_calib23),
FUNCTION(dac_calib24),
FUNCTION(dac_calib25),
FUNCTION(dac_calib26),
FUNCTION(dac_calib3),
FUNCTION(dac_calib4),
FUNCTION(dac_calib5),
FUNCTION(dac_calib6),
FUNCTION(dac_calib7),
FUNCTION(dac_calib8),
FUNCTION(dac_calib9),
FUNCTION(dac_gpio),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(gpio),
FUNCTION(gsm_tx),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc),
FUNCTION(hdmi_hot),
FUNCTION(hdmi_rcv),
FUNCTION(isense_dbg),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_slimbus),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync_p_b),
FUNCTION(mdp_vsync_s_b),
FUNCTION(modem_tsync),
FUNCTION(mss_lte),
FUNCTION(nav_dr),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(pci_e2),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto),
FUNCTION(pwr_modem),
FUNCTION(pwr_nav),
FUNCTION(qdss_cti),
FUNCTION(qdss_cti_trig_in_a),
FUNCTION(qdss_cti_trig_in_b),
FUNCTION(qdss_cti_trig_out_a),
FUNCTION(qdss_cti_trig_out_b),
FUNCTION(qdss_stm0),
FUNCTION(qdss_stm1),
FUNCTION(qdss_stm10),
FUNCTION(qdss_stm11),
FUNCTION(qdss_stm12),
FUNCTION(qdss_stm13),
FUNCTION(qdss_stm14),
FUNCTION(qdss_stm15),
FUNCTION(qdss_stm16),
FUNCTION(qdss_stm17),
FUNCTION(qdss_stm18),
FUNCTION(qdss_stm19),
FUNCTION(qdss_stm2),
FUNCTION(qdss_stm20),
FUNCTION(qdss_stm21),
FUNCTION(qdss_stm22),
FUNCTION(qdss_stm23),
FUNCTION(qdss_stm24),
FUNCTION(qdss_stm25),
FUNCTION(qdss_stm26),
FUNCTION(qdss_stm27),
FUNCTION(qdss_stm28),
FUNCTION(qdss_stm29),
FUNCTION(qdss_stm3),
FUNCTION(qdss_stm30),
FUNCTION(qdss_stm31),
FUNCTION(qdss_stm4),
FUNCTION(qdss_stm5),
FUNCTION(qdss_stm6),
FUNCTION(qdss_stm7),
FUNCTION(qdss_stm8),
FUNCTION(qdss_stm9),
FUNCTION(qdss_traceclk_a),
FUNCTION(qdss_traceclk_b),
FUNCTION(qdss_tracectl_a),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_tracedata_11),
FUNCTION(qdss_tracedata_12),
FUNCTION(qdss_tracedata_a),
FUNCTION(qdss_tracedata_b),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qua_mi2s),
FUNCTION(sd_card),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(spkr_i2s),
FUNCTION(ssbi1),
FUNCTION(ssbi2),
FUNCTION(ssc_irq),
FUNCTION(ter_mi2s),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(tsif2_clk),
FUNCTION(tsif2_data),
FUNCTION(tsif2_en),
FUNCTION(tsif2_error),
FUNCTION(tsif2_sync),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim3),
FUNCTION(uim4),
FUNCTION(uim_batt),
FUNCTION(vfr_1),
static const struct pinfunction msm8996_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest_bbrx0),
MSM_PIN_FUNCTION(atest_bbrx1),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_gpsadc0),
MSM_PIN_FUNCTION(atest_gpsadc1),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp10_spi),
MSM_PIN_FUNCTION(blsp11_i2c_scl_b),
MSM_PIN_FUNCTION(blsp11_i2c_sda_b),
MSM_PIN_FUNCTION(blsp11_uart_rx_b),
MSM_PIN_FUNCTION(blsp11_uart_tx_b),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart10),
MSM_PIN_FUNCTION(blsp_uart11),
MSM_PIN_FUNCTION(blsp_uart12),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uart7),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart9),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim10),
MSM_PIN_FUNCTION(blsp_uim11),
MSM_PIN_FUNCTION(blsp_uim12),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(blsp_uim7),
MSM_PIN_FUNCTION(blsp_uim8),
MSM_PIN_FUNCTION(blsp_uim9),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dac_calib0),
MSM_PIN_FUNCTION(dac_calib1),
MSM_PIN_FUNCTION(dac_calib10),
MSM_PIN_FUNCTION(dac_calib11),
MSM_PIN_FUNCTION(dac_calib12),
MSM_PIN_FUNCTION(dac_calib13),
MSM_PIN_FUNCTION(dac_calib14),
MSM_PIN_FUNCTION(dac_calib15),
MSM_PIN_FUNCTION(dac_calib16),
MSM_PIN_FUNCTION(dac_calib17),
MSM_PIN_FUNCTION(dac_calib18),
MSM_PIN_FUNCTION(dac_calib19),
MSM_PIN_FUNCTION(dac_calib2),
MSM_PIN_FUNCTION(dac_calib20),
MSM_PIN_FUNCTION(dac_calib21),
MSM_PIN_FUNCTION(dac_calib22),
MSM_PIN_FUNCTION(dac_calib23),
MSM_PIN_FUNCTION(dac_calib24),
MSM_PIN_FUNCTION(dac_calib25),
MSM_PIN_FUNCTION(dac_calib26),
MSM_PIN_FUNCTION(dac_calib3),
MSM_PIN_FUNCTION(dac_calib4),
MSM_PIN_FUNCTION(dac_calib5),
MSM_PIN_FUNCTION(dac_calib6),
MSM_PIN_FUNCTION(dac_calib7),
MSM_PIN_FUNCTION(dac_calib8),
MSM_PIN_FUNCTION(dac_calib9),
MSM_PIN_FUNCTION(dac_gpio),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gsm_tx),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_hot),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(isense_dbg),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync_p_b),
MSM_PIN_FUNCTION(mdp_vsync_s_b),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_dr),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pci_e2),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto),
MSM_PIN_FUNCTION(pwr_modem),
MSM_PIN_FUNCTION(pwr_nav),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b),
MSM_PIN_FUNCTION(qdss_stm0),
MSM_PIN_FUNCTION(qdss_stm1),
MSM_PIN_FUNCTION(qdss_stm10),
MSM_PIN_FUNCTION(qdss_stm11),
MSM_PIN_FUNCTION(qdss_stm12),
MSM_PIN_FUNCTION(qdss_stm13),
MSM_PIN_FUNCTION(qdss_stm14),
MSM_PIN_FUNCTION(qdss_stm15),
MSM_PIN_FUNCTION(qdss_stm16),
MSM_PIN_FUNCTION(qdss_stm17),
MSM_PIN_FUNCTION(qdss_stm18),
MSM_PIN_FUNCTION(qdss_stm19),
MSM_PIN_FUNCTION(qdss_stm2),
MSM_PIN_FUNCTION(qdss_stm20),
MSM_PIN_FUNCTION(qdss_stm21),
MSM_PIN_FUNCTION(qdss_stm22),
MSM_PIN_FUNCTION(qdss_stm23),
MSM_PIN_FUNCTION(qdss_stm24),
MSM_PIN_FUNCTION(qdss_stm25),
MSM_PIN_FUNCTION(qdss_stm26),
MSM_PIN_FUNCTION(qdss_stm27),
MSM_PIN_FUNCTION(qdss_stm28),
MSM_PIN_FUNCTION(qdss_stm29),
MSM_PIN_FUNCTION(qdss_stm3),
MSM_PIN_FUNCTION(qdss_stm30),
MSM_PIN_FUNCTION(qdss_stm31),
MSM_PIN_FUNCTION(qdss_stm4),
MSM_PIN_FUNCTION(qdss_stm5),
MSM_PIN_FUNCTION(qdss_stm6),
MSM_PIN_FUNCTION(qdss_stm7),
MSM_PIN_FUNCTION(qdss_stm8),
MSM_PIN_FUNCTION(qdss_stm9),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_tracedata_11),
MSM_PIN_FUNCTION(qdss_tracedata_12),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ssbi1),
MSM_PIN_FUNCTION(ssbi2),
MSM_PIN_FUNCTION(ssc_irq),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif1_clk),
MSM_PIN_FUNCTION(tsif1_data),
MSM_PIN_FUNCTION(tsif1_en),
MSM_PIN_FUNCTION(tsif1_error),
MSM_PIN_FUNCTION(tsif1_sync),
MSM_PIN_FUNCTION(tsif2_clk),
MSM_PIN_FUNCTION(tsif2_data),
MSM_PIN_FUNCTION(tsif2_en),
MSM_PIN_FUNCTION(tsif2_error),
MSM_PIN_FUNCTION(tsif2_sync),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim3),
MSM_PIN_FUNCTION(uim4),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(vfr_1),
};
static const struct msm_pingroup msm8996_groups[] = {

380
drivers/pinctrl/qcom/pinctrl-msm8998.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -14,18 +13,11 @@
#define WEST 0x100000
#define EAST 0x900000
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -62,9 +54,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -87,9 +79,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1167,183 +1159,183 @@ static const char * const mss_lte_groups[] = {
"gpio144", "gpio145",
};
static const struct msm_function msm8998_functions[] = {
FUNCTION(gpio),
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(audio_ref),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp10_spi),
FUNCTION(blsp10_spi_a),
FUNCTION(blsp10_spi_b),
FUNCTION(blsp11_i2c),
FUNCTION(blsp1_spi),
FUNCTION(blsp1_spi_a),
FUNCTION(blsp1_spi_b),
FUNCTION(blsp2_spi),
FUNCTION(blsp9_spi),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_i2c9),
FUNCTION(blsp_i2c10),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_i2c12),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_spi9),
FUNCTION(blsp_spi10),
FUNCTION(blsp_spi11),
FUNCTION(blsp_spi12),
FUNCTION(blsp_uart1_a),
FUNCTION(blsp_uart1_b),
FUNCTION(blsp_uart2_a),
FUNCTION(blsp_uart2_b),
FUNCTION(blsp_uart3_a),
FUNCTION(blsp_uart3_b),
FUNCTION(blsp_uart7_a),
FUNCTION(blsp_uart7_b),
FUNCTION(blsp_uart8),
FUNCTION(blsp_uart8_a),
FUNCTION(blsp_uart8_b),
FUNCTION(blsp_uart9_a),
FUNCTION(blsp_uart9_b),
FUNCTION(blsp_uim1_a),
FUNCTION(blsp_uim1_b),
FUNCTION(blsp_uim2_a),
FUNCTION(blsp_uim2_b),
FUNCTION(blsp_uim3_a),
FUNCTION(blsp_uim3_b),
FUNCTION(blsp_uim7_a),
FUNCTION(blsp_uim7_b),
FUNCTION(blsp_uim8_a),
FUNCTION(blsp_uim8_b),
FUNCTION(blsp_uim9_a),
FUNCTION(blsp_uim9_b),
FUNCTION(bt_reset),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1_a),
FUNCTION(gcc_gp1_b),
FUNCTION(gcc_gp2_a),
FUNCTION(gcc_gp2_b),
FUNCTION(gcc_gp3_a),
FUNCTION(gcc_gp3_b),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc),
FUNCTION(hdmi_hot),
FUNCTION(hdmi_rcv),
FUNCTION(isense_dbg),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_slimbus),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mdp_vsync_a),
FUNCTION(mdp_vsync_b),
FUNCTION(modem_tsync),
FUNCTION(mss_lte),
FUNCTION(nav_dr),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(phase_flag),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto),
FUNCTION(pwr_modem),
FUNCTION(pwr_nav),
FUNCTION(qdss_cti0_a),
FUNCTION(qdss_cti0_b),
FUNCTION(qdss_cti1_a),
FUNCTION(qdss_cti1_b),
FUNCTION(qdss),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qua_mi2s),
FUNCTION(sd_card),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(sp_cmu),
FUNCTION(spkr_i2s),
FUNCTION(ssbi1),
FUNCTION(ssc_irq),
FUNCTION(ter_mi2s),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif0),
FUNCTION(tsif1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_clkout),
FUNCTION(vsense_data0),
FUNCTION(vsense_data1),
FUNCTION(vsense_mode),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction msm8998_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_gpsadc0),
MSM_PIN_FUNCTION(atest_gpsadc1),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp10_spi),
MSM_PIN_FUNCTION(blsp10_spi_a),
MSM_PIN_FUNCTION(blsp10_spi_b),
MSM_PIN_FUNCTION(blsp11_i2c),
MSM_PIN_FUNCTION(blsp1_spi),
MSM_PIN_FUNCTION(blsp1_spi_a),
MSM_PIN_FUNCTION(blsp1_spi_b),
MSM_PIN_FUNCTION(blsp2_spi),
MSM_PIN_FUNCTION(blsp9_spi),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_uart1_a),
MSM_PIN_FUNCTION(blsp_uart1_b),
MSM_PIN_FUNCTION(blsp_uart2_a),
MSM_PIN_FUNCTION(blsp_uart2_b),
MSM_PIN_FUNCTION(blsp_uart3_a),
MSM_PIN_FUNCTION(blsp_uart3_b),
MSM_PIN_FUNCTION(blsp_uart7_a),
MSM_PIN_FUNCTION(blsp_uart7_b),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart8_a),
MSM_PIN_FUNCTION(blsp_uart8_b),
MSM_PIN_FUNCTION(blsp_uart9_a),
MSM_PIN_FUNCTION(blsp_uart9_b),
MSM_PIN_FUNCTION(blsp_uim1_a),
MSM_PIN_FUNCTION(blsp_uim1_b),
MSM_PIN_FUNCTION(blsp_uim2_a),
MSM_PIN_FUNCTION(blsp_uim2_b),
MSM_PIN_FUNCTION(blsp_uim3_a),
MSM_PIN_FUNCTION(blsp_uim3_b),
MSM_PIN_FUNCTION(blsp_uim7_a),
MSM_PIN_FUNCTION(blsp_uim7_b),
MSM_PIN_FUNCTION(blsp_uim8_a),
MSM_PIN_FUNCTION(blsp_uim8_b),
MSM_PIN_FUNCTION(blsp_uim9_a),
MSM_PIN_FUNCTION(blsp_uim9_b),
MSM_PIN_FUNCTION(bt_reset),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1_a),
MSM_PIN_FUNCTION(gcc_gp1_b),
MSM_PIN_FUNCTION(gcc_gp2_a),
MSM_PIN_FUNCTION(gcc_gp2_b),
MSM_PIN_FUNCTION(gcc_gp3_a),
MSM_PIN_FUNCTION(gcc_gp3_b),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_hot),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(isense_dbg),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mdp_vsync_a),
MSM_PIN_FUNCTION(mdp_vsync_b),
MSM_PIN_FUNCTION(modem_tsync),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_dr),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto),
MSM_PIN_FUNCTION(pwr_modem),
MSM_PIN_FUNCTION(pwr_nav),
MSM_PIN_FUNCTION(qdss_cti0_a),
MSM_PIN_FUNCTION(qdss_cti0_b),
MSM_PIN_FUNCTION(qdss_cti1_a),
MSM_PIN_FUNCTION(qdss_cti1_b),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(sd_card),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ssbi1),
MSM_PIN_FUNCTION(ssc_irq),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif0),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_clkout),
MSM_PIN_FUNCTION(vsense_data0),
MSM_PIN_FUNCTION(vsense_data1),
MSM_PIN_FUNCTION(vsense_mode),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
static const struct msm_pingroup msm8998_groups[] = {

474
drivers/pinctrl/qcom/pinctrl-msm8x74.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -325,27 +324,20 @@ static const unsigned int sdc2_data_pins[] = { 151 };
static const unsigned int hsic_strobe_pins[] = { 152 };
static const unsigned int hsic_data_pins[] = { 153 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7 \
msm_mux_gpio, \
msm_mux_##f1, \
msm_mux_##f2, \
msm_mux_##f3, \
msm_mux_##f4, \
msm_mux_##f5, \
msm_mux_##f6, \
msm_mux_##f7 \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
@ -371,9 +363,9 @@ static const unsigned int hsic_data_pins[] = { 153 };
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -397,12 +389,12 @@ static const unsigned int hsic_data_pins[] = { 153 };
#define HSIC_PINGROUP(pg_name, ctl) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_hsic_ctl, \
msm_mux_gpio, \
msm_mux_hsic_ctl, \
}, \
.nfuncs = 2, \
.ctl_reg = ctl, \
@ -431,113 +423,113 @@ static const unsigned int hsic_data_pins[] = { 153 };
* the pingroup table below.
*/
enum msm8x74_functions {
MSM_MUX_gpio,
MSM_MUX_cci_i2c0,
MSM_MUX_cci_i2c1,
MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
MSM_MUX_blsp_i2c3,
MSM_MUX_blsp_i2c4,
MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_i2c6,
MSM_MUX_blsp_i2c7,
MSM_MUX_blsp_i2c8,
MSM_MUX_blsp_i2c9,
MSM_MUX_blsp_i2c10,
MSM_MUX_blsp_i2c11,
MSM_MUX_blsp_i2c12,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi1_cs1,
MSM_MUX_blsp_spi1_cs2,
MSM_MUX_blsp_spi1_cs3,
MSM_MUX_blsp_spi2,
MSM_MUX_blsp_spi2_cs1,
MSM_MUX_blsp_spi2_cs2,
MSM_MUX_blsp_spi2_cs3,
MSM_MUX_blsp_spi3,
MSM_MUX_blsp_spi4,
MSM_MUX_blsp_spi5,
MSM_MUX_blsp_spi6,
MSM_MUX_blsp_spi7,
MSM_MUX_blsp_spi8,
MSM_MUX_blsp_spi9,
MSM_MUX_blsp_spi10,
MSM_MUX_blsp_spi10_cs1,
MSM_MUX_blsp_spi10_cs2,
MSM_MUX_blsp_spi10_cs3,
MSM_MUX_blsp_spi11,
MSM_MUX_blsp_spi12,
MSM_MUX_blsp_uart1,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart3,
MSM_MUX_blsp_uart4,
MSM_MUX_blsp_uart5,
MSM_MUX_blsp_uart6,
MSM_MUX_blsp_uart7,
MSM_MUX_blsp_uart8,
MSM_MUX_blsp_uart9,
MSM_MUX_blsp_uart10,
MSM_MUX_blsp_uart11,
MSM_MUX_blsp_uart12,
MSM_MUX_blsp_uim1,
MSM_MUX_blsp_uim2,
MSM_MUX_blsp_uim3,
MSM_MUX_blsp_uim4,
MSM_MUX_blsp_uim5,
MSM_MUX_blsp_uim6,
MSM_MUX_blsp_uim7,
MSM_MUX_blsp_uim8,
MSM_MUX_blsp_uim9,
MSM_MUX_blsp_uim10,
MSM_MUX_blsp_uim11,
MSM_MUX_blsp_uim12,
MSM_MUX_uim1,
MSM_MUX_uim2,
MSM_MUX_uim_batt_alarm,
MSM_MUX_sdc3,
MSM_MUX_sdc4,
MSM_MUX_gcc_gp_clk1,
MSM_MUX_gcc_gp_clk2,
MSM_MUX_gcc_gp_clk3,
MSM_MUX_qua_mi2s,
MSM_MUX_pri_mi2s,
MSM_MUX_spkr_mi2s,
MSM_MUX_ter_mi2s,
MSM_MUX_sec_mi2s,
MSM_MUX_hdmi_cec,
MSM_MUX_hdmi_ddc,
MSM_MUX_hdmi_hpd,
MSM_MUX_edp_hpd,
MSM_MUX_mdp_vsync,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_cam_mclk2,
MSM_MUX_cam_mclk3,
MSM_MUX_cci_timer0,
MSM_MUX_cci_timer1,
MSM_MUX_cci_timer2,
MSM_MUX_cci_timer3,
MSM_MUX_cci_timer4,
MSM_MUX_cci_async_in0,
MSM_MUX_cci_async_in1,
MSM_MUX_cci_async_in2,
MSM_MUX_gp_pdm0,
MSM_MUX_gp_pdm1,
MSM_MUX_gp_pdm2,
MSM_MUX_gp0_clk,
MSM_MUX_gp1_clk,
MSM_MUX_gp_mn,
MSM_MUX_tsif1,
MSM_MUX_tsif2,
MSM_MUX_hsic,
MSM_MUX_grfc,
MSM_MUX_audio_ref_clk,
MSM_MUX_bt,
MSM_MUX_fm,
MSM_MUX_wlan,
MSM_MUX_slimbus,
MSM_MUX_hsic_ctl,
MSM_MUX_NA,
msm_mux_gpio,
msm_mux_cci_i2c0,
msm_mux_cci_i2c1,
msm_mux_blsp_i2c1,
msm_mux_blsp_i2c2,
msm_mux_blsp_i2c3,
msm_mux_blsp_i2c4,
msm_mux_blsp_i2c5,
msm_mux_blsp_i2c6,
msm_mux_blsp_i2c7,
msm_mux_blsp_i2c8,
msm_mux_blsp_i2c9,
msm_mux_blsp_i2c10,
msm_mux_blsp_i2c11,
msm_mux_blsp_i2c12,
msm_mux_blsp_spi1,
msm_mux_blsp_spi1_cs1,
msm_mux_blsp_spi1_cs2,
msm_mux_blsp_spi1_cs3,
msm_mux_blsp_spi2,
msm_mux_blsp_spi2_cs1,
msm_mux_blsp_spi2_cs2,
msm_mux_blsp_spi2_cs3,
msm_mux_blsp_spi3,
msm_mux_blsp_spi4,
msm_mux_blsp_spi5,
msm_mux_blsp_spi6,
msm_mux_blsp_spi7,
msm_mux_blsp_spi8,
msm_mux_blsp_spi9,
msm_mux_blsp_spi10,
msm_mux_blsp_spi10_cs1,
msm_mux_blsp_spi10_cs2,
msm_mux_blsp_spi10_cs3,
msm_mux_blsp_spi11,
msm_mux_blsp_spi12,
msm_mux_blsp_uart1,
msm_mux_blsp_uart2,
msm_mux_blsp_uart3,
msm_mux_blsp_uart4,
msm_mux_blsp_uart5,
msm_mux_blsp_uart6,
msm_mux_blsp_uart7,
msm_mux_blsp_uart8,
msm_mux_blsp_uart9,
msm_mux_blsp_uart10,
msm_mux_blsp_uart11,
msm_mux_blsp_uart12,
msm_mux_blsp_uim1,
msm_mux_blsp_uim2,
msm_mux_blsp_uim3,
msm_mux_blsp_uim4,
msm_mux_blsp_uim5,
msm_mux_blsp_uim6,
msm_mux_blsp_uim7,
msm_mux_blsp_uim8,
msm_mux_blsp_uim9,
msm_mux_blsp_uim10,
msm_mux_blsp_uim11,
msm_mux_blsp_uim12,
msm_mux_uim1,
msm_mux_uim2,
msm_mux_uim_batt_alarm,
msm_mux_sdc3,
msm_mux_sdc4,
msm_mux_gcc_gp_clk1,
msm_mux_gcc_gp_clk2,
msm_mux_gcc_gp_clk3,
msm_mux_qua_mi2s,
msm_mux_pri_mi2s,
msm_mux_spkr_mi2s,
msm_mux_ter_mi2s,
msm_mux_sec_mi2s,
msm_mux_hdmi_cec,
msm_mux_hdmi_ddc,
msm_mux_hdmi_hpd,
msm_mux_edp_hpd,
msm_mux_mdp_vsync,
msm_mux_cam_mclk0,
msm_mux_cam_mclk1,
msm_mux_cam_mclk2,
msm_mux_cam_mclk3,
msm_mux_cci_timer0,
msm_mux_cci_timer1,
msm_mux_cci_timer2,
msm_mux_cci_timer3,
msm_mux_cci_timer4,
msm_mux_cci_async_in0,
msm_mux_cci_async_in1,
msm_mux_cci_async_in2,
msm_mux_gp_pdm0,
msm_mux_gp_pdm1,
msm_mux_gp_pdm2,
msm_mux_gp0_clk,
msm_mux_gp1_clk,
msm_mux_gp_mn,
msm_mux_tsif1,
msm_mux_tsif2,
msm_mux_hsic,
msm_mux_grfc,
msm_mux_audio_ref_clk,
msm_mux_bt,
msm_mux_fm,
msm_mux_wlan,
msm_mux_slimbus,
msm_mux_hsic_ctl,
msm_mux_NA,
};
static const char * const gpio_groups[] = {
@ -785,113 +777,113 @@ static const char * const wlan_groups[] = {
static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" };
static const struct msm_function msm8x74_functions[] = {
FUNCTION(gpio),
FUNCTION(cci_i2c0),
FUNCTION(cci_i2c1),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim_batt_alarm),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim4),
FUNCTION(blsp_uim5),
FUNCTION(blsp_uim6),
FUNCTION(blsp_uim7),
FUNCTION(blsp_uim8),
FUNCTION(blsp_uim9),
FUNCTION(blsp_uim10),
FUNCTION(blsp_uim11),
FUNCTION(blsp_uim12),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8),
FUNCTION(blsp_i2c9),
FUNCTION(blsp_i2c10),
FUNCTION(blsp_i2c11),
FUNCTION(blsp_i2c12),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi1_cs1),
FUNCTION(blsp_spi1_cs2),
FUNCTION(blsp_spi1_cs3),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi2_cs1),
FUNCTION(blsp_spi2_cs2),
FUNCTION(blsp_spi2_cs3),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8),
FUNCTION(blsp_spi9),
FUNCTION(blsp_spi10),
FUNCTION(blsp_spi10_cs1),
FUNCTION(blsp_spi10_cs2),
FUNCTION(blsp_spi10_cs3),
FUNCTION(blsp_spi11),
FUNCTION(blsp_spi12),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6),
FUNCTION(blsp_uart7),
FUNCTION(blsp_uart8),
FUNCTION(blsp_uart9),
FUNCTION(blsp_uart10),
FUNCTION(blsp_uart11),
FUNCTION(blsp_uart12),
FUNCTION(sdc3),
FUNCTION(sdc4),
FUNCTION(gcc_gp_clk1),
FUNCTION(gcc_gp_clk2),
FUNCTION(gcc_gp_clk3),
FUNCTION(qua_mi2s),
FUNCTION(pri_mi2s),
FUNCTION(spkr_mi2s),
FUNCTION(ter_mi2s),
FUNCTION(sec_mi2s),
FUNCTION(mdp_vsync),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cam_mclk2),
FUNCTION(cam_mclk3),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cci_async_in0),
FUNCTION(cci_async_in1),
FUNCTION(cci_async_in2),
FUNCTION(hdmi_cec),
FUNCTION(hdmi_ddc),
FUNCTION(hdmi_hpd),
FUNCTION(edp_hpd),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gp0_clk),
FUNCTION(gp1_clk),
FUNCTION(gp_mn),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(hsic),
FUNCTION(grfc),
FUNCTION(audio_ref_clk),
FUNCTION(bt),
FUNCTION(fm),
FUNCTION(wlan),
FUNCTION(slimbus),
FUNCTION(hsic_ctl),
static const struct pinfunction msm8x74_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(cci_i2c0),
MSM_PIN_FUNCTION(cci_i2c1),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim_batt_alarm),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim3),
MSM_PIN_FUNCTION(blsp_uim4),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(blsp_uim7),
MSM_PIN_FUNCTION(blsp_uim8),
MSM_PIN_FUNCTION(blsp_uim9),
MSM_PIN_FUNCTION(blsp_uim10),
MSM_PIN_FUNCTION(blsp_uim11),
MSM_PIN_FUNCTION(blsp_uim12),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8),
MSM_PIN_FUNCTION(blsp_i2c9),
MSM_PIN_FUNCTION(blsp_i2c10),
MSM_PIN_FUNCTION(blsp_i2c11),
MSM_PIN_FUNCTION(blsp_i2c12),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi1_cs1),
MSM_PIN_FUNCTION(blsp_spi1_cs2),
MSM_PIN_FUNCTION(blsp_spi1_cs3),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi2_cs1),
MSM_PIN_FUNCTION(blsp_spi2_cs2),
MSM_PIN_FUNCTION(blsp_spi2_cs3),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8),
MSM_PIN_FUNCTION(blsp_spi9),
MSM_PIN_FUNCTION(blsp_spi10),
MSM_PIN_FUNCTION(blsp_spi10_cs1),
MSM_PIN_FUNCTION(blsp_spi10_cs2),
MSM_PIN_FUNCTION(blsp_spi10_cs3),
MSM_PIN_FUNCTION(blsp_spi11),
MSM_PIN_FUNCTION(blsp_spi12),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6),
MSM_PIN_FUNCTION(blsp_uart7),
MSM_PIN_FUNCTION(blsp_uart8),
MSM_PIN_FUNCTION(blsp_uart9),
MSM_PIN_FUNCTION(blsp_uart10),
MSM_PIN_FUNCTION(blsp_uart11),
MSM_PIN_FUNCTION(blsp_uart12),
MSM_PIN_FUNCTION(sdc3),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(gcc_gp_clk1),
MSM_PIN_FUNCTION(gcc_gp_clk2),
MSM_PIN_FUNCTION(gcc_gp_clk3),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(spkr_mi2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(cam_mclk3),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cci_async_in0),
MSM_PIN_FUNCTION(cci_async_in1),
MSM_PIN_FUNCTION(cci_async_in2),
MSM_PIN_FUNCTION(hdmi_cec),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(hdmi_hpd),
MSM_PIN_FUNCTION(edp_hpd),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gp0_clk),
MSM_PIN_FUNCTION(gp1_clk),
MSM_PIN_FUNCTION(gp_mn),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(hsic),
MSM_PIN_FUNCTION(grfc),
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(bt),
MSM_PIN_FUNCTION(fm),
MSM_PIN_FUNCTION(wlan),
MSM_PIN_FUNCTION(slimbus),
MSM_PIN_FUNCTION(hsic_ctl),
};
static const struct msm_pingroup msm8x74_groups[] = {

230
drivers/pinctrl/qcom/pinctrl-qcm2290.c
View File

@ -6,24 +6,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -85,9 +77,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -837,108 +829,108 @@ static const char * const pwm_9_groups[] = {
"gpio115",
};
static const struct msm_function qcm2290_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(char_exec),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dac_calib),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gsm0_tx),
FUNCTION(gsm1_tx),
FUNCTION(jitter_bist),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync_out_0),
FUNCTION(mdp_vsync_out_1),
FUNCTION(mpm_pwr),
FUNCTION(mss_lte),
FUNCTION(m_voc),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pbs0),
FUNCTION(pbs1),
FUNCTION(pbs2),
FUNCTION(pbs3),
FUNCTION(pbs4),
FUNCTION(pbs5),
FUNCTION(pbs6),
FUNCTION(pbs7),
FUNCTION(pbs8),
FUNCTION(pbs9),
FUNCTION(pbs10),
FUNCTION(pbs11),
FUNCTION(pbs12),
FUNCTION(pbs13),
FUNCTION(pbs14),
FUNCTION(pbs15),
FUNCTION(pbs_out),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(prng_rosc),
FUNCTION(pwm_0),
FUNCTION(pwm_1),
FUNCTION(pwm_2),
FUNCTION(pwm_3),
FUNCTION(pwm_4),
FUNCTION(pwm_5),
FUNCTION(pwm_6),
FUNCTION(pwm_7),
FUNCTION(pwm_8),
FUNCTION(pwm_9),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sd_write),
FUNCTION(ssbi_wtr1),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
static const struct pinfunction qcm2290_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(char_exec),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dac_calib),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(gsm1_tx),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync_out_0),
MSM_PIN_FUNCTION(mdp_vsync_out_1),
MSM_PIN_FUNCTION(mpm_pwr),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs0),
MSM_PIN_FUNCTION(pbs1),
MSM_PIN_FUNCTION(pbs2),
MSM_PIN_FUNCTION(pbs3),
MSM_PIN_FUNCTION(pbs4),
MSM_PIN_FUNCTION(pbs5),
MSM_PIN_FUNCTION(pbs6),
MSM_PIN_FUNCTION(pbs7),
MSM_PIN_FUNCTION(pbs8),
MSM_PIN_FUNCTION(pbs9),
MSM_PIN_FUNCTION(pbs10),
MSM_PIN_FUNCTION(pbs11),
MSM_PIN_FUNCTION(pbs12),
MSM_PIN_FUNCTION(pbs13),
MSM_PIN_FUNCTION(pbs14),
MSM_PIN_FUNCTION(pbs15),
MSM_PIN_FUNCTION(pbs_out),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwm_0),
MSM_PIN_FUNCTION(pwm_1),
MSM_PIN_FUNCTION(pwm_2),
MSM_PIN_FUNCTION(pwm_3),
MSM_PIN_FUNCTION(pwm_4),
MSM_PIN_FUNCTION(pwm_5),
MSM_PIN_FUNCTION(pwm_6),
MSM_PIN_FUNCTION(pwm_7),
MSM_PIN_FUNCTION(pwm_8),
MSM_PIN_FUNCTION(pwm_9),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(ssbi_wtr1),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

388
drivers/pinctrl/qcom/pinctrl-qcs404.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -22,18 +21,11 @@ enum {
EAST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -71,9 +63,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -1303,190 +1295,190 @@ static const char * const i2s_3_ws_a_groups[] = {
"gpio105",
};
static const struct msm_function qcs404_functions[] = {
FUNCTION(gpio),
FUNCTION(hdmi_tx),
FUNCTION(hdmi_ddc),
FUNCTION(blsp_uart_tx_a2),
FUNCTION(blsp_spi2),
FUNCTION(m_voc),
FUNCTION(qdss_cti_trig_in_a0),
FUNCTION(blsp_uart_rx_a2),
FUNCTION(qdss_tracectl_a),
FUNCTION(blsp_uart2),
FUNCTION(aud_cdc),
FUNCTION(blsp_i2c_sda_a2),
FUNCTION(qdss_tracedata_a),
FUNCTION(blsp_i2c_scl_a2),
FUNCTION(qdss_tracectl_b),
FUNCTION(qdss_cti_trig_in_b0),
FUNCTION(blsp_uart1),
FUNCTION(blsp_spi_mosi_a1),
FUNCTION(blsp_spi_miso_a1),
FUNCTION(qdss_tracedata_b),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_spi_cs_n_a1),
FUNCTION(gcc_plltest),
FUNCTION(blsp_spi_clk_a1),
FUNCTION(rgb_data0),
FUNCTION(blsp_uart5),
FUNCTION(blsp_spi5),
FUNCTION(adsp_ext),
FUNCTION(rgb_data1),
FUNCTION(prng_rosc),
FUNCTION(rgb_data2),
FUNCTION(blsp_i2c5),
FUNCTION(gcc_gp1_clk_b),
FUNCTION(rgb_data3),
FUNCTION(gcc_gp2_clk_b),
FUNCTION(blsp_spi0),
FUNCTION(blsp_uart0),
FUNCTION(gcc_gp3_clk_b),
FUNCTION(blsp_i2c0),
FUNCTION(qdss_traceclk_b),
FUNCTION(pcie_clk),
FUNCTION(nfc_irq),
FUNCTION(blsp_spi4),
FUNCTION(nfc_dwl),
FUNCTION(audio_ts),
FUNCTION(rgb_data4),
FUNCTION(spi_lcd),
FUNCTION(blsp_uart_tx_b2),
FUNCTION(gcc_gp3_clk_a),
FUNCTION(rgb_data5),
FUNCTION(blsp_uart_rx_b2),
FUNCTION(blsp_i2c_sda_b2),
FUNCTION(blsp_i2c_scl_b2),
FUNCTION(pwm_led11),
FUNCTION(i2s_3_data0_a),
FUNCTION(ebi2_lcd),
FUNCTION(i2s_3_data1_a),
FUNCTION(i2s_3_data2_a),
FUNCTION(atest_char),
FUNCTION(pwm_led3),
FUNCTION(i2s_3_data3_a),
FUNCTION(pwm_led4),
FUNCTION(i2s_4),
FUNCTION(ebi2_a),
FUNCTION(dsd_clk_b),
FUNCTION(pwm_led5),
FUNCTION(pwm_led6),
FUNCTION(pwm_led7),
FUNCTION(pwm_led8),
FUNCTION(pwm_led24),
FUNCTION(spkr_dac0),
FUNCTION(blsp_i2c4),
FUNCTION(pwm_led9),
FUNCTION(pwm_led10),
FUNCTION(spdifrx_opt),
FUNCTION(pwm_led12),
FUNCTION(pwm_led13),
FUNCTION(pwm_led14),
FUNCTION(wlan1_adc1),
FUNCTION(rgb_data_b0),
FUNCTION(pwm_led15),
FUNCTION(blsp_spi_mosi_b1),
FUNCTION(wlan1_adc0),
FUNCTION(rgb_data_b1),
FUNCTION(pwm_led16),
FUNCTION(blsp_spi_miso_b1),
FUNCTION(qdss_cti_trig_out_b0),
FUNCTION(wlan2_adc1),
FUNCTION(rgb_data_b2),
FUNCTION(pwm_led17),
FUNCTION(blsp_spi_cs_n_b1),
FUNCTION(wlan2_adc0),
FUNCTION(rgb_data_b3),
FUNCTION(pwm_led18),
FUNCTION(blsp_spi_clk_b1),
FUNCTION(rgb_data_b4),
FUNCTION(pwm_led19),
FUNCTION(ext_mclk1_b),
FUNCTION(qdss_traceclk_a),
FUNCTION(rgb_data_b5),
FUNCTION(pwm_led20),
FUNCTION(atest_char3),
FUNCTION(i2s_3_sck_b),
FUNCTION(ldo_update),
FUNCTION(bimc_dte0),
FUNCTION(rgb_hsync),
FUNCTION(pwm_led21),
FUNCTION(i2s_3_ws_b),
FUNCTION(dbg_out),
FUNCTION(rgb_vsync),
FUNCTION(i2s_3_data0_b),
FUNCTION(ldo_en),
FUNCTION(hdmi_dtest),
FUNCTION(rgb_de),
FUNCTION(i2s_3_data1_b),
FUNCTION(hdmi_lbk9),
FUNCTION(rgb_clk),
FUNCTION(atest_char1),
FUNCTION(i2s_3_data2_b),
FUNCTION(ebi_cdc),
FUNCTION(hdmi_lbk8),
FUNCTION(rgb_mdp),
FUNCTION(atest_char0),
FUNCTION(i2s_3_data3_b),
FUNCTION(hdmi_lbk7),
FUNCTION(rgb_data_b6),
FUNCTION(rgb_data_b7),
FUNCTION(hdmi_lbk6),
FUNCTION(rgmii_int),
FUNCTION(cri_trng1),
FUNCTION(rgmii_wol),
FUNCTION(cri_trng0),
FUNCTION(gcc_tlmm),
FUNCTION(rgmii_ck),
FUNCTION(rgmii_tx),
FUNCTION(hdmi_lbk5),
FUNCTION(hdmi_pixel),
FUNCTION(hdmi_rcv),
FUNCTION(hdmi_lbk4),
FUNCTION(rgmii_ctl),
FUNCTION(ext_lpass),
FUNCTION(rgmii_rx),
FUNCTION(cri_trng),
FUNCTION(hdmi_lbk3),
FUNCTION(hdmi_lbk2),
FUNCTION(qdss_cti_trig_out_b1),
FUNCTION(rgmii_mdio),
FUNCTION(hdmi_lbk1),
FUNCTION(rgmii_mdc),
FUNCTION(hdmi_lbk0),
FUNCTION(ir_in),
FUNCTION(wsa_en),
FUNCTION(rgb_data6),
FUNCTION(rgb_data7),
FUNCTION(atest_char2),
FUNCTION(ebi_ch0),
FUNCTION(blsp_uart3),
FUNCTION(blsp_spi3),
FUNCTION(sd_write),
FUNCTION(blsp_i2c3),
FUNCTION(gcc_gp1_clk_a),
FUNCTION(qdss_cti_trig_in_b1),
FUNCTION(gcc_gp2_clk_a),
FUNCTION(ext_mclk0),
FUNCTION(mclk_in1),
FUNCTION(i2s_1),
FUNCTION(dsd_clk_a),
FUNCTION(qdss_cti_trig_in_a1),
FUNCTION(rgmi_dll1),
FUNCTION(pwm_led22),
FUNCTION(pwm_led23),
FUNCTION(qdss_cti_trig_out_a0),
FUNCTION(rgmi_dll2),
FUNCTION(pwm_led1),
FUNCTION(qdss_cti_trig_out_a1),
FUNCTION(pwm_led2),
FUNCTION(i2s_2),
FUNCTION(pll_bist),
FUNCTION(ext_mclk1_a),
FUNCTION(mclk_in2),
FUNCTION(bimc_dte1),
FUNCTION(i2s_3_sck_a),
FUNCTION(i2s_3_ws_a),
static const struct pinfunction qcs404_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(hdmi_tx),
MSM_PIN_FUNCTION(hdmi_ddc),
MSM_PIN_FUNCTION(blsp_uart_tx_a2),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
MSM_PIN_FUNCTION(blsp_uart_rx_a2),
MSM_PIN_FUNCTION(qdss_tracectl_a),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(aud_cdc),
MSM_PIN_FUNCTION(blsp_i2c_sda_a2),
MSM_PIN_FUNCTION(qdss_tracedata_a),
MSM_PIN_FUNCTION(blsp_i2c_scl_a2),
MSM_PIN_FUNCTION(qdss_tracectl_b),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_spi_mosi_a1),
MSM_PIN_FUNCTION(blsp_spi_miso_a1),
MSM_PIN_FUNCTION(qdss_tracedata_b),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_spi_cs_n_a1),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(blsp_spi_clk_a1),
MSM_PIN_FUNCTION(rgb_data0),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(rgb_data1),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(rgb_data2),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(gcc_gp1_clk_b),
MSM_PIN_FUNCTION(rgb_data3),
MSM_PIN_FUNCTION(gcc_gp2_clk_b),
MSM_PIN_FUNCTION(blsp_spi0),
MSM_PIN_FUNCTION(blsp_uart0),
MSM_PIN_FUNCTION(gcc_gp3_clk_b),
MSM_PIN_FUNCTION(blsp_i2c0),
MSM_PIN_FUNCTION(qdss_traceclk_b),
MSM_PIN_FUNCTION(pcie_clk),
MSM_PIN_FUNCTION(nfc_irq),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(nfc_dwl),
MSM_PIN_FUNCTION(audio_ts),
MSM_PIN_FUNCTION(rgb_data4),
MSM_PIN_FUNCTION(spi_lcd),
MSM_PIN_FUNCTION(blsp_uart_tx_b2),
MSM_PIN_FUNCTION(gcc_gp3_clk_a),
MSM_PIN_FUNCTION(rgb_data5),
MSM_PIN_FUNCTION(blsp_uart_rx_b2),
MSM_PIN_FUNCTION(blsp_i2c_sda_b2),
MSM_PIN_FUNCTION(blsp_i2c_scl_b2),
MSM_PIN_FUNCTION(pwm_led11),
MSM_PIN_FUNCTION(i2s_3_data0_a),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(i2s_3_data1_a),
MSM_PIN_FUNCTION(i2s_3_data2_a),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(pwm_led3),
MSM_PIN_FUNCTION(i2s_3_data3_a),
MSM_PIN_FUNCTION(pwm_led4),
MSM_PIN_FUNCTION(i2s_4),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(dsd_clk_b),
MSM_PIN_FUNCTION(pwm_led5),
MSM_PIN_FUNCTION(pwm_led6),
MSM_PIN_FUNCTION(pwm_led7),
MSM_PIN_FUNCTION(pwm_led8),
MSM_PIN_FUNCTION(pwm_led24),
MSM_PIN_FUNCTION(spkr_dac0),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(pwm_led9),
MSM_PIN_FUNCTION(pwm_led10),
MSM_PIN_FUNCTION(spdifrx_opt),
MSM_PIN_FUNCTION(pwm_led12),
MSM_PIN_FUNCTION(pwm_led13),
MSM_PIN_FUNCTION(pwm_led14),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(rgb_data_b0),
MSM_PIN_FUNCTION(pwm_led15),
MSM_PIN_FUNCTION(blsp_spi_mosi_b1),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(rgb_data_b1),
MSM_PIN_FUNCTION(pwm_led16),
MSM_PIN_FUNCTION(blsp_spi_miso_b1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
MSM_PIN_FUNCTION(wlan2_adc1),
MSM_PIN_FUNCTION(rgb_data_b2),
MSM_PIN_FUNCTION(pwm_led17),
MSM_PIN_FUNCTION(blsp_spi_cs_n_b1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(rgb_data_b3),
MSM_PIN_FUNCTION(pwm_led18),
MSM_PIN_FUNCTION(blsp_spi_clk_b1),
MSM_PIN_FUNCTION(rgb_data_b4),
MSM_PIN_FUNCTION(pwm_led19),
MSM_PIN_FUNCTION(ext_mclk1_b),
MSM_PIN_FUNCTION(qdss_traceclk_a),
MSM_PIN_FUNCTION(rgb_data_b5),
MSM_PIN_FUNCTION(pwm_led20),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(i2s_3_sck_b),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(rgb_hsync),
MSM_PIN_FUNCTION(pwm_led21),
MSM_PIN_FUNCTION(i2s_3_ws_b),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(rgb_vsync),
MSM_PIN_FUNCTION(i2s_3_data0_b),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(hdmi_dtest),
MSM_PIN_FUNCTION(rgb_de),
MSM_PIN_FUNCTION(i2s_3_data1_b),
MSM_PIN_FUNCTION(hdmi_lbk9),
MSM_PIN_FUNCTION(rgb_clk),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(i2s_3_data2_b),
MSM_PIN_FUNCTION(ebi_cdc),
MSM_PIN_FUNCTION(hdmi_lbk8),
MSM_PIN_FUNCTION(rgb_mdp),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(i2s_3_data3_b),
MSM_PIN_FUNCTION(hdmi_lbk7),
MSM_PIN_FUNCTION(rgb_data_b6),
MSM_PIN_FUNCTION(rgb_data_b7),
MSM_PIN_FUNCTION(hdmi_lbk6),
MSM_PIN_FUNCTION(rgmii_int),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(rgmii_wol),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(gcc_tlmm),
MSM_PIN_FUNCTION(rgmii_ck),
MSM_PIN_FUNCTION(rgmii_tx),
MSM_PIN_FUNCTION(hdmi_lbk5),
MSM_PIN_FUNCTION(hdmi_pixel),
MSM_PIN_FUNCTION(hdmi_rcv),
MSM_PIN_FUNCTION(hdmi_lbk4),
MSM_PIN_FUNCTION(rgmii_ctl),
MSM_PIN_FUNCTION(ext_lpass),
MSM_PIN_FUNCTION(rgmii_rx),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(hdmi_lbk3),
MSM_PIN_FUNCTION(hdmi_lbk2),
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
MSM_PIN_FUNCTION(rgmii_mdio),
MSM_PIN_FUNCTION(hdmi_lbk1),
MSM_PIN_FUNCTION(rgmii_mdc),
MSM_PIN_FUNCTION(hdmi_lbk0),
MSM_PIN_FUNCTION(ir_in),
MSM_PIN_FUNCTION(wsa_en),
MSM_PIN_FUNCTION(rgb_data6),
MSM_PIN_FUNCTION(rgb_data7),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(ebi_ch0),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(gcc_gp1_clk_a),
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
MSM_PIN_FUNCTION(gcc_gp2_clk_a),
MSM_PIN_FUNCTION(ext_mclk0),
MSM_PIN_FUNCTION(mclk_in1),
MSM_PIN_FUNCTION(i2s_1),
MSM_PIN_FUNCTION(dsd_clk_a),
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
MSM_PIN_FUNCTION(rgmi_dll1),
MSM_PIN_FUNCTION(pwm_led22),
MSM_PIN_FUNCTION(pwm_led23),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
MSM_PIN_FUNCTION(rgmi_dll2),
MSM_PIN_FUNCTION(pwm_led1),
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
MSM_PIN_FUNCTION(pwm_led2),
MSM_PIN_FUNCTION(i2s_2),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(ext_mclk1_a),
MSM_PIN_FUNCTION(mclk_in2),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(i2s_3_sck_a),
MSM_PIN_FUNCTION(i2s_3_ws_a),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

8
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
View File

@ -90,17 +90,17 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
*/
for (i = 0; i < num_gpios; i++) {
pins[i].number = i;
groups[i].pins = &pins[i].number;
groups[i].grp.pins = &pins[i].number;
}
/* Populate the entries that are meant to be exposed as GPIOs. */
for (i = 0; i < avail_gpios; i++) {
unsigned int gpio = gpios[i];
groups[gpio].npins = 1;
groups[gpio].grp.npins = 1;
snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
pins[gpio].name = names[i];
groups[gpio].name = names[i];
groups[gpio].grp.name = names[i];
groups[gpio].ctl_reg = 0x10000 * gpio;
groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
@ -142,7 +142,7 @@ MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
static struct platform_driver qdf2xxx_pinctrl_driver = {
.driver = {
.name = "qdf2xxx-pinctrl",
.acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
.acpi_match_table = qdf2xxx_acpi_ids,
},
.probe = qdf2xxx_pinctrl_probe,
.remove = msm_pinctrl_remove,

249
drivers/pinctrl/qcom/pinctrl-qdu1000.c
View File

@ -7,24 +7,17 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -61,9 +54,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = REG_BASE + ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -86,9 +79,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -910,117 +903,117 @@ static const char * const vsense_trigger_groups[] = {
"gpio135",
};
static const struct msm_function qdu1000_functions[] = {
FUNCTION(gpio),
FUNCTION(cmo_pri),
FUNCTION(si5518_int),
FUNCTION(atest_char),
FUNCTION(atest_usb),
FUNCTION(char_exec),
FUNCTION(cmu_rng),
FUNCTION(dbg_out_clk),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(ddr_pxi4),
FUNCTION(ddr_pxi5),
FUNCTION(ddr_pxi6),
FUNCTION(ddr_pxi7),
FUNCTION(eth012_int_n),
FUNCTION(eth345_int_n),
FUNCTION(eth6_int_n),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gps_pps_in),
FUNCTION(hardsync_pps_in),
FUNCTION(intr_c),
FUNCTION(jitter_bist_ref),
FUNCTION(pcie_clkreqn),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_clk),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qlink2_enable),
FUNCTION(qlink2_request),
FUNCTION(qlink2_wmss),
FUNCTION(qlink3_enable),
FUNCTION(qlink3_request),
FUNCTION(qlink3_wmss),
FUNCTION(qlink4_enable),
FUNCTION(qlink4_request),
FUNCTION(qlink4_wmss),
FUNCTION(qlink5_enable),
FUNCTION(qlink5_request),
FUNCTION(qlink5_wmss),
FUNCTION(qlink6_enable),
FUNCTION(qlink6_request),
FUNCTION(qlink6_wmss),
FUNCTION(qlink7_enable),
FUNCTION(qlink7_request),
FUNCTION(qlink7_wmss),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup03),
FUNCTION(qup04),
FUNCTION(qup05),
FUNCTION(qup06),
FUNCTION(qup07),
FUNCTION(qup08),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup20),
FUNCTION(qup21),
FUNCTION(qup22),
FUNCTION(smb_alert),
FUNCTION(smb_clk),
FUNCTION(smb_dat),
FUNCTION(tb_trig),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tgu_ch4),
FUNCTION(tgu_ch5),
FUNCTION(tgu_ch6),
FUNCTION(tgu_ch7),
FUNCTION(tmess_prng0),
FUNCTION(tmess_prng1),
FUNCTION(tmess_prng2),
FUNCTION(tmess_prng3),
FUNCTION(tod_pps_in),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(usb2phy_ac),
FUNCTION(usb_con_det),
FUNCTION(usb_dfp_en),
FUNCTION(usb_phy),
FUNCTION(vfr_0),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
static const struct pinfunction qdu1000_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(cmo_pri),
MSM_PIN_FUNCTION(si5518_int),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(char_exec),
MSM_PIN_FUNCTION(cmu_rng),
MSM_PIN_FUNCTION(dbg_out_clk),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(ddr_pxi4),
MSM_PIN_FUNCTION(ddr_pxi5),
MSM_PIN_FUNCTION(ddr_pxi6),
MSM_PIN_FUNCTION(ddr_pxi7),
MSM_PIN_FUNCTION(eth012_int_n),
MSM_PIN_FUNCTION(eth345_int_n),
MSM_PIN_FUNCTION(eth6_int_n),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gps_pps_in),
MSM_PIN_FUNCTION(hardsync_pps_in),
MSM_PIN_FUNCTION(intr_c),
MSM_PIN_FUNCTION(jitter_bist_ref),
MSM_PIN_FUNCTION(pcie_clkreqn),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qlink2_enable),
MSM_PIN_FUNCTION(qlink2_request),
MSM_PIN_FUNCTION(qlink2_wmss),
MSM_PIN_FUNCTION(qlink3_enable),
MSM_PIN_FUNCTION(qlink3_request),
MSM_PIN_FUNCTION(qlink3_wmss),
MSM_PIN_FUNCTION(qlink4_enable),
MSM_PIN_FUNCTION(qlink4_request),
MSM_PIN_FUNCTION(qlink4_wmss),
MSM_PIN_FUNCTION(qlink5_enable),
MSM_PIN_FUNCTION(qlink5_request),
MSM_PIN_FUNCTION(qlink5_wmss),
MSM_PIN_FUNCTION(qlink6_enable),
MSM_PIN_FUNCTION(qlink6_request),
MSM_PIN_FUNCTION(qlink6_wmss),
MSM_PIN_FUNCTION(qlink7_enable),
MSM_PIN_FUNCTION(qlink7_request),
MSM_PIN_FUNCTION(qlink7_wmss),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(qup03),
MSM_PIN_FUNCTION(qup04),
MSM_PIN_FUNCTION(qup05),
MSM_PIN_FUNCTION(qup06),
MSM_PIN_FUNCTION(qup07),
MSM_PIN_FUNCTION(qup08),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup20),
MSM_PIN_FUNCTION(qup21),
MSM_PIN_FUNCTION(qup22),
MSM_PIN_FUNCTION(smb_alert),
MSM_PIN_FUNCTION(smb_clk),
MSM_PIN_FUNCTION(smb_dat),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tgu_ch4),
MSM_PIN_FUNCTION(tgu_ch5),
MSM_PIN_FUNCTION(tgu_ch6),
MSM_PIN_FUNCTION(tgu_ch7),
MSM_PIN_FUNCTION(tmess_prng0),
MSM_PIN_FUNCTION(tmess_prng1),
MSM_PIN_FUNCTION(tmess_prng2),
MSM_PIN_FUNCTION(tmess_prng3),
MSM_PIN_FUNCTION(tod_pps_in),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_con_det),
MSM_PIN_FUNCTION(usb_dfp_en),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_0),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
};
/*

327
drivers/pinctrl/qcom/pinctrl-sa8775p.c
View File

@ -7,24 +7,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -63,9 +55,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -88,9 +80,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1179,147 +1171,147 @@ static const char * const vsense_trigger_groups[] = {
"gpio111",
};
static const struct msm_function sa8775p_functions[] = {
FUNCTION(gpio),
FUNCTION(atest_char),
FUNCTION(atest_usb2),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cci_timer5),
FUNCTION(cci_timer6),
FUNCTION(cci_timer7),
FUNCTION(cci_timer8),
FUNCTION(cci_timer9),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(ddr_pxi4),
FUNCTION(ddr_pxi5),
FUNCTION(edp0_hot),
FUNCTION(edp0_lcd),
FUNCTION(edp1_hot),
FUNCTION(edp1_lcd),
FUNCTION(edp2_hot),
FUNCTION(edp2_lcd),
FUNCTION(edp3_hot),
FUNCTION(edp3_lcd),
FUNCTION(emac0_mcg0),
FUNCTION(emac0_mcg1),
FUNCTION(emac0_mcg2),
FUNCTION(emac0_mcg3),
FUNCTION(emac0_mdc),
FUNCTION(emac0_mdio),
FUNCTION(emac0_ptp_aux),
FUNCTION(emac0_ptp_pps),
FUNCTION(emac1_mcg0),
FUNCTION(emac1_mcg1),
FUNCTION(emac1_mcg2),
FUNCTION(emac1_mcg3),
FUNCTION(emac1_mdc),
FUNCTION(emac1_mdio),
FUNCTION(emac1_ptp_aux),
FUNCTION(emac1_ptp_pps),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_gp4),
FUNCTION(gcc_gp5),
FUNCTION(hs0_mi2s),
FUNCTION(hs1_mi2s),
FUNCTION(hs2_mi2s),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(mdp0_vsync0),
FUNCTION(mdp0_vsync1),
FUNCTION(mdp0_vsync2),
FUNCTION(mdp0_vsync3),
FUNCTION(mdp0_vsync4),
FUNCTION(mdp0_vsync5),
FUNCTION(mdp0_vsync6),
FUNCTION(mdp0_vsync7),
FUNCTION(mdp0_vsync8),
FUNCTION(mdp1_vsync0),
FUNCTION(mdp1_vsync1),
FUNCTION(mdp1_vsync2),
FUNCTION(mdp1_vsync3),
FUNCTION(mdp1_vsync4),
FUNCTION(mdp1_vsync5),
FUNCTION(mdp1_vsync6),
FUNCTION(mdp1_vsync7),
FUNCTION(mdp1_vsync8),
FUNCTION(mdp_vsync),
FUNCTION(mi2s1_data0),
FUNCTION(mi2s1_data1),
FUNCTION(mi2s1_sck),
FUNCTION(mi2s1_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(mi2s_mclk0),
FUNCTION(mi2s_mclk1),
FUNCTION(pcie0_clkreq),
FUNCTION(pcie1_clkreq),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_clk),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qup0_se0),
FUNCTION(qup0_se1),
FUNCTION(qup0_se2),
FUNCTION(qup0_se3),
FUNCTION(qup0_se4),
FUNCTION(qup0_se5),
FUNCTION(qup1_se0),
FUNCTION(qup1_se1),
FUNCTION(qup1_se2),
FUNCTION(qup1_se3),
FUNCTION(qup1_se4),
FUNCTION(qup1_se5),
FUNCTION(qup1_se6),
FUNCTION(qup2_se0),
FUNCTION(qup2_se1),
FUNCTION(qup2_se2),
FUNCTION(qup2_se3),
FUNCTION(qup2_se4),
FUNCTION(qup2_se5),
FUNCTION(qup2_se6),
FUNCTION(qup3_se0),
FUNCTION(sail_top),
FUNCTION(sailss_emac0),
FUNCTION(sailss_ospi),
FUNCTION(sgmii_phy),
FUNCTION(tb_trig),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tgu_ch4),
FUNCTION(tgu_ch5),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsense_pwm3),
FUNCTION(tsense_pwm4),
FUNCTION(usb2phy_ac),
FUNCTION(vsense_trigger),
static const struct pinfunction sa8775p_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cci_timer5),
MSM_PIN_FUNCTION(cci_timer6),
MSM_PIN_FUNCTION(cci_timer7),
MSM_PIN_FUNCTION(cci_timer8),
MSM_PIN_FUNCTION(cci_timer9),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(ddr_pxi4),
MSM_PIN_FUNCTION(ddr_pxi5),
MSM_PIN_FUNCTION(edp0_hot),
MSM_PIN_FUNCTION(edp0_lcd),
MSM_PIN_FUNCTION(edp1_hot),
MSM_PIN_FUNCTION(edp1_lcd),
MSM_PIN_FUNCTION(edp2_hot),
MSM_PIN_FUNCTION(edp2_lcd),
MSM_PIN_FUNCTION(edp3_hot),
MSM_PIN_FUNCTION(edp3_lcd),
MSM_PIN_FUNCTION(emac0_mcg0),
MSM_PIN_FUNCTION(emac0_mcg1),
MSM_PIN_FUNCTION(emac0_mcg2),
MSM_PIN_FUNCTION(emac0_mcg3),
MSM_PIN_FUNCTION(emac0_mdc),
MSM_PIN_FUNCTION(emac0_mdio),
MSM_PIN_FUNCTION(emac0_ptp_aux),
MSM_PIN_FUNCTION(emac0_ptp_pps),
MSM_PIN_FUNCTION(emac1_mcg0),
MSM_PIN_FUNCTION(emac1_mcg1),
MSM_PIN_FUNCTION(emac1_mcg2),
MSM_PIN_FUNCTION(emac1_mcg3),
MSM_PIN_FUNCTION(emac1_mdc),
MSM_PIN_FUNCTION(emac1_mdio),
MSM_PIN_FUNCTION(emac1_ptp_aux),
MSM_PIN_FUNCTION(emac1_ptp_pps),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_gp4),
MSM_PIN_FUNCTION(gcc_gp5),
MSM_PIN_FUNCTION(hs0_mi2s),
MSM_PIN_FUNCTION(hs1_mi2s),
MSM_PIN_FUNCTION(hs2_mi2s),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(mdp0_vsync0),
MSM_PIN_FUNCTION(mdp0_vsync1),
MSM_PIN_FUNCTION(mdp0_vsync2),
MSM_PIN_FUNCTION(mdp0_vsync3),
MSM_PIN_FUNCTION(mdp0_vsync4),
MSM_PIN_FUNCTION(mdp0_vsync5),
MSM_PIN_FUNCTION(mdp0_vsync6),
MSM_PIN_FUNCTION(mdp0_vsync7),
MSM_PIN_FUNCTION(mdp0_vsync8),
MSM_PIN_FUNCTION(mdp1_vsync0),
MSM_PIN_FUNCTION(mdp1_vsync1),
MSM_PIN_FUNCTION(mdp1_vsync2),
MSM_PIN_FUNCTION(mdp1_vsync3),
MSM_PIN_FUNCTION(mdp1_vsync4),
MSM_PIN_FUNCTION(mdp1_vsync5),
MSM_PIN_FUNCTION(mdp1_vsync6),
MSM_PIN_FUNCTION(mdp1_vsync7),
MSM_PIN_FUNCTION(mdp1_vsync8),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(mi2s_mclk0),
MSM_PIN_FUNCTION(mi2s_mclk1),
MSM_PIN_FUNCTION(pcie0_clkreq),
MSM_PIN_FUNCTION(pcie1_clkreq),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qup0_se0),
MSM_PIN_FUNCTION(qup0_se1),
MSM_PIN_FUNCTION(qup0_se2),
MSM_PIN_FUNCTION(qup0_se3),
MSM_PIN_FUNCTION(qup0_se4),
MSM_PIN_FUNCTION(qup0_se5),
MSM_PIN_FUNCTION(qup1_se0),
MSM_PIN_FUNCTION(qup1_se1),
MSM_PIN_FUNCTION(qup1_se2),
MSM_PIN_FUNCTION(qup1_se3),
MSM_PIN_FUNCTION(qup1_se4),
MSM_PIN_FUNCTION(qup1_se5),
MSM_PIN_FUNCTION(qup1_se6),
MSM_PIN_FUNCTION(qup2_se0),
MSM_PIN_FUNCTION(qup2_se1),
MSM_PIN_FUNCTION(qup2_se2),
MSM_PIN_FUNCTION(qup2_se3),
MSM_PIN_FUNCTION(qup2_se4),
MSM_PIN_FUNCTION(qup2_se5),
MSM_PIN_FUNCTION(qup2_se6),
MSM_PIN_FUNCTION(qup3_se0),
MSM_PIN_FUNCTION(sail_top),
MSM_PIN_FUNCTION(sailss_emac0),
MSM_PIN_FUNCTION(sailss_ospi),
MSM_PIN_FUNCTION(sgmii_phy),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tgu_ch4),
MSM_PIN_FUNCTION(tgu_ch5),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsense_pwm3),
MSM_PIN_FUNCTION(tsense_pwm4),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(vsense_trigger),
};
/*
@ -1491,6 +1483,23 @@ static const struct msm_pingroup sa8775p_groups[] = {
[153] = SDC_QDSD_PINGROUP(sdc1_data, 0x199000, 9, 0),
};
static const struct msm_gpio_wakeirq_map sa8775p_pdc_map[] = {
{ 0, 169 }, { 1, 174 }, { 2, 170 }, { 3, 175 }, { 4, 171 }, { 5, 173 },
{ 6, 172 }, { 7, 182 }, { 10, 220 }, { 11, 213 }, { 12, 221 },
{ 16, 230 }, { 19, 231 }, { 20, 232 }, { 23, 233 }, { 24, 234 },
{ 26, 223 }, { 27, 235 }, { 28, 209 }, { 29, 176 }, { 30, 200 },
{ 31, 201 }, { 32, 212 }, { 35, 177 }, { 36, 178 }, { 39, 184 },
{ 40, 185 }, { 41, 227 }, { 42, 186 }, { 43, 228 }, { 45, 187 },
{ 47, 188 }, { 48, 194 }, { 51, 195 }, { 52, 196 }, { 55, 197 },
{ 56, 198 }, { 57, 236 }, { 58, 192 }, { 59, 193 }, { 72, 179 },
{ 73, 180 }, { 74, 181 }, { 75, 202 }, { 76, 183 }, { 77, 189 },
{ 78, 190 }, { 79, 191 }, { 80, 199 }, { 83, 204 }, { 84, 205 },
{ 85, 229 }, { 86, 206 }, { 89, 207 }, { 91, 208 }, { 94, 214 },
{ 95, 215 }, { 96, 237 }, { 97, 216 }, { 98, 238 }, { 99, 217 },
{ 100, 239 }, { 105, 219 }, { 106, 210 }, { 107, 211 }, { 108, 222 },
{ 109, 203 }, { 145, 225 }, { 146, 226 },
};
static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
.pins = sa8775p_pins,
.npins = ARRAY_SIZE(sa8775p_pins),
@ -1499,6 +1508,8 @@ static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
.groups = sa8775p_groups,
.ngroups = ARRAY_SIZE(sa8775p_groups),
.ngpios = 150,
.wakeirq_map = sa8775p_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map),
};
static int sa8775p_pinctrl_probe(struct platform_device *pdev)

254
drivers/pinctrl/qcom/pinctrl-sc7180.c
View File

@ -4,7 +4,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -20,18 +19,11 @@ enum {
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -69,9 +61,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -95,9 +87,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -868,120 +860,120 @@ static const char * const qup04_uart_groups[] = {
"gpio115", "gpio116",
};
static const struct msm_function sc7180_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(aoss_cti),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb2),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(audio_ref),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gps_tx),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_ext),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s_0),
FUNCTION(mi2s_1),
FUNCTION(mi2s_2),
FUNCTION(mss_lte),
FUNCTION(m_voc),
FUNCTION(pa_indicator),
FUNCTION(phase_flag),
FUNCTION(PLL_BIST),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(prng_rosc),
FUNCTION(qdss),
FUNCTION(qdss_cti),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qspi_data),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02_i2c),
FUNCTION(qup02_uart),
FUNCTION(qup03),
FUNCTION(qup04_i2c),
FUNCTION(qup04_uart),
FUNCTION(qup05),
FUNCTION(qup10),
FUNCTION(qup11_i2c),
FUNCTION(qup11_uart),
FUNCTION(qup12),
FUNCTION(qup13_i2c),
FUNCTION(qup13_uart),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sd_write),
FUNCTION(sp_cmu),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim_batt),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(_V_GPIO),
FUNCTION(_V_PPS_IN),
FUNCTION(_V_PPS_OUT),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction sc7180_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_ext),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s_0),
MSM_PIN_FUNCTION(mi2s_1),
MSM_PIN_FUNCTION(mi2s_2),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(PLL_BIST),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02_i2c),
MSM_PIN_FUNCTION(qup02_uart),
MSM_PIN_FUNCTION(qup03),
MSM_PIN_FUNCTION(qup04_i2c),
MSM_PIN_FUNCTION(qup04_uart),
MSM_PIN_FUNCTION(qup05),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11_i2c),
MSM_PIN_FUNCTION(qup11_uart),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13_i2c),
MSM_PIN_FUNCTION(qup13_uart),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(_V_GPIO),
MSM_PIN_FUNCTION(_V_PPS_IN),
MSM_PIN_FUNCTION(_V_PPS_OUT),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

322
drivers/pinctrl/qcom/pinctrl-sc7280.c
View File

@ -6,22 +6,14 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -85,9 +77,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1120,154 +1112,154 @@ static const char * const vsense_trigger_groups[] = {
"gpio100",
};
static const struct msm_function sc7280_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_usb0),
FUNCTION(atest_usb00),
FUNCTION(atest_usb01),
FUNCTION(atest_usb02),
FUNCTION(atest_usb03),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cmu_rng0),
FUNCTION(cmu_rng1),
FUNCTION(cmu_rng2),
FUNCTION(cmu_rng3),
FUNCTION(coex_uart1),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(dp_hot),
FUNCTION(dp_lcd),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(egpio),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(host2wlan_sol),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mdp_vsync4),
FUNCTION(mdp_vsync5),
FUNCTION(mi2s0_data0),
FUNCTION(mi2s0_data1),
FUNCTION(mi2s0_sck),
FUNCTION(mi2s0_ws),
FUNCTION(mi2s1_data0),
FUNCTION(mi2s1_data1),
FUNCTION(mi2s1_sck),
FUNCTION(mi2s1_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(mss_grfc0),
FUNCTION(mss_grfc1),
FUNCTION(mss_grfc10),
FUNCTION(mss_grfc11),
FUNCTION(mss_grfc12),
FUNCTION(mss_grfc2),
FUNCTION(mss_grfc3),
FUNCTION(mss_grfc4),
FUNCTION(mss_grfc5),
FUNCTION(mss_grfc6),
FUNCTION(mss_grfc7),
FUNCTION(mss_grfc8),
FUNCTION(mss_grfc9),
FUNCTION(nav_gpio0),
FUNCTION(nav_gpio1),
FUNCTION(nav_gpio2),
FUNCTION(pa_indicator),
FUNCTION(pcie0_clkreqn),
FUNCTION(pcie1_clkreqn),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_clk),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(qdss),
FUNCTION(qdss_cti),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qspi_data),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup03),
FUNCTION(qup04),
FUNCTION(qup05),
FUNCTION(qup06),
FUNCTION(qup07),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(tb_trig),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim0_clk),
FUNCTION(uim0_data),
FUNCTION(uim0_present),
FUNCTION(uim0_reset),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vfr_0),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
static const struct pinfunction sc7280_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_usb0),
MSM_PIN_FUNCTION(atest_usb00),
MSM_PIN_FUNCTION(atest_usb01),
MSM_PIN_FUNCTION(atest_usb02),
MSM_PIN_FUNCTION(atest_usb03),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cmu_rng0),
MSM_PIN_FUNCTION(cmu_rng1),
MSM_PIN_FUNCTION(cmu_rng2),
MSM_PIN_FUNCTION(cmu_rng3),
MSM_PIN_FUNCTION(coex_uart1),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(dp_lcd),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(egpio),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(host2wlan_sol),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mdp_vsync4),
MSM_PIN_FUNCTION(mdp_vsync5),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(mss_grfc0),
MSM_PIN_FUNCTION(mss_grfc1),
MSM_PIN_FUNCTION(mss_grfc10),
MSM_PIN_FUNCTION(mss_grfc11),
MSM_PIN_FUNCTION(mss_grfc12),
MSM_PIN_FUNCTION(mss_grfc2),
MSM_PIN_FUNCTION(mss_grfc3),
MSM_PIN_FUNCTION(mss_grfc4),
MSM_PIN_FUNCTION(mss_grfc5),
MSM_PIN_FUNCTION(mss_grfc6),
MSM_PIN_FUNCTION(mss_grfc7),
MSM_PIN_FUNCTION(mss_grfc8),
MSM_PIN_FUNCTION(mss_grfc9),
MSM_PIN_FUNCTION(nav_gpio0),
MSM_PIN_FUNCTION(nav_gpio1),
MSM_PIN_FUNCTION(nav_gpio2),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pcie0_clkreqn),
MSM_PIN_FUNCTION(pcie1_clkreqn),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(qup03),
MSM_PIN_FUNCTION(qup04),
MSM_PIN_FUNCTION(qup05),
MSM_PIN_FUNCTION(qup06),
MSM_PIN_FUNCTION(qup07),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim0_clk),
MSM_PIN_FUNCTION(uim0_data),
MSM_PIN_FUNCTION(uim0_present),
MSM_PIN_FUNCTION(uim0_reset),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_0),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

292
drivers/pinctrl/qcom/pinctrl-sc8180x.c
View File

@ -7,7 +7,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -38,19 +37,12 @@ static const struct tile_info sc8180x_tile_info[] = {
{ 0x00100000, 0x00300000, },
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -91,9 +83,9 @@ static const struct tile_info sc8180x_tile_info[] = {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -117,9 +109,9 @@ static const struct tile_info sc8180x_tile_info[] = {
#define UFS_RESET(pg_name) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = 0xb6000, \
.io_reg = 0xb6004, \
.intr_cfg_reg = 0, \
@ -1238,136 +1230,136 @@ static const char * const wmss_reset_groups[] = {
"gpio63",
};
static const struct msm_function sc8180x_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(aoss_cti),
FUNCTION(atest_char),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb0),
FUNCTION(atest_usb1),
FUNCTION(atest_usb2),
FUNCTION(atest_usb3),
FUNCTION(atest_usb4),
FUNCTION(audio_ref),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cci_timer5),
FUNCTION(cci_timer6),
FUNCTION(cci_timer7),
FUNCTION(cci_timer8),
FUNCTION(cci_timer9),
FUNCTION(cri_trng),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi),
FUNCTION(debug_hot),
FUNCTION(dp_hot),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(emac_phy),
FUNCTION(emac_pps),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_gp4),
FUNCTION(gcc_gp5),
FUNCTION(gpio),
FUNCTION(gps),
FUNCTION(grfc),
FUNCTION(hs1_mi2s),
FUNCTION(hs2_mi2s),
FUNCTION(hs3_mi2s),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mdp_vsync4),
FUNCTION(mdp_vsync5),
FUNCTION(mss_lte),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(pci_e2),
FUNCTION(pci_e3),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink),
FUNCTION(qspi0),
FUNCTION(qspi0_clk),
FUNCTION(qspi0_cs),
FUNCTION(qspi1),
FUNCTION(qspi1_clk),
FUNCTION(qspi1_cs),
FUNCTION(qua_mi2s),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(rgmii),
FUNCTION(sd_write),
FUNCTION(sdc4),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(sp_cmu),
FUNCTION(spkr_i2s),
FUNCTION(ter_mi2s),
FUNCTION(tgu),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim_batt),
FUNCTION(usb0_phy),
FUNCTION(usb1_phy),
FUNCTION(usb2phy_ac),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc),
FUNCTION(wlan2_adc),
FUNCTION(wmss_reset),
static const struct pinfunction sc8180x_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb0),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb3),
MSM_PIN_FUNCTION(atest_usb4),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cci_timer5),
MSM_PIN_FUNCTION(cci_timer6),
MSM_PIN_FUNCTION(cci_timer7),
MSM_PIN_FUNCTION(cci_timer8),
MSM_PIN_FUNCTION(cci_timer9),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi),
MSM_PIN_FUNCTION(debug_hot),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(emac_phy),
MSM_PIN_FUNCTION(emac_pps),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_gp4),
MSM_PIN_FUNCTION(gcc_gp5),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gps),
MSM_PIN_FUNCTION(grfc),
MSM_PIN_FUNCTION(hs1_mi2s),
MSM_PIN_FUNCTION(hs2_mi2s),
MSM_PIN_FUNCTION(hs3_mi2s),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mdp_vsync4),
MSM_PIN_FUNCTION(mdp_vsync5),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pci_e2),
MSM_PIN_FUNCTION(pci_e3),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi0_clk),
MSM_PIN_FUNCTION(qspi0_cs),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi1_clk),
MSM_PIN_FUNCTION(qspi1_cs),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(rgmii),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb0_phy),
MSM_PIN_FUNCTION(usb1_phy),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc),
MSM_PIN_FUNCTION(wlan2_adc),
MSM_PIN_FUNCTION(wmss_reset),
};
/* Every pin is maintained as a single group, and missing or non-existing pin
@ -1630,7 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = {
static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev)
{
int nres_num = pdev->num_resources + ARRAY_SIZE(sc8180x_tiles) - 1;
struct resource *mres, *nres, *res;
struct resource *mres = NULL;
struct resource *nres, *res;
int i, ret;
/*
@ -1657,6 +1650,9 @@ static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev)
*res++ = *r;
}
if (!mres)
return -EINVAL;
/* Append tile memory resources */
for (i = 0; i < ARRAY_SIZE(sc8180x_tiles); i++, res++) {
const struct tile_info *info = &sc8180x_tile_info[i];

358
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
View File

@ -7,23 +7,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -85,9 +77,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1476,172 +1468,172 @@ static const char * const vsense_trigger_groups[] = {
"gpio81",
};
static const struct msm_function sc8280xp_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_usb),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cci_timer5),
FUNCTION(cci_timer6),
FUNCTION(cci_timer7),
FUNCTION(cci_timer8),
FUNCTION(cci_timer9),
FUNCTION(cmu_rng),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(ddr_pxi4),
FUNCTION(ddr_pxi5),
FUNCTION(ddr_pxi6),
FUNCTION(ddr_pxi7),
FUNCTION(dp2_hot),
FUNCTION(dp3_hot),
FUNCTION(edp0_lcd),
FUNCTION(edp1_lcd),
FUNCTION(edp2_lcd),
FUNCTION(edp3_lcd),
FUNCTION(edp_hot),
FUNCTION(egpio),
FUNCTION(emac0_dll),
FUNCTION(emac0_mcg0),
FUNCTION(emac0_mcg1),
FUNCTION(emac0_mcg2),
FUNCTION(emac0_mcg3),
FUNCTION(emac0_phy),
FUNCTION(emac0_ptp),
FUNCTION(emac1_dll0),
FUNCTION(emac1_dll1),
FUNCTION(emac1_mcg0),
FUNCTION(emac1_mcg1),
FUNCTION(emac1_mcg2),
FUNCTION(emac1_mcg3),
FUNCTION(emac1_phy),
FUNCTION(emac1_ptp),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_gp4),
FUNCTION(gcc_gp5),
FUNCTION(gpio),
FUNCTION(hs1_mi2s),
FUNCTION(hs2_mi2s),
FUNCTION(hs3_mi2s),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(mdp0_vsync0),
FUNCTION(mdp0_vsync1),
FUNCTION(mdp0_vsync2),
FUNCTION(mdp0_vsync3),
FUNCTION(mdp0_vsync4),
FUNCTION(mdp0_vsync5),
FUNCTION(mdp0_vsync6),
FUNCTION(mdp0_vsync7),
FUNCTION(mdp0_vsync8),
FUNCTION(mdp1_vsync0),
FUNCTION(mdp1_vsync1),
FUNCTION(mdp1_vsync2),
FUNCTION(mdp1_vsync3),
FUNCTION(mdp1_vsync4),
FUNCTION(mdp1_vsync5),
FUNCTION(mdp1_vsync6),
FUNCTION(mdp1_vsync7),
FUNCTION(mdp1_vsync8),
FUNCTION(mdp_vsync),
FUNCTION(mi2s0_data0),
FUNCTION(mi2s0_data1),
FUNCTION(mi2s0_sck),
FUNCTION(mi2s0_ws),
FUNCTION(mi2s1_data0),
FUNCTION(mi2s1_data1),
FUNCTION(mi2s1_sck),
FUNCTION(mi2s1_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(mi2s_mclk1),
FUNCTION(mi2s_mclk2),
FUNCTION(pcie2a_clkreq),
FUNCTION(pcie2b_clkreq),
FUNCTION(pcie3a_clkreq),
FUNCTION(pcie3b_clkreq),
FUNCTION(pcie4_clkreq),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_clk),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qspi),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup20),
FUNCTION(qup21),
FUNCTION(qup22),
FUNCTION(qup23),
FUNCTION(rgmii_0),
FUNCTION(rgmii_1),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(tb_trig),
FUNCTION(tgu),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsense_pwm3),
FUNCTION(tsense_pwm4),
FUNCTION(usb0_dp),
FUNCTION(usb0_phy),
FUNCTION(usb0_sbrx),
FUNCTION(usb0_sbtx),
FUNCTION(usb0_usb4),
FUNCTION(usb1_dp),
FUNCTION(usb1_phy),
FUNCTION(usb1_sbrx),
FUNCTION(usb1_sbtx),
FUNCTION(usb1_usb4),
FUNCTION(usb2phy_ac),
FUNCTION(vsense_trigger),
static const struct pinfunction sc8280xp_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cci_timer5),
MSM_PIN_FUNCTION(cci_timer6),
MSM_PIN_FUNCTION(cci_timer7),
MSM_PIN_FUNCTION(cci_timer8),
MSM_PIN_FUNCTION(cci_timer9),
MSM_PIN_FUNCTION(cmu_rng),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(ddr_pxi4),
MSM_PIN_FUNCTION(ddr_pxi5),
MSM_PIN_FUNCTION(ddr_pxi6),
MSM_PIN_FUNCTION(ddr_pxi7),
MSM_PIN_FUNCTION(dp2_hot),
MSM_PIN_FUNCTION(dp3_hot),
MSM_PIN_FUNCTION(edp0_lcd),
MSM_PIN_FUNCTION(edp1_lcd),
MSM_PIN_FUNCTION(edp2_lcd),
MSM_PIN_FUNCTION(edp3_lcd),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(egpio),
MSM_PIN_FUNCTION(emac0_dll),
MSM_PIN_FUNCTION(emac0_mcg0),
MSM_PIN_FUNCTION(emac0_mcg1),
MSM_PIN_FUNCTION(emac0_mcg2),
MSM_PIN_FUNCTION(emac0_mcg3),
MSM_PIN_FUNCTION(emac0_phy),
MSM_PIN_FUNCTION(emac0_ptp),
MSM_PIN_FUNCTION(emac1_dll0),
MSM_PIN_FUNCTION(emac1_dll1),
MSM_PIN_FUNCTION(emac1_mcg0),
MSM_PIN_FUNCTION(emac1_mcg1),
MSM_PIN_FUNCTION(emac1_mcg2),
MSM_PIN_FUNCTION(emac1_mcg3),
MSM_PIN_FUNCTION(emac1_phy),
MSM_PIN_FUNCTION(emac1_ptp),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_gp4),
MSM_PIN_FUNCTION(gcc_gp5),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(hs1_mi2s),
MSM_PIN_FUNCTION(hs2_mi2s),
MSM_PIN_FUNCTION(hs3_mi2s),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(mdp0_vsync0),
MSM_PIN_FUNCTION(mdp0_vsync1),
MSM_PIN_FUNCTION(mdp0_vsync2),
MSM_PIN_FUNCTION(mdp0_vsync3),
MSM_PIN_FUNCTION(mdp0_vsync4),
MSM_PIN_FUNCTION(mdp0_vsync5),
MSM_PIN_FUNCTION(mdp0_vsync6),
MSM_PIN_FUNCTION(mdp0_vsync7),
MSM_PIN_FUNCTION(mdp0_vsync8),
MSM_PIN_FUNCTION(mdp1_vsync0),
MSM_PIN_FUNCTION(mdp1_vsync1),
MSM_PIN_FUNCTION(mdp1_vsync2),
MSM_PIN_FUNCTION(mdp1_vsync3),
MSM_PIN_FUNCTION(mdp1_vsync4),
MSM_PIN_FUNCTION(mdp1_vsync5),
MSM_PIN_FUNCTION(mdp1_vsync6),
MSM_PIN_FUNCTION(mdp1_vsync7),
MSM_PIN_FUNCTION(mdp1_vsync8),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(mi2s_mclk1),
MSM_PIN_FUNCTION(mi2s_mclk2),
MSM_PIN_FUNCTION(pcie2a_clkreq),
MSM_PIN_FUNCTION(pcie2b_clkreq),
MSM_PIN_FUNCTION(pcie3a_clkreq),
MSM_PIN_FUNCTION(pcie3b_clkreq),
MSM_PIN_FUNCTION(pcie4_clkreq),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qspi),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup20),
MSM_PIN_FUNCTION(qup21),
MSM_PIN_FUNCTION(qup22),
MSM_PIN_FUNCTION(qup23),
MSM_PIN_FUNCTION(rgmii_0),
MSM_PIN_FUNCTION(rgmii_1),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsense_pwm3),
MSM_PIN_FUNCTION(tsense_pwm4),
MSM_PIN_FUNCTION(usb0_dp),
MSM_PIN_FUNCTION(usb0_phy),
MSM_PIN_FUNCTION(usb0_sbrx),
MSM_PIN_FUNCTION(usb0_sbtx),
MSM_PIN_FUNCTION(usb0_usb4),
MSM_PIN_FUNCTION(usb1_dp),
MSM_PIN_FUNCTION(usb1_phy),
MSM_PIN_FUNCTION(usb1_sbrx),
MSM_PIN_FUNCTION(usb1_sbtx),
MSM_PIN_FUNCTION(usb1_usb4),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(vsense_trigger),
};
static const struct msm_pingroup sc8280xp_groups[] = {

387
drivers/pinctrl/qcom/pinctrl-sdm660.c
View File

@ -7,7 +7,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -25,19 +24,11 @@ enum {
#define REG_SIZE 0x1000
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -75,9 +66,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -1099,189 +1090,189 @@ static const char * const wlan2_adc1_groups[] = {
"gpio10",
};
static const struct msm_function sdm660_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_gpsadc0),
FUNCTION(atest_gpsadc1),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb2),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(audio_ref),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_i2c6),
FUNCTION(blsp_i2c7),
FUNCTION(blsp_i2c8_a),
FUNCTION(blsp_i2c8_b),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi3_cs1),
FUNCTION(blsp_spi3_cs2),
FUNCTION(blsp_spi4),
FUNCTION(blsp_spi5),
FUNCTION(blsp_spi6),
FUNCTION(blsp_spi7),
FUNCTION(blsp_spi8_a),
FUNCTION(blsp_spi8_b),
FUNCTION(blsp_spi8_cs1),
FUNCTION(blsp_spi8_cs2),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart5),
FUNCTION(blsp_uart6_a),
FUNCTION(blsp_uart6_b),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim5),
FUNCTION(blsp_uim6),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(gps_tx_a),
FUNCTION(gps_tx_b),
FUNCTION(gps_tx_c),
FUNCTION(isense_dbg),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdss_vsync0),
FUNCTION(mdss_vsync1),
FUNCTION(mdss_vsync2),
FUNCTION(mdss_vsync3),
FUNCTION(mss_lte),
FUNCTION(nav_pps_a),
FUNCTION(nav_pps_b),
FUNCTION(nav_pps_c),
FUNCTION(pa_indicator),
FUNCTION(phase_flag0),
FUNCTION(phase_flag1),
FUNCTION(phase_flag2),
FUNCTION(phase_flag3),
FUNCTION(phase_flag4),
FUNCTION(phase_flag5),
FUNCTION(phase_flag6),
FUNCTION(phase_flag7),
FUNCTION(phase_flag8),
FUNCTION(phase_flag9),
FUNCTION(phase_flag10),
FUNCTION(phase_flag11),
FUNCTION(phase_flag12),
FUNCTION(phase_flag13),
FUNCTION(phase_flag14),
FUNCTION(phase_flag15),
FUNCTION(phase_flag16),
FUNCTION(phase_flag17),
FUNCTION(phase_flag18),
FUNCTION(phase_flag19),
FUNCTION(phase_flag20),
FUNCTION(phase_flag21),
FUNCTION(phase_flag22),
FUNCTION(phase_flag23),
FUNCTION(phase_flag24),
FUNCTION(phase_flag25),
FUNCTION(phase_flag26),
FUNCTION(phase_flag27),
FUNCTION(phase_flag28),
FUNCTION(phase_flag29),
FUNCTION(phase_flag30),
FUNCTION(phase_flag31),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(pwr_crypto),
FUNCTION(pwr_modem),
FUNCTION(pwr_nav),
FUNCTION(qdss_cti0_a),
FUNCTION(qdss_cti0_b),
FUNCTION(qdss_cti1_a),
FUNCTION(qdss_cti1_b),
FUNCTION(qdss_gpio),
FUNCTION(qdss_gpio0),
FUNCTION(qdss_gpio1),
FUNCTION(qdss_gpio10),
FUNCTION(qdss_gpio11),
FUNCTION(qdss_gpio12),
FUNCTION(qdss_gpio13),
FUNCTION(qdss_gpio14),
FUNCTION(qdss_gpio15),
FUNCTION(qdss_gpio2),
FUNCTION(qdss_gpio3),
FUNCTION(qdss_gpio4),
FUNCTION(qdss_gpio5),
FUNCTION(qdss_gpio6),
FUNCTION(qdss_gpio7),
FUNCTION(qdss_gpio8),
FUNCTION(qdss_gpio9),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qspi_data0),
FUNCTION(qspi_data1),
FUNCTION(qspi_data2),
FUNCTION(qspi_data3),
FUNCTION(qspi_resetn),
FUNCTION(sec_mi2s),
FUNCTION(sndwire_clk),
FUNCTION(sndwire_data),
FUNCTION(sp_cmu),
FUNCTION(ssc_irq),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(vfr_1),
FUNCTION(vsense_clkout),
FUNCTION(vsense_data0),
FUNCTION(vsense_data1),
FUNCTION(vsense_mode),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction sdm660_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_gpsadc0),
MSM_PIN_FUNCTION(atest_gpsadc1),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_i2c5),
MSM_PIN_FUNCTION(blsp_i2c6),
MSM_PIN_FUNCTION(blsp_i2c7),
MSM_PIN_FUNCTION(blsp_i2c8_a),
MSM_PIN_FUNCTION(blsp_i2c8_b),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi3_cs1),
MSM_PIN_FUNCTION(blsp_spi3_cs2),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_spi5),
MSM_PIN_FUNCTION(blsp_spi6),
MSM_PIN_FUNCTION(blsp_spi7),
MSM_PIN_FUNCTION(blsp_spi8_a),
MSM_PIN_FUNCTION(blsp_spi8_b),
MSM_PIN_FUNCTION(blsp_spi8_cs1),
MSM_PIN_FUNCTION(blsp_spi8_cs2),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart5),
MSM_PIN_FUNCTION(blsp_uart6_a),
MSM_PIN_FUNCTION(blsp_uart6_b),
MSM_PIN_FUNCTION(blsp_uim1),
MSM_PIN_FUNCTION(blsp_uim2),
MSM_PIN_FUNCTION(blsp_uim5),
MSM_PIN_FUNCTION(blsp_uim6),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gps_tx_a),
MSM_PIN_FUNCTION(gps_tx_b),
MSM_PIN_FUNCTION(gps_tx_c),
MSM_PIN_FUNCTION(isense_dbg),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdss_vsync0),
MSM_PIN_FUNCTION(mdss_vsync1),
MSM_PIN_FUNCTION(mdss_vsync2),
MSM_PIN_FUNCTION(mdss_vsync3),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps_a),
MSM_PIN_FUNCTION(nav_pps_b),
MSM_PIN_FUNCTION(nav_pps_c),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(phase_flag0),
MSM_PIN_FUNCTION(phase_flag1),
MSM_PIN_FUNCTION(phase_flag2),
MSM_PIN_FUNCTION(phase_flag3),
MSM_PIN_FUNCTION(phase_flag4),
MSM_PIN_FUNCTION(phase_flag5),
MSM_PIN_FUNCTION(phase_flag6),
MSM_PIN_FUNCTION(phase_flag7),
MSM_PIN_FUNCTION(phase_flag8),
MSM_PIN_FUNCTION(phase_flag9),
MSM_PIN_FUNCTION(phase_flag10),
MSM_PIN_FUNCTION(phase_flag11),
MSM_PIN_FUNCTION(phase_flag12),
MSM_PIN_FUNCTION(phase_flag13),
MSM_PIN_FUNCTION(phase_flag14),
MSM_PIN_FUNCTION(phase_flag15),
MSM_PIN_FUNCTION(phase_flag16),
MSM_PIN_FUNCTION(phase_flag17),
MSM_PIN_FUNCTION(phase_flag18),
MSM_PIN_FUNCTION(phase_flag19),
MSM_PIN_FUNCTION(phase_flag20),
MSM_PIN_FUNCTION(phase_flag21),
MSM_PIN_FUNCTION(phase_flag22),
MSM_PIN_FUNCTION(phase_flag23),
MSM_PIN_FUNCTION(phase_flag24),
MSM_PIN_FUNCTION(phase_flag25),
MSM_PIN_FUNCTION(phase_flag26),
MSM_PIN_FUNCTION(phase_flag27),
MSM_PIN_FUNCTION(phase_flag28),
MSM_PIN_FUNCTION(phase_flag29),
MSM_PIN_FUNCTION(phase_flag30),
MSM_PIN_FUNCTION(phase_flag31),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(pwr_crypto),
MSM_PIN_FUNCTION(pwr_modem),
MSM_PIN_FUNCTION(pwr_nav),
MSM_PIN_FUNCTION(qdss_cti0_a),
MSM_PIN_FUNCTION(qdss_cti0_b),
MSM_PIN_FUNCTION(qdss_cti1_a),
MSM_PIN_FUNCTION(qdss_cti1_b),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qdss_gpio0),
MSM_PIN_FUNCTION(qdss_gpio1),
MSM_PIN_FUNCTION(qdss_gpio10),
MSM_PIN_FUNCTION(qdss_gpio11),
MSM_PIN_FUNCTION(qdss_gpio12),
MSM_PIN_FUNCTION(qdss_gpio13),
MSM_PIN_FUNCTION(qdss_gpio14),
MSM_PIN_FUNCTION(qdss_gpio15),
MSM_PIN_FUNCTION(qdss_gpio2),
MSM_PIN_FUNCTION(qdss_gpio3),
MSM_PIN_FUNCTION(qdss_gpio4),
MSM_PIN_FUNCTION(qdss_gpio5),
MSM_PIN_FUNCTION(qdss_gpio6),
MSM_PIN_FUNCTION(qdss_gpio7),
MSM_PIN_FUNCTION(qdss_gpio8),
MSM_PIN_FUNCTION(qdss_gpio9),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qspi_data0),
MSM_PIN_FUNCTION(qspi_data1),
MSM_PIN_FUNCTION(qspi_data2),
MSM_PIN_FUNCTION(qspi_data3),
MSM_PIN_FUNCTION(qspi_resetn),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sndwire_clk),
MSM_PIN_FUNCTION(sndwire_data),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(ssc_irq),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_clkout),
MSM_PIN_FUNCTION(vsense_data0),
MSM_PIN_FUNCTION(vsense_data1),
MSM_PIN_FUNCTION(vsense_mode),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
static const struct msm_pingroup sdm660_groups[] = {

284
drivers/pinctrl/qcom/pinctrl-sdm670.c
View File

@ -7,17 +7,9 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define NORTH 0x00500000
#define SOUTH 0x00900000
#define WEST 0x00100000
@ -25,9 +17,9 @@
#define REG_SIZE 0x1000
#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -68,9 +60,9 @@
*/
#define PINGROUP_DUMMY(id) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.ctl_reg = 0, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -93,9 +85,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -118,9 +110,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -998,132 +990,132 @@ static const char * const mss_lte_groups[] = {
"gpio144", "gpio145",
};
static const struct msm_function sdm670_functions[] = {
FUNCTION(gpio),
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb2),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(copy_gp),
FUNCTION(copy_phase),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gps_tx),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_slimbus),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mss_lte),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qua_mi2s),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sdc4_data),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(ter_mi2s),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(tsif2_clk),
FUNCTION(tsif2_data),
FUNCTION(tsif2_en),
FUNCTION(tsif2_error),
FUNCTION(tsif2_sync),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
FUNCTION(wsa_clk),
FUNCTION(wsa_data),
static const struct pinfunction sdm670_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(copy_gp),
MSM_PIN_FUNCTION(copy_phase),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sdc4_data),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsif1_clk),
MSM_PIN_FUNCTION(tsif1_data),
MSM_PIN_FUNCTION(tsif1_en),
MSM_PIN_FUNCTION(tsif1_error),
MSM_PIN_FUNCTION(tsif1_sync),
MSM_PIN_FUNCTION(tsif2_clk),
MSM_PIN_FUNCTION(tsif2_data),
MSM_PIN_FUNCTION(tsif2_en),
MSM_PIN_FUNCTION(tsif2_error),
MSM_PIN_FUNCTION(tsif2_sync),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
MSM_PIN_FUNCTION(wsa_clk),
MSM_PIN_FUNCTION(wsa_data),
};
/*

286
drivers/pinctrl/qcom/pinctrl-sdm845.c
View File

@ -7,26 +7,18 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define NORTH 0x00500000
#define SOUTH 0x00900000
#define EAST 0x00100000
#define REG_SIZE 0x1000
#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -64,9 +56,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -89,9 +81,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -983,136 +975,136 @@ static const char * const tsif1_sync_groups[] = {
"gpio12",
};
static const struct msm_function sdm845_functions[] = {
FUNCTION(gpio),
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb2),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(audio_ref),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_slimbus),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mss_lte),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qspi_data),
FUNCTION(qua_mi2s),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(sd_write),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sdc4_data),
FUNCTION(sec_mi2s),
FUNCTION(sp_cmu),
FUNCTION(spkr_i2s),
FUNCTION(ter_mi2s),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(tsif2_clk),
FUNCTION(tsif2_data),
FUNCTION(tsif2_en),
FUNCTION(tsif2_error),
FUNCTION(tsif2_sync),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction sdm845_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qspi_data),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sdc4_data),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif1_clk),
MSM_PIN_FUNCTION(tsif1_data),
MSM_PIN_FUNCTION(tsif1_en),
MSM_PIN_FUNCTION(tsif1_error),
MSM_PIN_FUNCTION(tsif1_sync),
MSM_PIN_FUNCTION(tsif2_clk),
MSM_PIN_FUNCTION(tsif2_data),
MSM_PIN_FUNCTION(tsif2_en),
MSM_PIN_FUNCTION(tsif2_error),
MSM_PIN_FUNCTION(tsif2_sync),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

190
drivers/pinctrl/qcom/pinctrl-sdx55.c
View File

@ -6,24 +6,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -765,91 +757,91 @@ static const char * const spmi_coex_groups[] = {
"gpio44", "gpio45",
};
static const struct msm_function sdx55_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(atest),
FUNCTION(audio_ref),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(char_exec),
FUNCTION(coex_uart),
FUNCTION(coex_uart2),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ebi0_wrcdc),
FUNCTION(ebi2_a),
FUNCTION(ebi2_lcd),
FUNCTION(emac_gcc0),
FUNCTION(emac_gcc1),
FUNCTION(emac_pps0),
FUNCTION(emac_pps1),
FUNCTION(ext_dbg),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_plltest),
FUNCTION(gpio),
FUNCTION(i2s_mclk),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(mgpi_clk),
FUNCTION(m_voc),
FUNCTION(native_char),
FUNCTION(native_char0),
FUNCTION(native_char1),
FUNCTION(native_char2),
FUNCTION(native_char3),
FUNCTION(native_tsens),
FUNCTION(native_tsense),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pcie_clkreq),
FUNCTION(pci_e),
FUNCTION(pll_bist),
FUNCTION(pll_ref),
FUNCTION(pll_test),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qdss_stm),
FUNCTION(qlink0_en),
FUNCTION(qlink0_req),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_en),
FUNCTION(qlink1_req),
FUNCTION(qlink1_wmss),
FUNCTION(spmi_coex),
FUNCTION(sec_mi2s),
FUNCTION(spmi_vgi),
FUNCTION(tgu_ch0),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb2phy_ac),
FUNCTION(vsense_trigger),
static const struct pinfunction sdx55_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(char_exec),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(coex_uart2),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(emac_gcc0),
MSM_PIN_FUNCTION(emac_gcc1),
MSM_PIN_FUNCTION(emac_pps0),
MSM_PIN_FUNCTION(emac_pps1),
MSM_PIN_FUNCTION(ext_dbg),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(i2s_mclk),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(mgpi_clk),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(native_char),
MSM_PIN_FUNCTION(native_char0),
MSM_PIN_FUNCTION(native_char1),
MSM_PIN_FUNCTION(native_char2),
MSM_PIN_FUNCTION(native_char3),
MSM_PIN_FUNCTION(native_tsens),
MSM_PIN_FUNCTION(native_tsense),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pcie_clkreq),
MSM_PIN_FUNCTION(pci_e),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_ref),
MSM_PIN_FUNCTION(pll_test),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qdss_stm),
MSM_PIN_FUNCTION(qlink0_en),
MSM_PIN_FUNCTION(qlink0_req),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_en),
MSM_PIN_FUNCTION(qlink1_req),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(spmi_coex),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(spmi_vgi),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

194
drivers/pinctrl/qcom/pinctrl-sdx65.c
View File

@ -6,24 +6,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x0
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -85,9 +77,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -700,90 +692,90 @@ static const char * const sdc1_tb_groups[] = {
"gpio106",
};
static const struct msm_function sdx65_functions[] = {
FUNCTION(qlink0_wmss),
FUNCTION(adsp_ext),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(audio_ref),
FUNCTION(bimc_dte0),
FUNCTION(bimc_dte1),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c4),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi4),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart4),
FUNCTION(char_exec),
FUNCTION(coex_uart),
FUNCTION(coex_uart2),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ebi0_wrcdc),
FUNCTION(ebi2_a),
FUNCTION(ebi2_lcd),
FUNCTION(ext_dbg),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gcc_plltest),
FUNCTION(gpio),
FUNCTION(i2s_mclk),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(mgpi_clk),
FUNCTION(native_char),
FUNCTION(native_tsens),
FUNCTION(native_tsense),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pci_e),
FUNCTION(pcie_clkreq),
FUNCTION(pll_bist),
FUNCTION(pll_ref),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink0_en),
FUNCTION(qlink0_req),
FUNCTION(qlink1_en),
FUNCTION(qlink1_req),
FUNCTION(qlink1_wmss),
FUNCTION(qlink2_en),
FUNCTION(qlink2_req),
FUNCTION(qlink2_wmss),
FUNCTION(sdc1_tb),
FUNCTION(sec_mi2s),
FUNCTION(spmi_coex),
FUNCTION(spmi_vgi),
FUNCTION(tgu_ch0),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb2phy_ac),
FUNCTION(vsense_trigger),
static const struct pinfunction sdx65_functions[] = {
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(bimc_dte0),
MSM_PIN_FUNCTION(bimc_dte1),
MSM_PIN_FUNCTION(blsp_i2c1),
MSM_PIN_FUNCTION(blsp_i2c2),
MSM_PIN_FUNCTION(blsp_i2c3),
MSM_PIN_FUNCTION(blsp_i2c4),
MSM_PIN_FUNCTION(blsp_spi1),
MSM_PIN_FUNCTION(blsp_spi2),
MSM_PIN_FUNCTION(blsp_spi3),
MSM_PIN_FUNCTION(blsp_spi4),
MSM_PIN_FUNCTION(blsp_uart1),
MSM_PIN_FUNCTION(blsp_uart2),
MSM_PIN_FUNCTION(blsp_uart3),
MSM_PIN_FUNCTION(blsp_uart4),
MSM_PIN_FUNCTION(char_exec),
MSM_PIN_FUNCTION(coex_uart),
MSM_PIN_FUNCTION(coex_uart2),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ebi0_wrcdc),
MSM_PIN_FUNCTION(ebi2_a),
MSM_PIN_FUNCTION(ebi2_lcd),
MSM_PIN_FUNCTION(ext_dbg),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gcc_plltest),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(i2s_mclk),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mgpi_clk),
MSM_PIN_FUNCTION(native_char),
MSM_PIN_FUNCTION(native_tsens),
MSM_PIN_FUNCTION(native_tsense),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e),
MSM_PIN_FUNCTION(pcie_clkreq),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_ref),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_en),
MSM_PIN_FUNCTION(qlink0_req),
MSM_PIN_FUNCTION(qlink1_en),
MSM_PIN_FUNCTION(qlink1_req),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qlink2_en),
MSM_PIN_FUNCTION(qlink2_req),
MSM_PIN_FUNCTION(qlink2_wmss),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(spmi_coex),
MSM_PIN_FUNCTION(spmi_vgi),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

1144
drivers/pinctrl/qcom/pinctrl-sdx75.c Normal file
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File diff suppressed because it is too large Load Diff

162
drivers/pinctrl/qcom/pinctrl-sm6115.c
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@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -22,18 +21,11 @@ enum {
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -71,9 +63,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -97,9 +89,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -676,74 +668,74 @@ static const char * const ddr_pxi3_groups[] = {
"gpio104", "gpio105",
};
static const struct msm_function sm6115_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer),
FUNCTION(cri_trng),
FUNCTION(dac_calib),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gsm0_tx),
FUNCTION(gsm1_tx),
FUNCTION(jitter_bist),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync_out_0),
FUNCTION(mdp_vsync_out_1),
FUNCTION(mpm_pwr),
FUNCTION(mss_lte),
FUNCTION(m_voc),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pbs),
FUNCTION(pbs_out),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sd_write),
FUNCTION(ssbi_wtr1),
FUNCTION(tgu),
FUNCTION(tsense_pwm),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
static const struct pinfunction sm6115_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dac_calib),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gsm0_tx),
MSM_PIN_FUNCTION(gsm1_tx),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync_out_0),
MSM_PIN_FUNCTION(mdp_vsync_out_1),
MSM_PIN_FUNCTION(mpm_pwr),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pbs),
MSM_PIN_FUNCTION(pbs_out),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(ssbi_wtr1),
MSM_PIN_FUNCTION(tgu),
MSM_PIN_FUNCTION(tsense_pwm),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

282
drivers/pinctrl/qcom/pinctrl-sm6125.c
View File

@ -3,7 +3,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -19,18 +18,11 @@ enum {
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -68,9 +60,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -94,9 +86,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -949,134 +941,134 @@ static const char * const dmic1_data_groups[] = {
"gpio128",
};
static const struct msm_function sm6125_functions[] = {
FUNCTION(qup00),
FUNCTION(gpio),
FUNCTION(qdss),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_bist),
FUNCTION(atest_tsens2),
FUNCTION(vsense_trigger),
FUNCTION(atest_usb1),
FUNCTION(gp_pdm1),
FUNCTION(phase_flag),
FUNCTION(dbg_out),
FUNCTION(qup14),
FUNCTION(atest_usb11),
FUNCTION(ddr_pxi2),
FUNCTION(atest_usb10),
FUNCTION(jitter_bist),
FUNCTION(ddr_pxi3),
FUNCTION(pll_bypassnl),
FUNCTION(pll_bist),
FUNCTION(qup03),
FUNCTION(pll_reset),
FUNCTION(agera_pll),
FUNCTION(qdss_cti),
FUNCTION(qup04),
FUNCTION(wlan2_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wsa_clk),
FUNCTION(qup13),
FUNCTION(ter_mi2s),
FUNCTION(wsa_data),
FUNCTION(qup10),
FUNCTION(gcc_gp3),
FUNCTION(qup12),
FUNCTION(sd_write),
FUNCTION(qup11),
FUNCTION(cam_mclk),
FUNCTION(atest_tsens),
FUNCTION(cci_i2c),
FUNCTION(cci_timer2),
FUNCTION(cci_timer1),
FUNCTION(gcc_gp2),
FUNCTION(cci_async),
FUNCTION(cci_timer4),
FUNCTION(cci_timer0),
FUNCTION(gcc_gp1),
FUNCTION(cci_timer3),
FUNCTION(wlan1_adc1),
FUNCTION(wlan1_adc0),
FUNCTION(qlink_request),
FUNCTION(qlink_enable),
FUNCTION(pa_indicator),
FUNCTION(nav_pps),
FUNCTION(gps_tx),
FUNCTION(gp_pdm0),
FUNCTION(atest_usb13),
FUNCTION(ddr_pxi1),
FUNCTION(atest_usb12),
FUNCTION(cri_trng0),
FUNCTION(cri_trng),
FUNCTION(cri_trng1),
FUNCTION(gp_pdm2),
FUNCTION(sp_cmu),
FUNCTION(atest_usb2),
FUNCTION(atest_usb23),
FUNCTION(uim2_data),
FUNCTION(uim2_clk),
FUNCTION(uim2_reset),
FUNCTION(atest_usb22),
FUNCTION(uim2_present),
FUNCTION(atest_usb21),
FUNCTION(uim1_data),
FUNCTION(atest_usb20),
FUNCTION(uim1_clk),
FUNCTION(uim1_reset),
FUNCTION(uim1_present),
FUNCTION(mdp_vsync),
FUNCTION(copy_gp),
FUNCTION(tsense_pwm),
FUNCTION(mpm_pwr),
FUNCTION(tgu_ch3),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mdp_vsync4),
FUNCTION(mdp_vsync5),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(atest_char1),
FUNCTION(vfr_1),
FUNCTION(tgu_ch2),
FUNCTION(atest_char0),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(prng_rosc),
FUNCTION(dp_hot),
FUNCTION(debug_hot),
FUNCTION(copy_phase),
FUNCTION(usb_phy),
FUNCTION(atest_char),
FUNCTION(unused1),
FUNCTION(qua_mi2s),
FUNCTION(mss_lte),
FUNCTION(swr_tx),
FUNCTION(aud_sb),
FUNCTION(unused2),
FUNCTION(swr_rx),
FUNCTION(edp_hot),
FUNCTION(audio_ref),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(adsp_ext),
FUNCTION(edp_lcd),
FUNCTION(mclk2),
FUNCTION(m_voc),
FUNCTION(mclk1),
FUNCTION(qca_sb),
FUNCTION(qui_mi2s),
FUNCTION(dmic0_clk),
FUNCTION(sec_mi2s),
FUNCTION(dmic0_data),
FUNCTION(dmic1_clk),
FUNCTION(dmic1_data),
static const struct pinfunction sm6125_functions[] = {
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(qup03),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qup04),
MSM_PIN_FUNCTION(wlan2_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wsa_clk),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(wsa_data),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(copy_gp),
MSM_PIN_FUNCTION(tsense_pwm),
MSM_PIN_FUNCTION(mpm_pwr),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mdp_vsync4),
MSM_PIN_FUNCTION(mdp_vsync5),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(debug_hot),
MSM_PIN_FUNCTION(copy_phase),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(unused1),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(swr_tx),
MSM_PIN_FUNCTION(aud_sb),
MSM_PIN_FUNCTION(unused2),
MSM_PIN_FUNCTION(swr_rx),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(mclk2),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mclk1),
MSM_PIN_FUNCTION(qca_sb),
MSM_PIN_FUNCTION(qui_mi2s),
MSM_PIN_FUNCTION(dmic0_clk),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(dmic0_data),
MSM_PIN_FUNCTION(dmic1_clk),
MSM_PIN_FUNCTION(dmic1_data),
};
/*

296
drivers/pinctrl/qcom/pinctrl-sm6350.c
View File

@ -7,23 +7,15 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -60,9 +52,9 @@
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -85,9 +77,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1016,141 +1008,141 @@ static const char * const usb_phy_groups[] = {
"gpio124",
};
static const struct msm_function sm6350_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb),
FUNCTION(audio_ref),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(cam_mclk2),
FUNCTION(cam_mclk3),
FUNCTION(cam_mclk4),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gpio),
FUNCTION(gps_tx),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_ext),
FUNCTION(m_voc),
FUNCTION(mclk),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s_0),
FUNCTION(mi2s_1),
FUNCTION(mi2s_2),
FUNCTION(mss_lte),
FUNCTION(nav_gpio),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pcie0_clk),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qdss_gpio0),
FUNCTION(qdss_gpio1),
FUNCTION(qdss_gpio10),
FUNCTION(qdss_gpio11),
FUNCTION(qdss_gpio12),
FUNCTION(qdss_gpio13),
FUNCTION(qdss_gpio14),
FUNCTION(qdss_gpio15),
FUNCTION(qdss_gpio2),
FUNCTION(qdss_gpio3),
FUNCTION(qdss_gpio4),
FUNCTION(qdss_gpio5),
FUNCTION(qdss_gpio6),
FUNCTION(qdss_gpio7),
FUNCTION(qdss_gpio8),
FUNCTION(qdss_gpio9),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13_f1),
FUNCTION(qup13_f2),
FUNCTION(qup14),
FUNCTION(rffe0_clk),
FUNCTION(rffe0_data),
FUNCTION(rffe1_clk),
FUNCTION(rffe1_data),
FUNCTION(rffe2_clk),
FUNCTION(rffe2_data),
FUNCTION(rffe3_clk),
FUNCTION(rffe3_data),
FUNCTION(rffe4_clk),
FUNCTION(rffe4_data),
FUNCTION(sd_write),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sp_cmu),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction sm6350_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk0),
MSM_PIN_FUNCTION(cam_mclk1),
MSM_PIN_FUNCTION(cam_mclk2),
MSM_PIN_FUNCTION(cam_mclk3),
MSM_PIN_FUNCTION(cam_mclk4),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_ext),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mclk),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s_0),
MSM_PIN_FUNCTION(mi2s_1),
MSM_PIN_FUNCTION(mi2s_2),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pcie0_clk),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qdss_gpio0),
MSM_PIN_FUNCTION(qdss_gpio1),
MSM_PIN_FUNCTION(qdss_gpio10),
MSM_PIN_FUNCTION(qdss_gpio11),
MSM_PIN_FUNCTION(qdss_gpio12),
MSM_PIN_FUNCTION(qdss_gpio13),
MSM_PIN_FUNCTION(qdss_gpio14),
MSM_PIN_FUNCTION(qdss_gpio15),
MSM_PIN_FUNCTION(qdss_gpio2),
MSM_PIN_FUNCTION(qdss_gpio3),
MSM_PIN_FUNCTION(qdss_gpio4),
MSM_PIN_FUNCTION(qdss_gpio5),
MSM_PIN_FUNCTION(qdss_gpio6),
MSM_PIN_FUNCTION(qdss_gpio7),
MSM_PIN_FUNCTION(qdss_gpio8),
MSM_PIN_FUNCTION(qdss_gpio9),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13_f1),
MSM_PIN_FUNCTION(qup13_f2),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(rffe0_clk),
MSM_PIN_FUNCTION(rffe0_data),
MSM_PIN_FUNCTION(rffe1_clk),
MSM_PIN_FUNCTION(rffe1_data),
MSM_PIN_FUNCTION(rffe2_clk),
MSM_PIN_FUNCTION(rffe2_data),
MSM_PIN_FUNCTION(rffe3_clk),
MSM_PIN_FUNCTION(rffe3_data),
MSM_PIN_FUNCTION(rffe4_clk),
MSM_PIN_FUNCTION(rffe4_data),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
/*

358
drivers/pinctrl/qcom/pinctrl-sm6375.c
View File

@ -7,24 +7,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_BASE 0x100000
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -63,9 +55,9 @@
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -88,9 +80,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1135,172 +1127,172 @@ static const char * const wlan2_adc1_groups[] = {
"gpio93",
};
static const struct msm_function sm6375_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb2),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(audio_ref),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gpio),
FUNCTION(gps_tx),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(lpass_ext),
FUNCTION(m_voc),
FUNCTION(mclk),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s_0),
FUNCTION(mi2s_1),
FUNCTION(mi2s_2),
FUNCTION(mss_lte),
FUNCTION(nav_gpio),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(phase_flag0),
FUNCTION(phase_flag1),
FUNCTION(phase_flag10),
FUNCTION(phase_flag11),
FUNCTION(phase_flag12),
FUNCTION(phase_flag13),
FUNCTION(phase_flag14),
FUNCTION(phase_flag15),
FUNCTION(phase_flag16),
FUNCTION(phase_flag17),
FUNCTION(phase_flag18),
FUNCTION(phase_flag19),
FUNCTION(phase_flag2),
FUNCTION(phase_flag20),
FUNCTION(phase_flag21),
FUNCTION(phase_flag22),
FUNCTION(phase_flag23),
FUNCTION(phase_flag24),
FUNCTION(phase_flag25),
FUNCTION(phase_flag26),
FUNCTION(phase_flag27),
FUNCTION(phase_flag28),
FUNCTION(phase_flag29),
FUNCTION(phase_flag3),
FUNCTION(phase_flag30),
FUNCTION(phase_flag31),
FUNCTION(phase_flag4),
FUNCTION(phase_flag5),
FUNCTION(phase_flag6),
FUNCTION(phase_flag7),
FUNCTION(phase_flag8),
FUNCTION(phase_flag9),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_clk),
FUNCTION(pll_reset),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qdss_gpio0),
FUNCTION(qdss_gpio1),
FUNCTION(qdss_gpio10),
FUNCTION(qdss_gpio11),
FUNCTION(qdss_gpio12),
FUNCTION(qdss_gpio13),
FUNCTION(qdss_gpio14),
FUNCTION(qdss_gpio15),
FUNCTION(qdss_gpio2),
FUNCTION(qdss_gpio3),
FUNCTION(qdss_gpio4),
FUNCTION(qdss_gpio5),
FUNCTION(qdss_gpio6),
FUNCTION(qdss_gpio7),
FUNCTION(qdss_gpio8),
FUNCTION(qdss_gpio9),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup10),
FUNCTION(qup11_f1),
FUNCTION(qup11_f2),
FUNCTION(qup12),
FUNCTION(qup13_f1),
FUNCTION(qup13_f2),
FUNCTION(qup14),
FUNCTION(sd_write),
FUNCTION(sdc1_tb),
FUNCTION(sdc2_tb),
FUNCTION(sp_cmu),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
static const struct pinfunction sm6375_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(lpass_ext),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mclk),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s_0),
MSM_PIN_FUNCTION(mi2s_1),
MSM_PIN_FUNCTION(mi2s_2),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(phase_flag0),
MSM_PIN_FUNCTION(phase_flag1),
MSM_PIN_FUNCTION(phase_flag10),
MSM_PIN_FUNCTION(phase_flag11),
MSM_PIN_FUNCTION(phase_flag12),
MSM_PIN_FUNCTION(phase_flag13),
MSM_PIN_FUNCTION(phase_flag14),
MSM_PIN_FUNCTION(phase_flag15),
MSM_PIN_FUNCTION(phase_flag16),
MSM_PIN_FUNCTION(phase_flag17),
MSM_PIN_FUNCTION(phase_flag18),
MSM_PIN_FUNCTION(phase_flag19),
MSM_PIN_FUNCTION(phase_flag2),
MSM_PIN_FUNCTION(phase_flag20),
MSM_PIN_FUNCTION(phase_flag21),
MSM_PIN_FUNCTION(phase_flag22),
MSM_PIN_FUNCTION(phase_flag23),
MSM_PIN_FUNCTION(phase_flag24),
MSM_PIN_FUNCTION(phase_flag25),
MSM_PIN_FUNCTION(phase_flag26),
MSM_PIN_FUNCTION(phase_flag27),
MSM_PIN_FUNCTION(phase_flag28),
MSM_PIN_FUNCTION(phase_flag29),
MSM_PIN_FUNCTION(phase_flag3),
MSM_PIN_FUNCTION(phase_flag30),
MSM_PIN_FUNCTION(phase_flag31),
MSM_PIN_FUNCTION(phase_flag4),
MSM_PIN_FUNCTION(phase_flag5),
MSM_PIN_FUNCTION(phase_flag6),
MSM_PIN_FUNCTION(phase_flag7),
MSM_PIN_FUNCTION(phase_flag8),
MSM_PIN_FUNCTION(phase_flag9),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qdss_gpio0),
MSM_PIN_FUNCTION(qdss_gpio1),
MSM_PIN_FUNCTION(qdss_gpio10),
MSM_PIN_FUNCTION(qdss_gpio11),
MSM_PIN_FUNCTION(qdss_gpio12),
MSM_PIN_FUNCTION(qdss_gpio13),
MSM_PIN_FUNCTION(qdss_gpio14),
MSM_PIN_FUNCTION(qdss_gpio15),
MSM_PIN_FUNCTION(qdss_gpio2),
MSM_PIN_FUNCTION(qdss_gpio3),
MSM_PIN_FUNCTION(qdss_gpio4),
MSM_PIN_FUNCTION(qdss_gpio5),
MSM_PIN_FUNCTION(qdss_gpio6),
MSM_PIN_FUNCTION(qdss_gpio7),
MSM_PIN_FUNCTION(qdss_gpio8),
MSM_PIN_FUNCTION(qdss_gpio9),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11_f1),
MSM_PIN_FUNCTION(qup11_f2),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13_f1),
MSM_PIN_FUNCTION(qup13_f2),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc1_tb),
MSM_PIN_FUNCTION(sdc2_tb),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
};
/*

247
drivers/pinctrl/qcom/pinctrl-sm7150.c
View File

@ -23,20 +23,13 @@ enum {
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -74,9 +67,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -100,9 +93,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -966,117 +959,117 @@ static const char * const wsa_data_groups[] = {
"gpio50",
};
static const struct msm_function sm7150_functions[] = {
FUNCTION(gpio),
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(aoss_cti),
FUNCTION(atest_char),
FUNCTION(atest_tsens),
FUNCTION(atest_tsens2),
FUNCTION(atest_usb1),
FUNCTION(atest_usb2),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gp_pdm0),
FUNCTION(gp_pdm1),
FUNCTION(gp_pdm2),
FUNCTION(gps_tx),
FUNCTION(jitter_bist),
FUNCTION(ldo_en),
FUNCTION(ldo_update),
FUNCTION(m_voc),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mss_lte),
FUNCTION(nav_pps_in),
FUNCTION(nav_pps_out),
FUNCTION(pa_indicator),
FUNCTION(pci_e),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss),
FUNCTION(qlink_enable),
FUNCTION(qlink_request),
FUNCTION(qua_mi2s),
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup03),
FUNCTION(qup04),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(ter_mi2s),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(tsif2_clk),
FUNCTION(tsif2_data),
FUNCTION(tsif2_en),
FUNCTION(tsif2_error),
FUNCTION(tsif2_sync),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(uim2_clk),
FUNCTION(uim2_data),
FUNCTION(uim2_present),
FUNCTION(uim2_reset),
FUNCTION(uim_batt),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
FUNCTION(wsa_clk),
FUNCTION(wsa_data),
static const struct pinfunction sm7150_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_tsens),
MSM_PIN_FUNCTION(atest_tsens2),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gp_pdm0),
MSM_PIN_FUNCTION(gp_pdm1),
MSM_PIN_FUNCTION(gp_pdm2),
MSM_PIN_FUNCTION(gps_tx),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(ldo_en),
MSM_PIN_FUNCTION(ldo_update),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(nav_pps_in),
MSM_PIN_FUNCTION(nav_pps_out),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(qup00),
MSM_PIN_FUNCTION(qup01),
MSM_PIN_FUNCTION(qup02),
MSM_PIN_FUNCTION(qup03),
MSM_PIN_FUNCTION(qup04),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsif1_clk),
MSM_PIN_FUNCTION(tsif1_data),
MSM_PIN_FUNCTION(tsif1_en),
MSM_PIN_FUNCTION(tsif1_error),
MSM_PIN_FUNCTION(tsif1_sync),
MSM_PIN_FUNCTION(tsif2_clk),
MSM_PIN_FUNCTION(tsif2_data),
MSM_PIN_FUNCTION(tsif2_en),
MSM_PIN_FUNCTION(tsif2_error),
MSM_PIN_FUNCTION(tsif2_sync),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(uim2_clk),
MSM_PIN_FUNCTION(uim2_data),
MSM_PIN_FUNCTION(uim2_present),
MSM_PIN_FUNCTION(uim2_reset),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
MSM_PIN_FUNCTION(wsa_clk),
MSM_PIN_FUNCTION(wsa_data),
};
/*

286
drivers/pinctrl/qcom/pinctrl-sm8150.c
View File

@ -4,7 +4,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -22,18 +21,11 @@ enum {
WEST
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -71,9 +63,9 @@ enum {
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -97,9 +89,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1180,136 +1172,136 @@ static const char * const mss_lte_groups[] = {
"gpio69", "gpio70",
};
static const struct msm_function sm8150_functions[] = {
FUNCTION(adsp_ext),
FUNCTION(agera_pll),
FUNCTION(aoss_cti),
FUNCTION(ddr_pxi2),
FUNCTION(atest_char),
FUNCTION(atest_char0),
FUNCTION(atest_char1),
FUNCTION(atest_char2),
FUNCTION(atest_char3),
FUNCTION(audio_ref),
FUNCTION(atest_usb1),
FUNCTION(atest_usb2),
FUNCTION(atest_usb10),
FUNCTION(atest_usb11),
FUNCTION(atest_usb12),
FUNCTION(atest_usb13),
FUNCTION(atest_usb20),
FUNCTION(atest_usb21),
FUNCTION(atest_usb22),
FUNCTION(atest_usb23),
FUNCTION(btfm_slimbus),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi3),
FUNCTION(edp_hot),
FUNCTION(edp_lcd),
FUNCTION(emac_phy),
FUNCTION(emac_pps),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(hs1_mi2s),
FUNCTION(hs2_mi2s),
FUNCTION(hs3_mi2s),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mss_lte),
FUNCTION(m_voc),
FUNCTION(nav_pps),
FUNCTION(pa_indicator),
FUNCTION(pci_e0),
FUNCTION(phase_flag),
FUNCTION(pll_bypassnl),
FUNCTION(pll_bist),
FUNCTION(pci_e1),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(pri_mi2s_ws),
FUNCTION(prng_rosc),
FUNCTION(qdss),
FUNCTION(qdss_cti),
FUNCTION(qlink_request),
FUNCTION(qlink_enable),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qua_mi2s),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(rgmii),
FUNCTION(sdc4),
FUNCTION(sd_write),
FUNCTION(sec_mi2s),
FUNCTION(spkr_i2s),
FUNCTION(sp_cmu),
FUNCTION(ter_mi2s),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(uim1),
FUNCTION(uim2),
FUNCTION(uim_batt),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
FUNCTION(wlan1_adc0),
FUNCTION(wlan1_adc1),
FUNCTION(wlan2_adc0),
FUNCTION(wlan2_adc1),
FUNCTION(wmss_reset),
static const struct pinfunction sm8150_functions[] = {
MSM_PIN_FUNCTION(adsp_ext),
MSM_PIN_FUNCTION(agera_pll),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_char0),
MSM_PIN_FUNCTION(atest_char1),
MSM_PIN_FUNCTION(atest_char2),
MSM_PIN_FUNCTION(atest_char3),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(atest_usb1),
MSM_PIN_FUNCTION(atest_usb2),
MSM_PIN_FUNCTION(atest_usb10),
MSM_PIN_FUNCTION(atest_usb11),
MSM_PIN_FUNCTION(atest_usb12),
MSM_PIN_FUNCTION(atest_usb13),
MSM_PIN_FUNCTION(atest_usb20),
MSM_PIN_FUNCTION(atest_usb21),
MSM_PIN_FUNCTION(atest_usb22),
MSM_PIN_FUNCTION(atest_usb23),
MSM_PIN_FUNCTION(btfm_slimbus),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(edp_hot),
MSM_PIN_FUNCTION(edp_lcd),
MSM_PIN_FUNCTION(emac_phy),
MSM_PIN_FUNCTION(emac_pps),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(hs1_mi2s),
MSM_PIN_FUNCTION(hs2_mi2s),
MSM_PIN_FUNCTION(hs3_mi2s),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mss_lte),
MSM_PIN_FUNCTION(m_voc),
MSM_PIN_FUNCTION(nav_pps),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(pri_mi2s_ws),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qlink_request),
MSM_PIN_FUNCTION(qlink_enable),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qua_mi2s),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(rgmii),
MSM_PIN_FUNCTION(sdc4),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(spkr_i2s),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(ter_mi2s),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif1),
MSM_PIN_FUNCTION(tsif2),
MSM_PIN_FUNCTION(uim1),
MSM_PIN_FUNCTION(uim2),
MSM_PIN_FUNCTION(uim_batt),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
MSM_PIN_FUNCTION(wlan1_adc0),
MSM_PIN_FUNCTION(wlan1_adc1),
MSM_PIN_FUNCTION(wlan2_adc0),
MSM_PIN_FUNCTION(wlan2_adc1),
MSM_PIN_FUNCTION(wmss_reset),
};
/*

258
drivers/pinctrl/qcom/pinctrl-sm8250.c
View File

@ -6,7 +6,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
@ -22,19 +21,12 @@ enum {
NORTH,
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -72,9 +64,9 @@ enum {
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -98,9 +90,9 @@ enum {
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1003,122 +995,122 @@ static const char * const sdc42_groups[] = {
"gpio74",
};
static const struct msm_function sm8250_functions[] = {
FUNCTION(aoss_cti),
FUNCTION(atest),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer0),
FUNCTION(cci_timer1),
FUNCTION(cci_timer2),
FUNCTION(cci_timer3),
FUNCTION(cci_timer4),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(dp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s0_data0),
FUNCTION(mi2s0_data1),
FUNCTION(mi2s0_sck),
FUNCTION(mi2s0_ws),
FUNCTION(mi2s1_data0),
FUNCTION(mi2s1_data1),
FUNCTION(mi2s1_sck),
FUNCTION(mi2s1_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(pci_e0),
FUNCTION(pci_e1),
FUNCTION(pci_e2),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_bypassnl),
FUNCTION(pll_clk),
FUNCTION(pll_reset),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(sp_cmu),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsif0_clk),
FUNCTION(tsif0_data),
FUNCTION(tsif0_en),
FUNCTION(tsif0_error),
FUNCTION(tsif0_sync),
FUNCTION(tsif1_clk),
FUNCTION(tsif1_data),
FUNCTION(tsif1_en),
FUNCTION(tsif1_error),
FUNCTION(tsif1_sync),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vsense_trigger),
static const struct pinfunction sm8250_functions[] = {
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(atest),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer0),
MSM_PIN_FUNCTION(cci_timer1),
MSM_PIN_FUNCTION(cci_timer2),
MSM_PIN_FUNCTION(cci_timer3),
MSM_PIN_FUNCTION(cci_timer4),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(dp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(pci_e0),
MSM_PIN_FUNCTION(pci_e1),
MSM_PIN_FUNCTION(pci_e2),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_bypassnl),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(pll_reset),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(sp_cmu),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsif0_clk),
MSM_PIN_FUNCTION(tsif0_data),
MSM_PIN_FUNCTION(tsif0_en),
MSM_PIN_FUNCTION(tsif0_error),
MSM_PIN_FUNCTION(tsif0_sync),
MSM_PIN_FUNCTION(tsif1_clk),
MSM_PIN_FUNCTION(tsif1_data),
MSM_PIN_FUNCTION(tsif1_en),
MSM_PIN_FUNCTION(tsif1_error),
MSM_PIN_FUNCTION(tsif1_sync),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

298
drivers/pinctrl/qcom/pinctrl-sm8350.c
View File

@ -7,24 +7,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -61,9 +53,9 @@
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -86,9 +78,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1250,142 +1242,142 @@ static const char * const vsense_trigger_groups[] = {
"gpio78",
};
static const struct msm_function sm8350_functions[] = {
FUNCTION(atest_char),
FUNCTION(atest_usb),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer),
FUNCTION(cmu_rng),
FUNCTION(coex_uart1),
FUNCTION(coex_uart2),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(dp_lcd),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(gpio),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(lpass_slimbus),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s0_data0),
FUNCTION(mi2s0_data1),
FUNCTION(mi2s0_sck),
FUNCTION(mi2s0_ws),
FUNCTION(mi2s1_data0),
FUNCTION(mi2s1_data1),
FUNCTION(mi2s1_sck),
FUNCTION(mi2s1_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(mss_grfc0),
FUNCTION(mss_grfc1),
FUNCTION(mss_grfc10),
FUNCTION(mss_grfc11),
FUNCTION(mss_grfc12),
FUNCTION(mss_grfc2),
FUNCTION(mss_grfc3),
FUNCTION(mss_grfc4),
FUNCTION(mss_grfc5),
FUNCTION(mss_grfc6),
FUNCTION(mss_grfc7),
FUNCTION(mss_grfc8),
FUNCTION(mss_grfc9),
FUNCTION(nav_gpio),
FUNCTION(pa_indicator),
FUNCTION(pcie0_clkreqn),
FUNCTION(pcie1_clkreqn),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_clk),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qlink2_enable),
FUNCTION(qlink2_request),
FUNCTION(qlink2_wmss),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup2),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(tb_trig),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim0_clk),
FUNCTION(uim0_data),
FUNCTION(uim0_present),
FUNCTION(uim0_reset),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vfr_0),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
static const struct pinfunction sm8350_functions[] = {
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer),
MSM_PIN_FUNCTION(cmu_rng),
MSM_PIN_FUNCTION(coex_uart1),
MSM_PIN_FUNCTION(coex_uart2),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(dp_lcd),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(lpass_slimbus),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s1_data0),
MSM_PIN_FUNCTION(mi2s1_data1),
MSM_PIN_FUNCTION(mi2s1_sck),
MSM_PIN_FUNCTION(mi2s1_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(mss_grfc0),
MSM_PIN_FUNCTION(mss_grfc1),
MSM_PIN_FUNCTION(mss_grfc10),
MSM_PIN_FUNCTION(mss_grfc11),
MSM_PIN_FUNCTION(mss_grfc12),
MSM_PIN_FUNCTION(mss_grfc2),
MSM_PIN_FUNCTION(mss_grfc3),
MSM_PIN_FUNCTION(mss_grfc4),
MSM_PIN_FUNCTION(mss_grfc5),
MSM_PIN_FUNCTION(mss_grfc6),
MSM_PIN_FUNCTION(mss_grfc7),
MSM_PIN_FUNCTION(mss_grfc8),
MSM_PIN_FUNCTION(mss_grfc9),
MSM_PIN_FUNCTION(nav_gpio),
MSM_PIN_FUNCTION(pa_indicator),
MSM_PIN_FUNCTION(pcie0_clkreqn),
MSM_PIN_FUNCTION(pcie1_clkreqn),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qlink2_enable),
MSM_PIN_FUNCTION(qlink2_request),
MSM_PIN_FUNCTION(qlink2_wmss),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim0_clk),
MSM_PIN_FUNCTION(uim0_data),
MSM_PIN_FUNCTION(uim0_present),
MSM_PIN_FUNCTION(uim0_reset),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_0),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

300
drivers/pinctrl/qcom/pinctrl-sm8450.c
View File

@ -7,24 +7,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -63,9 +55,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -88,9 +80,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1276,143 +1268,143 @@ static const char * const vsense_trigger_groups[] = {
"gpio18",
};
static const struct msm_function sm8450_functions[] = {
FUNCTION(gpio),
FUNCTION(aon_cam),
FUNCTION(atest_char),
FUNCTION(atest_usb),
FUNCTION(audio_ref),
FUNCTION(cam_mclk),
FUNCTION(cci_async),
FUNCTION(cci_i2c),
FUNCTION(cci_timer),
FUNCTION(cmu_rng),
FUNCTION(coex_uart1),
FUNCTION(coex_uart2),
FUNCTION(cri_trng),
FUNCTION(cri_trng0),
FUNCTION(cri_trng1),
FUNCTION(dbg_out),
FUNCTION(ddr_bist),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(egpio),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0),
FUNCTION(mdp_vsync1),
FUNCTION(mdp_vsync2),
FUNCTION(mdp_vsync3),
FUNCTION(mi2s0_data0),
FUNCTION(mi2s0_data1),
FUNCTION(mi2s0_sck),
FUNCTION(mi2s0_ws),
FUNCTION(mi2s2_data0),
FUNCTION(mi2s2_data1),
FUNCTION(mi2s2_sck),
FUNCTION(mi2s2_ws),
FUNCTION(mss_grfc0),
FUNCTION(mss_grfc1),
FUNCTION(mss_grfc10),
FUNCTION(mss_grfc11),
FUNCTION(mss_grfc12),
FUNCTION(mss_grfc2),
FUNCTION(mss_grfc3),
FUNCTION(mss_grfc4),
FUNCTION(mss_grfc5),
FUNCTION(mss_grfc6),
FUNCTION(mss_grfc7),
FUNCTION(mss_grfc8),
FUNCTION(mss_grfc9),
FUNCTION(nav),
FUNCTION(pcie0_clkreqn),
FUNCTION(pcie1_clkreqn),
FUNCTION(phase_flag),
FUNCTION(pll_bist),
FUNCTION(pll_clk),
FUNCTION(pri_mi2s),
FUNCTION(prng_rosc),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qlink2_enable),
FUNCTION(qlink2_request),
FUNCTION(qlink2_wmss),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup0),
FUNCTION(qup1),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),
FUNCTION(qup16),
FUNCTION(qup17),
FUNCTION(qup18),
FUNCTION(qup19),
FUNCTION(qup2),
FUNCTION(qup20),
FUNCTION(qup21),
FUNCTION(qup3),
FUNCTION(qup4),
FUNCTION(qup5),
FUNCTION(qup6),
FUNCTION(qup7),
FUNCTION(qup8),
FUNCTION(qup9),
FUNCTION(qup_l4),
FUNCTION(qup_l5),
FUNCTION(qup_l6),
FUNCTION(sd_write),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(sec_mi2s),
FUNCTION(tb_trig),
FUNCTION(tgu_ch0),
FUNCTION(tgu_ch1),
FUNCTION(tgu_ch2),
FUNCTION(tgu_ch3),
FUNCTION(tmess_prng0),
FUNCTION(tmess_prng1),
FUNCTION(tmess_prng2),
FUNCTION(tmess_prng3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(uim0_clk),
FUNCTION(uim0_data),
FUNCTION(uim0_present),
FUNCTION(uim0_reset),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(usb2phy_ac),
FUNCTION(usb_phy),
FUNCTION(vfr_0),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger),
static const struct pinfunction sm8450_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(aon_cam),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(audio_ref),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async),
MSM_PIN_FUNCTION(cci_i2c),
MSM_PIN_FUNCTION(cci_timer),
MSM_PIN_FUNCTION(cmu_rng),
MSM_PIN_FUNCTION(coex_uart1),
MSM_PIN_FUNCTION(coex_uart2),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(cri_trng0),
MSM_PIN_FUNCTION(cri_trng1),
MSM_PIN_FUNCTION(dbg_out),
MSM_PIN_FUNCTION(ddr_bist),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(egpio),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0),
MSM_PIN_FUNCTION(mdp_vsync1),
MSM_PIN_FUNCTION(mdp_vsync2),
MSM_PIN_FUNCTION(mdp_vsync3),
MSM_PIN_FUNCTION(mi2s0_data0),
MSM_PIN_FUNCTION(mi2s0_data1),
MSM_PIN_FUNCTION(mi2s0_sck),
MSM_PIN_FUNCTION(mi2s0_ws),
MSM_PIN_FUNCTION(mi2s2_data0),
MSM_PIN_FUNCTION(mi2s2_data1),
MSM_PIN_FUNCTION(mi2s2_sck),
MSM_PIN_FUNCTION(mi2s2_ws),
MSM_PIN_FUNCTION(mss_grfc0),
MSM_PIN_FUNCTION(mss_grfc1),
MSM_PIN_FUNCTION(mss_grfc10),
MSM_PIN_FUNCTION(mss_grfc11),
MSM_PIN_FUNCTION(mss_grfc12),
MSM_PIN_FUNCTION(mss_grfc2),
MSM_PIN_FUNCTION(mss_grfc3),
MSM_PIN_FUNCTION(mss_grfc4),
MSM_PIN_FUNCTION(mss_grfc5),
MSM_PIN_FUNCTION(mss_grfc6),
MSM_PIN_FUNCTION(mss_grfc7),
MSM_PIN_FUNCTION(mss_grfc8),
MSM_PIN_FUNCTION(mss_grfc9),
MSM_PIN_FUNCTION(nav),
MSM_PIN_FUNCTION(pcie0_clkreqn),
MSM_PIN_FUNCTION(pcie1_clkreqn),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist),
MSM_PIN_FUNCTION(pll_clk),
MSM_PIN_FUNCTION(pri_mi2s),
MSM_PIN_FUNCTION(prng_rosc),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qlink2_enable),
MSM_PIN_FUNCTION(qlink2_request),
MSM_PIN_FUNCTION(qlink2_wmss),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup0),
MSM_PIN_FUNCTION(qup1),
MSM_PIN_FUNCTION(qup10),
MSM_PIN_FUNCTION(qup11),
MSM_PIN_FUNCTION(qup12),
MSM_PIN_FUNCTION(qup13),
MSM_PIN_FUNCTION(qup14),
MSM_PIN_FUNCTION(qup15),
MSM_PIN_FUNCTION(qup16),
MSM_PIN_FUNCTION(qup17),
MSM_PIN_FUNCTION(qup18),
MSM_PIN_FUNCTION(qup19),
MSM_PIN_FUNCTION(qup2),
MSM_PIN_FUNCTION(qup20),
MSM_PIN_FUNCTION(qup21),
MSM_PIN_FUNCTION(qup3),
MSM_PIN_FUNCTION(qup4),
MSM_PIN_FUNCTION(qup5),
MSM_PIN_FUNCTION(qup6),
MSM_PIN_FUNCTION(qup7),
MSM_PIN_FUNCTION(qup8),
MSM_PIN_FUNCTION(qup9),
MSM_PIN_FUNCTION(qup_l4),
MSM_PIN_FUNCTION(qup_l5),
MSM_PIN_FUNCTION(qup_l6),
MSM_PIN_FUNCTION(sd_write),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(sec_mi2s),
MSM_PIN_FUNCTION(tb_trig),
MSM_PIN_FUNCTION(tgu_ch0),
MSM_PIN_FUNCTION(tgu_ch1),
MSM_PIN_FUNCTION(tgu_ch2),
MSM_PIN_FUNCTION(tgu_ch3),
MSM_PIN_FUNCTION(tmess_prng0),
MSM_PIN_FUNCTION(tmess_prng1),
MSM_PIN_FUNCTION(tmess_prng2),
MSM_PIN_FUNCTION(tmess_prng3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(uim0_clk),
MSM_PIN_FUNCTION(uim0_data),
MSM_PIN_FUNCTION(uim0_present),
MSM_PIN_FUNCTION(uim0_reset),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb2phy_ac),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_0),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger),
};
/* Every pin is maintained as a single group, and missing or non-existing pin

320
drivers/pinctrl/qcom/pinctrl-sm8550.c
View File

@ -8,24 +8,16 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
.grp = PINCTRL_PINGROUP("gpio" #id, \
gpio##id##_pins, \
ARRAY_SIZE(gpio##id##_pins)), \
.funcs = (int[]){ \
msm_mux_gpio, /* gpio mode */ \
msm_mux_##f1, \
@ -65,9 +57,9 @@
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
@ -90,9 +82,9 @@
#define UFS_RESET(pg_name, offset) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
.grp = PINCTRL_PINGROUP(#pg_name, \
pg_name##_pins, \
ARRAY_SIZE(pg_name##_pins)), \
.ctl_reg = offset, \
.io_reg = offset + 0x4, \
.intr_cfg_reg = 0, \
@ -1347,153 +1339,153 @@ static const char *const vsense_trigger_mirnat_groups[] = {
"gpio24",
};
static const struct msm_function sm8550_functions[] = {
FUNCTION(gpio),
FUNCTION(aon_cci),
FUNCTION(aoss_cti),
FUNCTION(atest_char),
FUNCTION(atest_usb),
FUNCTION(audio_ext_mclk0),
FUNCTION(audio_ext_mclk1),
FUNCTION(audio_ref_clk),
FUNCTION(cam_aon_mclk4),
FUNCTION(cam_mclk),
FUNCTION(cci_async_in),
FUNCTION(cci_i2c_scl),
FUNCTION(cci_i2c_sda),
FUNCTION(cci_timer),
FUNCTION(cmu_rng),
FUNCTION(coex_uart1_rx),
FUNCTION(coex_uart1_tx),
FUNCTION(coex_uart2_rx),
FUNCTION(coex_uart2_tx),
FUNCTION(cri_trng),
FUNCTION(dbg_out_clk),
FUNCTION(ddr_bist_complete),
FUNCTION(ddr_bist_fail),
FUNCTION(ddr_bist_start),
FUNCTION(ddr_bist_stop),
FUNCTION(ddr_pxi0),
FUNCTION(ddr_pxi1),
FUNCTION(ddr_pxi2),
FUNCTION(ddr_pxi3),
FUNCTION(dp_hot),
FUNCTION(gcc_gp1),
FUNCTION(gcc_gp2),
FUNCTION(gcc_gp3),
FUNCTION(i2chub0_se0),
FUNCTION(i2chub0_se1),
FUNCTION(i2chub0_se2),
FUNCTION(i2chub0_se3),
FUNCTION(i2chub0_se4),
FUNCTION(i2chub0_se5),
FUNCTION(i2chub0_se6),
FUNCTION(i2chub0_se7),
FUNCTION(i2chub0_se8),
FUNCTION(i2chub0_se9),
FUNCTION(i2s0_data0),
FUNCTION(i2s0_data1),
FUNCTION(i2s0_sck),
FUNCTION(i2s0_ws),
FUNCTION(i2s1_data0),
FUNCTION(i2s1_data1),
FUNCTION(i2s1_sck),
FUNCTION(i2s1_ws),
FUNCTION(ibi_i3c),
FUNCTION(jitter_bist),
FUNCTION(mdp_vsync),
FUNCTION(mdp_vsync0_out),
FUNCTION(mdp_vsync1_out),
FUNCTION(mdp_vsync2_out),
FUNCTION(mdp_vsync3_out),
FUNCTION(mdp_vsync_e),
FUNCTION(nav_gpio0),
FUNCTION(nav_gpio1),
FUNCTION(nav_gpio2),
FUNCTION(pcie0_clk_req_n),
FUNCTION(pcie1_clk_req_n),
FUNCTION(phase_flag),
FUNCTION(pll_bist_sync),
FUNCTION(pll_clk_aux),
FUNCTION(prng_rosc0),
FUNCTION(prng_rosc1),
FUNCTION(prng_rosc2),
FUNCTION(prng_rosc3),
FUNCTION(qdss_cti),
FUNCTION(qdss_gpio),
FUNCTION(qlink0_enable),
FUNCTION(qlink0_request),
FUNCTION(qlink0_wmss),
FUNCTION(qlink1_enable),
FUNCTION(qlink1_request),
FUNCTION(qlink1_wmss),
FUNCTION(qlink2_enable),
FUNCTION(qlink2_request),
FUNCTION(qlink2_wmss),
FUNCTION(qspi0),
FUNCTION(qspi1),
FUNCTION(qspi2),
FUNCTION(qspi3),
FUNCTION(qspi_clk),
FUNCTION(qspi_cs),
FUNCTION(qup1_se0),
FUNCTION(qup1_se1),
FUNCTION(qup1_se2),
FUNCTION(qup1_se3),
FUNCTION(qup1_se4),
FUNCTION(qup1_se5),
FUNCTION(qup1_se6),
FUNCTION(qup1_se7),
FUNCTION(qup2_se0),
FUNCTION(qup2_se0_l0_mira),
FUNCTION(qup2_se0_l0_mirb),
FUNCTION(qup2_se0_l1_mira),
FUNCTION(qup2_se0_l1_mirb),
FUNCTION(qup2_se0_l2_mira),
FUNCTION(qup2_se0_l2_mirb),
FUNCTION(qup2_se0_l3_mira),
FUNCTION(qup2_se0_l3_mirb),
FUNCTION(qup2_se1),
FUNCTION(qup2_se2),
FUNCTION(qup2_se3),
FUNCTION(qup2_se4),
FUNCTION(qup2_se5),
FUNCTION(qup2_se6),
FUNCTION(qup2_se7),
FUNCTION(resout_n),
FUNCTION(sd_write_protect),
FUNCTION(sdc40),
FUNCTION(sdc41),
FUNCTION(sdc42),
FUNCTION(sdc43),
FUNCTION(sdc4_clk),
FUNCTION(sdc4_cmd),
FUNCTION(tb_trig_sdc2),
FUNCTION(tb_trig_sdc4),
FUNCTION(tgu_ch0_trigout),
FUNCTION(tgu_ch1_trigout),
FUNCTION(tgu_ch2_trigout),
FUNCTION(tgu_ch3_trigout),
FUNCTION(tmess_prng0),
FUNCTION(tmess_prng1),
FUNCTION(tmess_prng2),
FUNCTION(tmess_prng3),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
FUNCTION(tsense_pwm3),
FUNCTION(uim0_clk),
FUNCTION(uim0_data),
FUNCTION(uim0_present),
FUNCTION(uim0_reset),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
FUNCTION(uim1_reset),
FUNCTION(usb1_hs),
FUNCTION(usb_phy),
FUNCTION(vfr_0),
FUNCTION(vfr_1),
FUNCTION(vsense_trigger_mirnat),
static const struct pinfunction sm8550_functions[] = {
MSM_PIN_FUNCTION(gpio),
MSM_PIN_FUNCTION(aon_cci),
MSM_PIN_FUNCTION(aoss_cti),
MSM_PIN_FUNCTION(atest_char),
MSM_PIN_FUNCTION(atest_usb),
MSM_PIN_FUNCTION(audio_ext_mclk0),
MSM_PIN_FUNCTION(audio_ext_mclk1),
MSM_PIN_FUNCTION(audio_ref_clk),
MSM_PIN_FUNCTION(cam_aon_mclk4),
MSM_PIN_FUNCTION(cam_mclk),
MSM_PIN_FUNCTION(cci_async_in),
MSM_PIN_FUNCTION(cci_i2c_scl),
MSM_PIN_FUNCTION(cci_i2c_sda),
MSM_PIN_FUNCTION(cci_timer),
MSM_PIN_FUNCTION(cmu_rng),
MSM_PIN_FUNCTION(coex_uart1_rx),
MSM_PIN_FUNCTION(coex_uart1_tx),
MSM_PIN_FUNCTION(coex_uart2_rx),
MSM_PIN_FUNCTION(coex_uart2_tx),
MSM_PIN_FUNCTION(cri_trng),
MSM_PIN_FUNCTION(dbg_out_clk),
MSM_PIN_FUNCTION(ddr_bist_complete),
MSM_PIN_FUNCTION(ddr_bist_fail),
MSM_PIN_FUNCTION(ddr_bist_start),
MSM_PIN_FUNCTION(ddr_bist_stop),
MSM_PIN_FUNCTION(ddr_pxi0),
MSM_PIN_FUNCTION(ddr_pxi1),
MSM_PIN_FUNCTION(ddr_pxi2),
MSM_PIN_FUNCTION(ddr_pxi3),
MSM_PIN_FUNCTION(dp_hot),
MSM_PIN_FUNCTION(gcc_gp1),
MSM_PIN_FUNCTION(gcc_gp2),
MSM_PIN_FUNCTION(gcc_gp3),
MSM_PIN_FUNCTION(i2chub0_se0),
MSM_PIN_FUNCTION(i2chub0_se1),
MSM_PIN_FUNCTION(i2chub0_se2),
MSM_PIN_FUNCTION(i2chub0_se3),
MSM_PIN_FUNCTION(i2chub0_se4),
MSM_PIN_FUNCTION(i2chub0_se5),
MSM_PIN_FUNCTION(i2chub0_se6),
MSM_PIN_FUNCTION(i2chub0_se7),
MSM_PIN_FUNCTION(i2chub0_se8),
MSM_PIN_FUNCTION(i2chub0_se9),
MSM_PIN_FUNCTION(i2s0_data0),
MSM_PIN_FUNCTION(i2s0_data1),
MSM_PIN_FUNCTION(i2s0_sck),
MSM_PIN_FUNCTION(i2s0_ws),
MSM_PIN_FUNCTION(i2s1_data0),
MSM_PIN_FUNCTION(i2s1_data1),
MSM_PIN_FUNCTION(i2s1_sck),
MSM_PIN_FUNCTION(i2s1_ws),
MSM_PIN_FUNCTION(ibi_i3c),
MSM_PIN_FUNCTION(jitter_bist),
MSM_PIN_FUNCTION(mdp_vsync),
MSM_PIN_FUNCTION(mdp_vsync0_out),
MSM_PIN_FUNCTION(mdp_vsync1_out),
MSM_PIN_FUNCTION(mdp_vsync2_out),
MSM_PIN_FUNCTION(mdp_vsync3_out),
MSM_PIN_FUNCTION(mdp_vsync_e),
MSM_PIN_FUNCTION(nav_gpio0),
MSM_PIN_FUNCTION(nav_gpio1),
MSM_PIN_FUNCTION(nav_gpio2),
MSM_PIN_FUNCTION(pcie0_clk_req_n),
MSM_PIN_FUNCTION(pcie1_clk_req_n),
MSM_PIN_FUNCTION(phase_flag),
MSM_PIN_FUNCTION(pll_bist_sync),
MSM_PIN_FUNCTION(pll_clk_aux),
MSM_PIN_FUNCTION(prng_rosc0),
MSM_PIN_FUNCTION(prng_rosc1),
MSM_PIN_FUNCTION(prng_rosc2),
MSM_PIN_FUNCTION(prng_rosc3),
MSM_PIN_FUNCTION(qdss_cti),
MSM_PIN_FUNCTION(qdss_gpio),
MSM_PIN_FUNCTION(qlink0_enable),
MSM_PIN_FUNCTION(qlink0_request),
MSM_PIN_FUNCTION(qlink0_wmss),
MSM_PIN_FUNCTION(qlink1_enable),
MSM_PIN_FUNCTION(qlink1_request),
MSM_PIN_FUNCTION(qlink1_wmss),
MSM_PIN_FUNCTION(qlink2_enable),
MSM_PIN_FUNCTION(qlink2_request),
MSM_PIN_FUNCTION(qlink2_wmss),
MSM_PIN_FUNCTION(qspi0),
MSM_PIN_FUNCTION(qspi1),
MSM_PIN_FUNCTION(qspi2),
MSM_PIN_FUNCTION(qspi3),
MSM_PIN_FUNCTION(qspi_clk),
MSM_PIN_FUNCTION(qspi_cs),
MSM_PIN_FUNCTION(qup1_se0),
MSM_PIN_FUNCTION(qup1_se1),
MSM_PIN_FUNCTION(qup1_se2),
MSM_PIN_FUNCTION(qup1_se3),
MSM_PIN_FUNCTION(qup1_se4),
MSM_PIN_FUNCTION(qup1_se5),
MSM_PIN_FUNCTION(qup1_se6),
MSM_PIN_FUNCTION(qup1_se7),
MSM_PIN_FUNCTION(qup2_se0),
MSM_PIN_FUNCTION(qup2_se0_l0_mira),
MSM_PIN_FUNCTION(qup2_se0_l0_mirb),
MSM_PIN_FUNCTION(qup2_se0_l1_mira),
MSM_PIN_FUNCTION(qup2_se0_l1_mirb),
MSM_PIN_FUNCTION(qup2_se0_l2_mira),
MSM_PIN_FUNCTION(qup2_se0_l2_mirb),
MSM_PIN_FUNCTION(qup2_se0_l3_mira),
MSM_PIN_FUNCTION(qup2_se0_l3_mirb),
MSM_PIN_FUNCTION(qup2_se1),
MSM_PIN_FUNCTION(qup2_se2),
MSM_PIN_FUNCTION(qup2_se3),
MSM_PIN_FUNCTION(qup2_se4),
MSM_PIN_FUNCTION(qup2_se5),
MSM_PIN_FUNCTION(qup2_se6),
MSM_PIN_FUNCTION(qup2_se7),
MSM_PIN_FUNCTION(resout_n),
MSM_PIN_FUNCTION(sd_write_protect),
MSM_PIN_FUNCTION(sdc40),
MSM_PIN_FUNCTION(sdc41),
MSM_PIN_FUNCTION(sdc42),
MSM_PIN_FUNCTION(sdc43),
MSM_PIN_FUNCTION(sdc4_clk),
MSM_PIN_FUNCTION(sdc4_cmd),
MSM_PIN_FUNCTION(tb_trig_sdc2),
MSM_PIN_FUNCTION(tb_trig_sdc4),
MSM_PIN_FUNCTION(tgu_ch0_trigout),
MSM_PIN_FUNCTION(tgu_ch1_trigout),
MSM_PIN_FUNCTION(tgu_ch2_trigout),
MSM_PIN_FUNCTION(tgu_ch3_trigout),
MSM_PIN_FUNCTION(tmess_prng0),
MSM_PIN_FUNCTION(tmess_prng1),
MSM_PIN_FUNCTION(tmess_prng2),
MSM_PIN_FUNCTION(tmess_prng3),
MSM_PIN_FUNCTION(tsense_pwm1),
MSM_PIN_FUNCTION(tsense_pwm2),
MSM_PIN_FUNCTION(tsense_pwm3),
MSM_PIN_FUNCTION(uim0_clk),
MSM_PIN_FUNCTION(uim0_data),
MSM_PIN_FUNCTION(uim0_present),
MSM_PIN_FUNCTION(uim0_reset),
MSM_PIN_FUNCTION(uim1_clk),
MSM_PIN_FUNCTION(uim1_data),
MSM_PIN_FUNCTION(uim1_present),
MSM_PIN_FUNCTION(uim1_reset),
MSM_PIN_FUNCTION(usb1_hs),
MSM_PIN_FUNCTION(usb_phy),
MSM_PIN_FUNCTION(vfr_0),
MSM_PIN_FUNCTION(vfr_1),
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
};
/*

2
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1229,6 +1229,8 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
/* pm8950 has 8 GPIOs with holes on 3 */
{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
/* pm8953 has 8 GPIOs with holes on 3 and 6 */
{ .compatible = "qcom,pm8953-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },

2
drivers/pinctrl/renesas/pfc-r8a77970.c
View File

@ -171,7 +171,7 @@
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

6
drivers/pinctrl/renesas/pfc-r8a77980.c
View File

@ -99,7 +99,7 @@
#define GPSR1_0 F_(IRQ0, IP2_27_24)
/* GPSR2 */
#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
#define GPSR2_26 F_(SDA3, IP10_7_4)
@ -264,11 +264,11 @@
#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

1
drivers/pinctrl/spear/pinctrl-spear.c
View File

@ -18,7 +18,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>

23
drivers/pinctrl/sunplus/sppctl.c
View File

@ -834,11 +834,6 @@ static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node
int i, size = 0;
list = of_get_property(np_config, "sunplus,pins", &size);
if (nmG <= 0)
nmG = 0;
parent = of_get_parent(np_config);
*num_maps = size / sizeof(*list);
/*
@ -866,10 +861,14 @@ static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node
}
}
if (nmG <= 0)
nmG = 0;
*map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL);
if (*map == NULL)
if (!(*map))
return -ENOMEM;
parent = of_get_parent(np_config);
for (i = 0; i < (*num_maps); i++) {
dt_pin = be32_to_cpu(list[i]);
pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
@ -883,6 +882,8 @@ static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node
(*map)[i].data.configs.num_configs = 1;
(*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
configs = kmalloc(sizeof(*configs), GFP_KERNEL);
if (!configs)
goto sppctl_map_err;
*configs = FIELD_GET(GENMASK(7, 0), dt_pin);
(*map)[i].data.configs.configs = configs;
@ -896,6 +897,8 @@ static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node
(*map)[i].data.configs.num_configs = 1;
(*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
configs = kmalloc(sizeof(*configs), GFP_KERNEL);
if (!configs)
goto sppctl_map_err;
*configs = SPPCTL_IOP_CONFIGS;
(*map)[i].data.configs.configs = configs;
@ -965,6 +968,14 @@ static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node
of_node_put(parent);
dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps);
return 0;
sppctl_map_err:
for (i = 0; i < (*num_maps); i++)
if ((*map)[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree((*map)[i].data.configs.configs);
kfree(*map);
of_node_put(parent);
return -ENOMEM;
}
static const struct pinctrl_ops sppctl_pctl_ops = {

4
drivers/pinctrl/tegra/Kconfig
View File

@ -28,6 +28,10 @@ config PINCTRL_TEGRA194
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA234
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA_XUSB
def_bool y if ARCH_TEGRA
select GENERIC_PHY

1
drivers/pinctrl/tegra/Makefile
View File

@ -6,4 +6,5 @@ obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o
obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o
obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o

30
drivers/pinctrl/tegra/pinctrl-tegra.c
View File

@ -232,7 +232,7 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->soc->functions[function].name;
return pmx->functions[function].name;
}
static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
@ -242,8 +242,8 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
*groups = pmx->soc->functions[function].groups;
*num_groups = pmx->soc->functions[function].ngroups;
*groups = pmx->functions[function].groups;
*num_groups = pmx->functions[function].ngroups;
return 0;
}
@ -789,20 +789,26 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
* Each mux group will appear in 4 functions' list of groups.
* This over-allocates slightly, since not all groups are mux groups.
*/
pmx->group_pins = devm_kcalloc(&pdev->dev,
soc_data->ngroups * 4, sizeof(*pmx->group_pins),
GFP_KERNEL);
pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,
sizeof(*pmx->group_pins), GFP_KERNEL);
if (!pmx->group_pins)
return -ENOMEM;
group_pins = pmx->group_pins;
for (fn = 0; fn < soc_data->nfunctions; fn++) {
struct tegra_function *func = &soc_data->functions[fn];
pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,
sizeof(*pmx->functions), GFP_KERNEL);
if (!pmx->functions)
return -ENOMEM;
group_pins = pmx->group_pins;
for (fn = 0; fn < pmx->soc->nfunctions; fn++) {
struct tegra_function *func = &pmx->functions[fn];
func->name = pmx->soc->functions[fn];
func->groups = group_pins;
for (gn = 0; gn < soc_data->ngroups; gn++) {
const struct tegra_pingroup *g = &soc_data->groups[gn];
for (gn = 0; gn < pmx->soc->ngroups; gn++) {
const struct tegra_pingroup *g = &pmx->soc->groups[gn];
if (g->mux_reg == -1)
continue;
@ -814,7 +820,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
continue;
BUG_ON(group_pins - pmx->group_pins >=
soc_data->ngroups * 4);
pmx->soc->ngroups * 4);
*group_pins++ = g->name;
func->ngroups++;
}

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