dt-bindings: net: fsl: enetc: Add bindings for the central MDIO PCIe endpoint
The on-chip PCIe root complex that integrates the ENETC ethernet controllers also integrates a PCIe endpoint for the MDIO controller providing for centralized control of the ENETC mdio bus. Add bindings for this "central" MDIO Integrated PCIe Endpoint. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -11,7 +11,9 @@ Required properties:
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to parent node bindings.
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- compatible : Should be "fsl,enetc".
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1) The ENETC external port is connected to a MDIO configurable phy:
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1. The ENETC external port is connected to a MDIO configurable phy
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1.1. Using the local ENETC Port MDIO interface
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In this case, the ENETC node should include a "mdio" sub-node
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that in turn should contain the "ethernet-phy" node describing the
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@ -47,8 +49,42 @@ Example:
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};
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};
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2) The ENETC port is an internal port or has a fixed-link external
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connection:
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1.2. Using the central MDIO PCIe endpoint device
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In this case, the mdio node should be defined as another PCIe
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endpoint node, at the same level with the ENETC port nodes.
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Required properties:
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- reg : Specifies PCIe Device Number and Function
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Number of the ENETC endpoint device, according
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to parent node bindings.
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- compatible : Should be "fsl,enetc-mdio".
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The remaining required mdio bus properties are standard, their bindings
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already defined in Documentation/devicetree/bindings/net/mdio.txt.
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Example:
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ethernet@0,0 {
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compatible = "fsl,enetc";
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reg = <0x000000 0 0 0 0>;
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phy-handle = <&sgmii_phy0>;
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phy-connection-type = "sgmii";
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};
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mdio@0,3 {
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compatible = "fsl,enetc-mdio";
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reg = <0x000300 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy0: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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2. The ENETC port is an internal port or has a fixed-link external
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connection
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In this case, the ENETC port node defines a fixed link connection,
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as specified by Documentation/devicetree/bindings/net/fixed-link.txt.
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