dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20230223042133.26551-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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@ -178,7 +178,8 @@
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#define IOCLK_AUDIOCDCLK5 58
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#define IOCLK_AUDIOCDCLK6 59
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#define TICK_USB 60
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#define AUD_NR_CLK 61
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#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
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#define AUD_NR_CLK 62
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/* CMU_CMGP */
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#define CLK_RCO_CMGP 1
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@ -227,7 +228,10 @@
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#define CLK_GOUT_MMC_CARD_ACLK 11
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#define CLK_GOUT_MMC_CARD_SDCLKIN 12
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#define CLK_GOUT_SYSREG_HSI_PCLK 13
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#define HSI_NR_CLK 14
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#define CLK_GOUT_HSI_PPMU_ACLK 14
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#define CLK_GOUT_HSI_PPMU_PCLK 15
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#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
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#define HSI_NR_CLK 17
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/* CMU_IS */
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#define CLK_MOUT_IS_BUS_USER 1
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