AT91 DT for v5.20 #4
It contains one new LAN966 based board, namely pcb8309, a cleanup on Makefile to sort alphabetically LAN966 entries and 2 cleanups on bindings. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYuDqzgAKCRCejrg/N2X7 /WPFAP4z2YlG5d+5leV6FWkrTMAOzQdSIJCn1dD8zVzvu0bPNQEA5KdCUBmu7fVR jhxhVeu0LKfPnN6g/7BmguSGpwTyqws= =Ldrk -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLhQeIACgkQmmx57+YA GNkyeRAAwfPJwRH7mcxySV14u6JJdbt5FjlFbUuDy8NUckBBXEtuXJYEWXN5cBs3 rajAF43GKBYTTqIqJzsY2DsWdJ2IKxTDosDZ/byIi071toAQHDXS59gBjFuMVNZk QhdNyQ4Qayf9N0Q+dPBN9wIA2Fe5Cn/8Y1Xi+cJ9OpWT6FaT+nyOJ8lin1iMsuW5 anrE71tKwQHbIzwJ0QKoKvBxEimMA3TPK8PuBtOiIlkrYKr3BONtUk7WxG+zWKXd wTIz/ZGXEb0HuD6aVIWvCK0umLZIx+jHhmkRkXpAyIJKx2I/vHa4tsF/rUU1Bn2z CjuNZ71faZ+dijLzcLSPw1b3dMUK228FTcIVKl+K6Uf2Ds6BcH8Qv2FBrA+UYodT 8qieWcy27MIqacFzbYDMd4rhflEOibEY7pvNiFCvLjzcgSiae2WhUA0bmF7G1/qw 2MNDI/qYjSL5M7h8YhMflZySFh8pDRcEP/sl0+HcyKNGvKHpt7Y4PU9r+enEqe6n 00VT5tpImh9afGawKcVmTwCSNKtnEcywx+r3jWTVlvlVdOjHJS1NyqJ8Y/bNUlvV At+57wJt/OlfTrqFMQ9IbGWKV4m7bJZiWFTuWYgrexpw8ovMh8LzPrkOWbm+iFhr cLfT4Txr3C7o5imkQSZ7Ie8mnBzlL3eQkSlBOMWX56hYanZMzZw= =NBpd -----END PGP SIGNATURE----- Merge tag 'at91-dt-5.20-4' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 DT for v5.20 #4 It contains one new LAN966 based board, namely pcb8309, a cleanup on Makefile to sort alphabetically LAN966 entries and 2 cleanups on bindings. * tag 'at91-dt-5.20-4' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: dt-bindings: soc: microchip: use absolute path to other schema dt-bindings: soc: microchip: drop quotes when not needed ARM: dts: lan966x: keep lan966 entries alphabetically sorted ARM: dts: lan966x: add support for pcb8309 dt-bindings: arm: at91: add lan966 pcb8309 board Link: https://lore.kernel.org/r/20220727075749.2445000-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
28188546df
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@ -163,9 +163,11 @@ properties:
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- const: microchip,sama7g5
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- const: microchip,sama7
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- description: Microchip LAN9662 PCB8291 Evaluation Board.
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- description: Microchip LAN9662 Evaluation Boards.
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items:
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- const: microchip,lan9662-pcb8291
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- enum:
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- microchip,lan9662-pcb8291
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- microchip,lan9662-pcb8309
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- const: microchip,lan9662
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- const: microchip,lan966
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel Timer Counter Block
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@ -75,7 +75,7 @@ patternProperties:
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"^pwm@[0-2]$":
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description: The timer block channels that are used as PWMs.
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$ref: ../../pwm/pwm.yaml#
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$ref: /schemas/pwm/pwm.yaml#
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type: object
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properties:
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compatible:
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@ -1,8 +1,8 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
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@ -784,9 +784,10 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
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dtb-$(CONFIG_SOC_IMXRT) += \
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imxrt1050-evk.dtb
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dtb-$(CONFIG_SOC_LAN966) += \
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lan966x-pcb8291.dtb \
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lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
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lan966x-kontron-kswitch-d10-mmt-8g.dtb
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lan966x-kontron-kswitch-d10-mmt-8g.dtb \
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lan966x-pcb8291.dtb \
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lan966x-pcb8309.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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ls1021a-iot.dtb \
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ls1021a-moxa-uc-8410a.dtb \
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@ -0,0 +1,184 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x_pcb8309.dts - Device Tree file for PCB8309
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*/
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/dts-v1/;
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#include "lan966x.dtsi"
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#include "dt-bindings/phy/phy-lan966x-serdes.h"
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/ {
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model = "Microchip EVB - LAN9662";
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compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
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aliases {
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serial0 = &usart3;
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i2c102 = &i2c102;
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i2c103 = &i2c103;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
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priority = <200>;
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};
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i2c-mux {
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compatible = "i2c-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mux-controls = <&mux>;
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i2c-parent = <&i2c4>;
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i2c102: i2c-sfp@1 {
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reg = <1>;
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};
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i2c103: i2c-sfp@2 {
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reg = <2>;
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};
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};
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mux: mux-controller {
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compatible = "gpio-mux";
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#mux-control-cells = <0>;
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mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */
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<&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */
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};
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sfp2: sfp2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c102>;
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tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>;
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los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
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};
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sfp3: sfp3 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c103>;
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tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>;
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los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>;
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};
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};
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&flx3 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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status = "okay";
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usart3: serial@200 {
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pinctrl-0 = <&fc3_b_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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};
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&flx4 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
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status = "okay";
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i2c4: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&nic_clk>;
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pinctrl-0 = <&fc4_b_pins>;
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pinctrl-names = "default";
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i2c-analog-filter;
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i2c-digital-filter;
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i2c-digital-filter-width-ns = <35>;
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i2c-sda-hold-time-ns = <1500>;
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status = "okay";
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};
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};
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&gpio {
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fc3_b_pins: fc3-b-pins {
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/* RXD, TXD */
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pins = "GPIO_52", "GPIO_53";
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function = "fc3_b";
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};
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fc4_b_pins: fc4-b-pins {
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/* SCL, SDA */
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pins = "GPIO_57", "GPIO_58";
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function = "fc4_b";
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};
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sgpio_a_pins: sgpio-a-pins {
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/* SCK, D0, D1, LD */
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pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
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function = "sgpio_a";
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};
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};
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&mdio1 {
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status = "okay";
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};
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&phy0 {
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status = "okay";
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};
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&phy1 {
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status = "okay";
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};
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&port0 {
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phy-handle = <&phy0>;
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phy-mode = "gmii";
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phys = <&serdes 0 CU(0)>;
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status = "okay";
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};
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&port1 {
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phy-handle = <&phy1>;
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phy-mode = "gmii";
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phys = <&serdes 1 CU(1)>;
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status = "okay";
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};
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&port2 {
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sfp = <&sfp2>;
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managed = "in-band-status";
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phy-mode = "sgmii";
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phys = <&serdes 2 SERDES6G(0)>;
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status = "okay";
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};
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&port3 {
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sfp = <&sfp3>;
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managed = "in-band-status";
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phy-mode = "sgmii";
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phys = <&serdes 3 SERDES6G(1)>;
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status = "okay";
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};
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&serdes {
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status = "okay";
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};
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&sgpio {
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pinctrl-0 = <&sgpio_a_pins>;
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pinctrl-names = "default";
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microchip,sgpio-port-ranges = <0 3>, <8 11>;
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status = "okay";
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gpio@0 {
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ngpios = <64>;
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};
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gpio@1 {
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ngpios = <64>;
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};
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};
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&switch {
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status = "okay";
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};
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