drm/i915: Reserve space in the global seqno during request allocation
A restriction on our global seqno is that they cannot wrap, and that we cannot use the value 0. This allows us to detect when a request has not yet been submitted, its global seqno is still 0, and ensures that hardware semaphores are monotonic as required by older hardware. To meet these restrictions when we defer the assignment of the global seqno, we must check that we have an available slot in the global seqno space during request construction. If that test fails, we wait for all requests to be completed and reset the hardware back to 0. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161028125858.23563-33-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
f6168e3304
commit
28176ef4cf
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@ -552,7 +552,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
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seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
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engine->name,
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i915_gem_request_get_seqno(work->flip_queued_req),
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dev_priv->gt.global_timeline.next_seqno,
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atomic_read(&dev_priv->gt.global_timeline.next_seqno),
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intel_engine_get_seqno(engine),
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i915_gem_request_completed(work->flip_queued_req));
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} else
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@ -1046,7 +1046,7 @@ i915_next_seqno_get(void *data, u64 *val)
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{
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struct drm_i915_private *dev_priv = data;
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*val = READ_ONCE(dev_priv->gt.global_timeline.next_seqno);
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*val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
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return 0;
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}
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@ -2277,8 +2277,8 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
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struct drm_file *file;
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seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
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seq_printf(m, "GPU busy? %s [%x]\n",
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yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
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seq_printf(m, "GPU busy? %s [%d requests]\n",
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yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
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seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
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seq_printf(m, "Frequency requested %d\n",
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intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
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@ -2313,7 +2313,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
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if (INTEL_GEN(dev_priv) >= 6 &&
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dev_priv->rps.enabled &&
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dev_priv->gt.active_engines) {
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dev_priv->gt.active_requests) {
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u32 rpup, rpupei;
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u32 rpdown, rpdownei;
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@ -2092,6 +2092,7 @@ struct drm_i915_private {
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struct list_head timelines;
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struct i915_gem_timeline global_timeline;
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u32 active_requests;
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/**
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* Is the GPU currently considered idle, or busy executing
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@ -2100,7 +2101,6 @@ struct drm_i915_private {
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* In order to reduce the effect on performance, there
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* is a slight delay before we do so.
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*/
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unsigned int active_engines;
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bool awake;
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/**
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@ -2688,8 +2688,6 @@ static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
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memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
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spin_unlock(&engine->execlist_lock);
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}
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engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
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}
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void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
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@ -2746,7 +2744,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
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if (!READ_ONCE(dev_priv->gt.awake))
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return;
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if (READ_ONCE(dev_priv->gt.active_engines))
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if (READ_ONCE(dev_priv->gt.active_requests))
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return;
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rearm_hangcheck =
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@ -2760,7 +2758,7 @@ i915_gem_idle_work_handler(struct work_struct *work)
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goto out_rearm;
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}
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if (dev_priv->gt.active_engines)
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if (dev_priv->gt.active_requests)
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goto out_unlock;
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for_each_engine(engine, dev_priv, id)
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@ -4399,6 +4397,7 @@ int i915_gem_suspend(struct drm_device *dev)
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goto err;
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i915_gem_retire_requests(dev_priv);
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GEM_BUG_ON(dev_priv->gt.active_requests);
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assert_kernel_context_is_current(dev_priv);
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i915_gem_context_lost(dev_priv);
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@ -159,6 +159,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
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*/
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list_del(&request->ring_link);
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request->ring->last_retired_head = request->postfix;
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request->i915->gt.active_requests--;
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/* Walk through the active list, calling retire on each. This allows
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* objects to track their GPU activity and mark themselves as idle
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@ -253,13 +254,15 @@ static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
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return ret;
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i915_gem_retire_requests(i915);
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GEM_BUG_ON(i915->gt.active_requests > 1);
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/* If the seqno wraps around, we need to clear the breadcrumb rbtree */
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if (!i915_seqno_passed(seqno, timeline->next_seqno)) {
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if (!i915_seqno_passed(seqno, atomic_read(&timeline->next_seqno))) {
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while (intel_kick_waiters(i915) || intel_kick_signalers(i915))
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yield();
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yield();
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}
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atomic_set(&timeline->next_seqno, seqno);
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/* Finally reset hw state */
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for_each_engine(engine, i915, id)
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@ -279,7 +282,6 @@ static int i915_gem_init_global_seqno(struct drm_i915_private *i915, u32 seqno)
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int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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int ret;
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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@ -289,32 +291,31 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
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/* HWS page needs to be set less than what we
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* will inject to ring
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*/
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ret = i915_gem_init_global_seqno(dev_priv, seqno - 1);
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if (ret)
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return ret;
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return i915_gem_init_global_seqno(dev_priv, seqno - 1);
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}
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static int reserve_global_seqno(struct drm_i915_private *i915)
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{
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u32 active_requests = ++i915->gt.active_requests;
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u32 next_seqno = atomic_read(&i915->gt.global_timeline.next_seqno);
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int ret;
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/* Reservation is fine until we need to wrap around */
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if (likely(next_seqno + active_requests > next_seqno))
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return 0;
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ret = i915_gem_init_global_seqno(i915, 0);
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if (ret) {
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i915->gt.active_requests--;
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return ret;
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}
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dev_priv->gt.global_timeline.next_seqno = seqno;
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return 0;
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}
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static int i915_gem_get_global_seqno(struct drm_i915_private *dev_priv,
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u32 *seqno)
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static u32 timeline_get_seqno(struct i915_gem_timeline *tl)
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{
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struct i915_gem_timeline *tl = &dev_priv->gt.global_timeline;
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/* reserve 0 for non-seqno */
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if (unlikely(tl->next_seqno == 0)) {
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int ret;
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ret = i915_gem_init_global_seqno(dev_priv, 0);
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if (ret)
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return ret;
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tl->next_seqno = 1;
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}
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*seqno = tl->next_seqno++;
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return 0;
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return atomic_inc_return(&tl->next_seqno);
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}
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static int __i915_sw_fence_call
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@ -356,9 +357,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_gem_request *req;
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u32 seqno;
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int ret;
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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/* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
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* EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
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* and restart.
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@ -367,6 +369,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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if (ret)
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return ERR_PTR(ret);
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ret = reserve_global_seqno(dev_priv);
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if (ret)
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return ERR_PTR(ret);
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/* Move the oldest request to the slab-cache (if not in use!) */
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req = list_first_entry_or_null(&engine->timeline->requests,
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typeof(*req), link);
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@ -402,12 +408,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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* Do not use kmem_cache_zalloc() here!
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*/
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req = kmem_cache_alloc(dev_priv->requests, GFP_KERNEL);
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if (!req)
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return ERR_PTR(-ENOMEM);
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ret = i915_gem_get_global_seqno(dev_priv, &seqno);
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if (ret)
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goto err;
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if (!req) {
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ret = -ENOMEM;
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goto err_unreserve;
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}
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req->timeline = engine->timeline;
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@ -416,14 +420,14 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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&i915_fence_ops,
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&req->lock,
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req->timeline->fence_context,
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seqno);
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timeline_get_seqno(req->timeline->common));
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i915_sw_fence_init(&req->submit, submit_notify);
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INIT_LIST_HEAD(&req->active_list);
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req->i915 = dev_priv;
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req->engine = engine;
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req->global_seqno = seqno;
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req->global_seqno = req->fence.seqno;
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req->ctx = i915_gem_context_get(ctx);
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/* No zalloc, must clear what we need by hand */
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@ -459,8 +463,9 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
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err_ctx:
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i915_gem_context_put(ctx);
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err:
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kmem_cache_free(dev_priv->requests, req);
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err_unreserve:
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dev_priv->gt.active_requests--;
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return ERR_PTR(ret);
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}
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@ -624,7 +629,6 @@ static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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dev_priv->gt.active_engines |= intel_engine_flag(engine);
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if (dev_priv->gt.awake)
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return;
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@ -700,6 +704,9 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
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i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
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&request->submitq);
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GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno,
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request->fence.seqno));
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request->emitted_jiffies = jiffies;
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request->previous_seqno = timeline->last_pending_seqno;
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timeline->last_pending_seqno = request->fence.seqno;
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@ -962,38 +969,35 @@ complete:
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return timeout;
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}
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static bool engine_retire_requests(struct intel_engine_cs *engine)
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static void engine_retire_requests(struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_request *request, *next;
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list_for_each_entry_safe(request, next,
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&engine->timeline->requests, link) {
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if (!i915_gem_request_completed(request))
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return false;
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return;
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i915_gem_request_retire(request);
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}
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return true;
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}
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void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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unsigned int tmp;
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enum intel_engine_id id;
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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if (dev_priv->gt.active_engines == 0)
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if (!dev_priv->gt.active_requests)
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return;
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GEM_BUG_ON(!dev_priv->gt.awake);
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for_each_engine_masked(engine, dev_priv, dev_priv->gt.active_engines, tmp)
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if (engine_retire_requests(engine))
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dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
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for_each_engine(engine, dev_priv, id)
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engine_retire_requests(engine);
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if (dev_priv->gt.active_engines == 0)
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if (!dev_priv->gt.active_requests)
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queue_delayed_work(dev_priv->wq,
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&dev_priv->gt.idle_work,
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msecs_to_jiffies(100));
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@ -55,7 +55,7 @@ struct intel_timeline {
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struct i915_gem_timeline {
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struct list_head link;
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u32 next_seqno;
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atomic_t next_seqno;
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struct drm_i915_private *i915;
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const char *name;
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