gpio: pl061: rename variable from chip to pl061
Rename the local variable "chip" referring to the struct pl061 state container to "pl061": we already have gpio_chip and irq_chip in the driver, we are needlessly adding yet another "chip" to the confusion. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
538f76c566
commit
2796325ffa
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@ -64,22 +64,22 @@ struct pl061 {
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static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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return !(readb(chip->base + GPIODIR) & BIT(offset));
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return !(readb(pl061->base + GPIODIR) & BIT(offset));
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}
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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unsigned long flags;
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unsigned char gpiodir;
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spin_lock_irqsave(&chip->lock, flags);
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gpiodir = readb(chip->base + GPIODIR);
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spin_lock_irqsave(&pl061->lock, flags);
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir &= ~(BIT(offset));
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writeb(gpiodir, chip->base + GPIODIR);
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spin_unlock_irqrestore(&chip->lock, flags);
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writeb(gpiodir, pl061->base + GPIODIR);
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spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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}
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@ -87,44 +87,44 @@ static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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unsigned long flags;
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unsigned char gpiodir;
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spin_lock_irqsave(&chip->lock, flags);
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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gpiodir = readb(chip->base + GPIODIR);
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spin_lock_irqsave(&pl061->lock, flags);
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir |= BIT(offset);
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writeb(gpiodir, chip->base + GPIODIR);
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writeb(gpiodir, pl061->base + GPIODIR);
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/*
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* gpio value is set again, because pl061 doesn't allow to set value of
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* a gpio pin before configuring it in OUT mode.
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*/
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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spin_unlock_irqrestore(&chip->lock, flags);
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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}
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static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
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{
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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return !!readb(chip->base + (BIT(offset + 2)));
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return !!readb(pl061->base + (BIT(offset + 2)));
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}
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static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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writeb(!!value << offset, chip->base + (BIT(offset + 2)));
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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}
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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int offset = irqd_to_hwirq(d);
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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@ -144,11 +144,11 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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}
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spin_lock_irqsave(&chip->lock, flags);
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spin_lock_irqsave(&pl061->lock, flags);
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gpioiev = readb(chip->base + GPIOIEV);
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gpiois = readb(chip->base + GPIOIS);
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gpioibe = readb(chip->base + GPIOIBE);
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gpioiev = readb(pl061->base + GPIOIEV);
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gpiois = readb(pl061->base + GPIOIS);
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gpioibe = readb(pl061->base + GPIOIBE);
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
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@ -200,11 +200,11 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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offset);
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}
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writeb(gpiois, chip->base + GPIOIS);
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writeb(gpioibe, chip->base + GPIOIBE);
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writeb(gpioiev, chip->base + GPIOIEV);
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writeb(gpiois, pl061->base + GPIOIS);
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writeb(gpioibe, pl061->base + GPIOIBE);
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writeb(gpioiev, pl061->base + GPIOIEV);
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spin_unlock_irqrestore(&chip->lock, flags);
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spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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}
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@ -214,12 +214,12 @@ static void pl061_irq_handler(struct irq_desc *desc)
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unsigned long pending;
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int offset;
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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chained_irq_enter(irqchip, desc);
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pending = readb(chip->base + GPIOMIS);
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pending = readb(pl061->base + GPIOMIS);
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if (pending) {
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for_each_set_bit(offset, &pending, PL061_GPIO_NR)
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generic_handle_irq(irq_find_mapping(gc->irqdomain,
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@ -232,27 +232,27 @@ static void pl061_irq_handler(struct irq_desc *desc)
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static void pl061_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) & ~mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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spin_lock(&pl061->lock);
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gpioie = readb(pl061->base + GPIOIE) & ~mask;
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writeb(gpioie, pl061->base + GPIOIE);
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spin_unlock(&pl061->lock);
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}
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static void pl061_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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spin_lock(&chip->lock);
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gpioie = readb(chip->base + GPIOIE) | mask;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock(&chip->lock);
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spin_lock(&pl061->lock);
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gpioie = readb(pl061->base + GPIOIE) | mask;
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writeb(gpioie, pl061->base + GPIOIE);
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spin_unlock(&pl061->lock);
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}
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/**
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@ -266,20 +266,20 @@ static void pl061_irq_unmask(struct irq_data *d)
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static void pl061_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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spin_lock(&chip->lock);
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writeb(mask, chip->base + GPIOIC);
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spin_unlock(&chip->lock);
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spin_lock(&pl061->lock);
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writeb(mask, pl061->base + GPIOIC);
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spin_unlock(&pl061->lock);
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}
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static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct pl061 *chip = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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return irq_set_irq_wake(chip->parent_irq, state);
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return irq_set_irq_wake(pl061->parent_irq, state);
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}
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static struct irq_chip pl061_irqchip = {
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@ -295,81 +295,81 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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{
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struct device *dev = &adev->dev;
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struct pl061_platform_data *pdata = dev_get_platdata(dev);
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struct pl061 *chip;
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struct pl061 *pl061;
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int ret, irq, i, irq_base;
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
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if (pl061 == NULL)
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return -ENOMEM;
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if (pdata) {
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chip->gc.base = pdata->gpio_base;
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pl061->gc.base = pdata->gpio_base;
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irq_base = pdata->irq_base;
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if (irq_base <= 0) {
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dev_err(&adev->dev, "invalid IRQ base in pdata\n");
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return -ENODEV;
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}
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} else {
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chip->gc.base = -1;
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pl061->gc.base = -1;
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irq_base = 0;
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}
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chip->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(chip->base))
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return PTR_ERR(chip->base);
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pl061->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(pl061->base))
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return PTR_ERR(pl061->base);
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spin_lock_init(&chip->lock);
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spin_lock_init(&pl061->lock);
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if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
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chip->gc.request = gpiochip_generic_request;
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chip->gc.free = gpiochip_generic_free;
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pl061->gc.request = gpiochip_generic_request;
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pl061->gc.free = gpiochip_generic_free;
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}
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chip->gc.get_direction = pl061_get_direction;
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chip->gc.direction_input = pl061_direction_input;
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chip->gc.direction_output = pl061_direction_output;
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chip->gc.get = pl061_get_value;
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chip->gc.set = pl061_set_value;
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chip->gc.ngpio = PL061_GPIO_NR;
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chip->gc.label = dev_name(dev);
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chip->gc.parent = dev;
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chip->gc.owner = THIS_MODULE;
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pl061->gc.get_direction = pl061_get_direction;
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pl061->gc.direction_input = pl061_direction_input;
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pl061->gc.direction_output = pl061_direction_output;
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pl061->gc.get = pl061_get_value;
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pl061->gc.set = pl061_set_value;
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pl061->gc.ngpio = PL061_GPIO_NR;
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pl061->gc.label = dev_name(dev);
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pl061->gc.parent = dev;
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pl061->gc.owner = THIS_MODULE;
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ret = gpiochip_add_data(&chip->gc, chip);
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ret = gpiochip_add_data(&pl061->gc, pl061);
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if (ret)
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return ret;
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/*
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* irq_chip support
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*/
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writeb(0, chip->base + GPIOIE); /* disable irqs */
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writeb(0, pl061->base + GPIOIE); /* disable irqs */
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irq = adev->irq[0];
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if (irq < 0) {
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dev_err(&adev->dev, "invalid IRQ\n");
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return -ENODEV;
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}
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chip->parent_irq = irq;
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pl061->parent_irq = irq;
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ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
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ret = gpiochip_irqchip_add(&pl061->gc, &pl061_irqchip,
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irq_base, handle_bad_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_info(&adev->dev, "could not add irqchip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
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gpiochip_set_chained_irqchip(&pl061->gc, &pl061_irqchip,
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irq, pl061_irq_handler);
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for (i = 0; i < PL061_GPIO_NR; i++) {
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if (pdata) {
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if (pdata->directions & (BIT(i)))
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pl061_direction_output(&chip->gc, i,
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pl061_direction_output(&pl061->gc, i,
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pdata->values & (BIT(i)));
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else
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pl061_direction_input(&chip->gc, i);
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pl061_direction_input(&pl061->gc, i);
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}
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}
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amba_set_drvdata(adev, chip);
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amba_set_drvdata(adev, pl061);
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dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
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&adev->res.start);
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@ -379,20 +379,20 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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#ifdef CONFIG_PM
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static int pl061_suspend(struct device *dev)
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{
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struct pl061 *chip = dev_get_drvdata(dev);
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struct pl061 *pl061 = dev_get_drvdata(dev);
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int offset;
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chip->csave_regs.gpio_data = 0;
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chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
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chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
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chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
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chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
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chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
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pl061->csave_regs.gpio_data = 0;
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pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
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pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
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pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
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pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
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pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (BIT(offset)))
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chip->csave_regs.gpio_data |=
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pl061_get_value(&chip->gc, offset) << offset;
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if (pl061->csave_regs.gpio_dir & (BIT(offset)))
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pl061->csave_regs.gpio_data |=
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pl061_get_value(&pl061->gc, offset) << offset;
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}
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return 0;
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@ -400,22 +400,22 @@ static int pl061_suspend(struct device *dev)
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static int pl061_resume(struct device *dev)
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{
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struct pl061 *chip = dev_get_drvdata(dev);
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struct pl061 *pl061 = dev_get_drvdata(dev);
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int offset;
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for (offset = 0; offset < PL061_GPIO_NR; offset++) {
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if (chip->csave_regs.gpio_dir & (BIT(offset)))
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pl061_direction_output(&chip->gc, offset,
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chip->csave_regs.gpio_data &
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if (pl061->csave_regs.gpio_dir & (BIT(offset)))
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pl061_direction_output(&pl061->gc, offset,
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pl061->csave_regs.gpio_data &
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(BIT(offset)));
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else
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pl061_direction_input(&chip->gc, offset);
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pl061_direction_input(&pl061->gc, offset);
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}
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writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
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writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
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writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
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writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
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writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
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writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
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writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
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writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
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return 0;
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}
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