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drm/nva3/pm: initial attempt at more magic PFB regs 

The reg calculation may get moved elsewhere at some point, but lets
figure out what exactly we need to do first.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-01-27 10:53:17 +10:00
parent 65115bb05a
commit 27740383dd
3 changed files with 28 additions and 3 deletions
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2
drivers/gpu/drm/nouveau/nouveau_perf.c
View File

@ -83,7 +83,7 @@ nouveau_perf_entry(struct drm_device *dev, int idx,
return NULL;
}
static u8 *
u8 *
nouveau_perf_rammap(struct drm_device *dev, u32 freq,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{

4
drivers/gpu/drm/nouveau/nouveau_pm.h
View File

@ -61,8 +61,10 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
/* nouveau_perf.c */
void nouveau_perf_init(struct drm_device *);
void nouveau_perf_fini(struct drm_device *);
u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
u8 *nouveau_perf_rammap(struct drm_device *, u32 freq, u8 *ver,
u8 *hdr, u8 *cnt, u8 *len);
u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
/* nouveau_mem.c */
void nouveau_mem_timing_init(struct drm_device *);

25
drivers/gpu/drm/nouveau/nva3_pm.c
View File

@ -354,8 +354,11 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
static void
mclk_clock_set(struct nouveau_mem_exec_func *exec)
{
struct nva3_pm_state *info = exec->priv;
struct drm_device *dev = exec->dev;
struct nva3_pm_state *info = exec->priv;
struct nouveau_pm_level *perflvl = info->perflvl;
u32 freq = perflvl->memory;
u8 *rammap, *ramcfg, ver, hdr, cnt, len;
nv_wr32(dev, 0x004018, 0x00001000);
@ -365,6 +368,26 @@ mclk_clock_set(struct nouveau_mem_exec_func *exec)
nv_wr32(dev, 0x004018, 0x1000d000);
else
nv_wr32(dev, 0x004018, 0x10005000);
rammap = nouveau_perf_rammap(dev, freq, &ver, &hdr, &cnt, &len);
if (rammap && ver == 0x10 && hdr >= 5) {
ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len);
if (ramcfg && (rammap[4] & 0x08)) {
u32 unk5a0 = (ROM16(ramcfg[5]) << 8) | ramcfg[5];
u32 unk5a4 = ROM16(ramcfg[7]);
u32 unk804 = (ramcfg[9] & 0xf0) << 16 |
(ramcfg[3] & 0x0f) << 16 |
(ramcfg[9] & 0x0f) |
0x80000000;
nv_wr32(dev, 0x1005a0, unk5a0);
nv_wr32(dev, 0x1005a4, unk5a4);
nv_wr32(dev, 0x10f804, unk804);
nv_mask(dev, 0x10053c, 0x00001000, 0x00000000);
} else {
nv_mask(dev, 0x10053c, 0x00001000, 0x00001000);
nv_mask(dev, 0x10f804, 0x80000000, 0x00000000);
}
}
}
static void