iommu/ipmmu-vmsa: Add device tree support
Make platform data optional when the device is instantiated from DT and look up the micro-TLB number in the bus master DT node. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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@ -16,6 +16,7 @@
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_data/ipmmu-vmsa.h>
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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@ -58,6 +59,8 @@ static LIST_HEAD(ipmmu_devices);
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* Registers Definition
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*/
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#define IM_NS_ALIAS_OFFSET 0x800
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#define IM_CTX_SIZE 0x40
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#define IMCTR 0x0000
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@ -1002,16 +1005,33 @@ static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
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static int ipmmu_find_utlb(struct ipmmu_vmsa_device *mmu, struct device *dev)
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{
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const struct ipmmu_vmsa_master *master = mmu->pdata->masters;
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const char *devname = dev_name(dev);
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unsigned int i;
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struct of_phandle_args args;
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int ret;
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for (i = 0; i < mmu->pdata->num_masters; ++i, ++master) {
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if (strcmp(master->name, devname) == 0)
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return master->utlb;
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if (mmu->pdata) {
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const struct ipmmu_vmsa_master *master = mmu->pdata->masters;
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const char *devname = dev_name(dev);
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unsigned int i;
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for (i = 0; i < mmu->pdata->num_masters; ++i, ++master) {
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if (strcmp(master->name, devname) == 0)
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return master->utlb;
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}
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return -1;
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}
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return -1;
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ret = of_parse_phandle_with_args(dev->of_node, "iommus",
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"#iommu-cells", 0, &args);
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if (ret < 0)
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return -1;
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of_node_put(args.np);
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if (args.np != mmu->dev->of_node || args.args_count != 1)
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return -1;
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return args.args[0];
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}
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static int ipmmu_add_device(struct device *dev)
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@ -1157,7 +1177,7 @@ static int ipmmu_probe(struct platform_device *pdev)
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int irq;
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int ret;
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if (!pdev->dev.platform_data) {
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if (!IS_ENABLED(CONFIG_OF) && !pdev->dev.platform_data) {
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dev_err(&pdev->dev, "missing platform data\n");
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return -EINVAL;
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}
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@ -1178,6 +1198,20 @@ static int ipmmu_probe(struct platform_device *pdev)
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if (IS_ERR(mmu->base))
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return PTR_ERR(mmu->base);
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/*
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* The IPMMU has two register banks, for secure and non-secure modes.
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* The bank mapped at the beginning of the IPMMU address space
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* corresponds to the running mode of the CPU. When running in secure
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* mode the non-secure register bank is also available at an offset.
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*
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* Secure mode operation isn't clearly documented and is thus currently
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* not implemented in the driver. Furthermore, preliminary tests of
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* non-secure operation with the main register bank were not successful.
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* Offset the registers base unconditionally to point to the non-secure
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* alias space for now.
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*/
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mmu->base += IM_NS_ALIAS_OFFSET;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "no IRQ found\n");
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@ -1223,9 +1257,14 @@ static int ipmmu_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id ipmmu_of_ids[] = {
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{ .compatible = "renesas,ipmmu-vmsa", },
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};
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static struct platform_driver ipmmu_driver = {
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.driver = {
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.name = "ipmmu-vmsa",
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.of_match_table = of_match_ptr(ipmmu_of_ids),
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},
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.probe = ipmmu_probe,
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.remove = ipmmu_remove,
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