libata: reorder functions in libata-sff.c
Reorder functions in drivers/ata/libata-sff.c such that functions generally follow ops table order and init functions come last. This is in preparation of SFF cleanup. This patch strictly moves stuff around and as such doesn't cause any functional difference. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Tejun Heo
Jeff Garzik
parent
21572ea58a
commit
272f7884e8
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@ -38,6 +38,43 @@
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#include "libata.h"
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/**
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* ata_check_status - Read device status reg & clear interrupt
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* @ap: port where the device is
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*
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* Reads ATA taskfile status register for currently-selected device
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* and return its value. This also clears pending interrupts
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* from this device
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_check_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.status_addr);
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}
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/**
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* ata_altstatus - Read device alternate status reg
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* @ap: port where the device is
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*
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* Reads ATA taskfile alternate status register for
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* currently-selected device and return its value.
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*
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* Note: may NOT be used as the check_altstatus() entry in
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* ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_altstatus(struct ata_port *ap)
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{
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if (ap->ops->check_altstatus)
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return ap->ops->check_altstatus(ap);
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return ioread8(ap->ioaddr.altstatus_addr);
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}
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/**
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* ata_irq_on - Enable interrupts on a port.
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* @ap: Port on which interrupts are enabled.
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@ -65,6 +102,27 @@ u8 ata_irq_on(struct ata_port *ap)
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return tmp;
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}
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/**
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* ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
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* @ap: Port associated with this ATA transaction.
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*
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* Clear interrupt and error flags in DMA status register.
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*
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* May be used as the irq_clear() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_irq_clear(struct ata_port *ap)
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{
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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if (!mmio)
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return;
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iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
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}
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/**
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* ata_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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@ -75,7 +133,6 @@ u8 ata_irq_on(struct ata_port *ap)
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* LOCKING:
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* Inherited from caller.
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*/
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void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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@ -125,25 +182,6 @@ void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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ata_wait_idle(ap);
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}
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/**
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* ata_exec_command - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Issues ATA command, with proper synchronization with interrupt
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* handler / other threads.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
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iowrite8(tf->command, ap->ioaddr.command_addr);
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ata_pause(ap);
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}
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/**
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* ata_tf_read - input device's ATA taskfile shadow registers
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* @ap: Port from which input is read
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@ -185,169 +223,22 @@ void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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}
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/**
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* ata_check_status - Read device status reg & clear interrupt
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* @ap: port where the device is
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* ata_exec_command - issue ATA command to host controller
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* @ap: port to which command is being issued
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* @tf: ATA taskfile register set
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*
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* Reads ATA taskfile status register for currently-selected device
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* and return its value. This also clears pending interrupts
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* from this device
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_check_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.status_addr);
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}
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/**
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* ata_altstatus - Read device alternate status reg
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* @ap: port where the device is
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*
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* Reads ATA taskfile alternate status register for
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* currently-selected device and return its value.
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*
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* Note: may NOT be used as the check_altstatus() entry in
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* ata_port_operations.
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*
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* LOCKING:
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* Inherited from caller.
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*/
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u8 ata_altstatus(struct ata_port *ap)
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{
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if (ap->ops->check_altstatus)
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return ap->ops->check_altstatus(ap);
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return ioread8(ap->ioaddr.altstatus_addr);
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}
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/**
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* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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* Issues ATA command, with proper synchronization with interrupt
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* handler / other threads.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_setup(struct ata_queued_cmd *qc)
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void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->exec_command(ap, &qc->tf);
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}
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/**
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* ata_bmdma_start - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* Strictly, one may wish to issue an ioread8() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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* Further, a read of the DMA status register _immediately_
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* following the write may not be what certain flaky hardware
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* is expected, so I think it is best to not add a readb()
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* without first all the MMIO ATA cards/mobos.
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* Or maybe I'm just being paranoid.
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*
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* FIXME: The posting of this write means I/O starts are
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* unneccessarily delayed for MMIO
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*/
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}
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/**
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* ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
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* @ap: Port associated with this ATA transaction.
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*
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* Clear interrupt and error flags in DMA status register.
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*
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* May be used as the irq_clear() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_irq_clear(struct ata_port *ap)
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{
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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if (!mmio)
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return;
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iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
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}
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/**
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* ata_noop_irq_clear - Noop placeholder for irq_clear
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* @ap: Port associated with this ATA transaction.
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*/
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void ata_noop_irq_clear(struct ata_port *ap)
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{
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}
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/**
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* ata_bmdma_status - Read PCI IDE BMDMA status
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* @ap: Port associated with this ATA transaction.
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*
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* Read and return BMDMA status register.
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*
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* May be used as the bmdma_status() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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u8 ata_bmdma_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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/**
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* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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* @qc: Command we are ending DMA for
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*
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* Clears the ATA_DMA_START flag in the dma control register
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*
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* May be used as the bmdma_stop() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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/* clear start/stop bit */
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iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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mmio + ATA_DMA_CMD);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_altstatus(ap); /* dummy read */
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iowrite8(tf->command, ap->ioaddr.command_addr);
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ata_pause(ap);
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}
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/**
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@ -495,7 +386,6 @@ void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
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* LOCKING:
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* Inherited from caller.
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*/
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int ata_sff_port_start(struct ata_port *ap)
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{
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if (ap->ioaddr.bmdma_addr)
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@ -503,20 +393,149 @@ int ata_sff_port_start(struct ata_port *ap)
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return 0;
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}
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/**
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* ata_bmdma_setup - Set up PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_setup(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* issue r/w command */
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ap->ops->exec_command(ap, &qc->tf);
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}
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/**
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* ata_bmdma_start - Start a PCI IDE BMDMA transaction
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
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/* Strictly, one may wish to issue an ioread8() here, to
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* flush the mmio write. However, control also passes
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* to the hardware at this point, and it will interrupt
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* us when we are to resume control. So, in effect,
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* we don't care when the mmio write flushes.
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* Further, a read of the DMA status register _immediately_
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* following the write may not be what certain flaky hardware
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* is expected, so I think it is best to not add a readb()
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* without first all the MMIO ATA cards/mobos.
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* Or maybe I'm just being paranoid.
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*
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* FIXME: The posting of this write means I/O starts are
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* unneccessarily delayed for MMIO
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*/
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}
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/**
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* ata_bmdma_stop - Stop PCI IDE BMDMA transfer
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* @qc: Command we are ending DMA for
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*
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* Clears the ATA_DMA_START flag in the dma control register
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*
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* May be used as the bmdma_stop() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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void ata_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = ap->ioaddr.bmdma_addr;
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/* clear start/stop bit */
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iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
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mmio + ATA_DMA_CMD);
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
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ata_altstatus(ap); /* dummy read */
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}
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/**
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* ata_bmdma_status - Read PCI IDE BMDMA status
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* @ap: Port associated with this ATA transaction.
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*
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* Read and return BMDMA status register.
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*
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* May be used as the bmdma_status() entry in ata_port_operations.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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u8 ata_bmdma_status(struct ata_port *ap)
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{
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return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
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}
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/**
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* ata_noop_irq_clear - Noop placeholder for irq_clear
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* @ap: Port associated with this ATA transaction.
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*/
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void ata_noop_irq_clear(struct ata_port *ap)
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{
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}
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#ifdef CONFIG_PCI
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static int ata_resources_present(struct pci_dev *pdev, int port)
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/**
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* ata_pci_clear_simplex - attempt to kick device out of simplex
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* @pdev: PCI device
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*
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* Some PCI ATA devices report simplex mode but in fact can be told to
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* enter non simplex mode. This implements the necessary logic to
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* perform the task on such devices. Calling it on other devices will
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* have -undefined- behaviour.
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*/
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int ata_pci_clear_simplex(struct pci_dev *pdev)
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{
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int i;
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unsigned long bmdma = pci_resource_start(pdev, 4);
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u8 simplex;
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/* Check the PCI resources for this channel are enabled */
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port = port * 2;
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for (i = 0; i < 2; i ++) {
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if (pci_resource_start(pdev, port + i) == 0 ||
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pci_resource_len(pdev, port + i) == 0)
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return 0;
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}
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return 1;
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if (bmdma == 0)
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return -ENOENT;
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simplex = inb(bmdma + 0x02);
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outb(simplex & 0x60, bmdma + 0x02);
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simplex = inb(bmdma + 0x02);
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if (simplex & 0x80)
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return -EOPNOTSUPP;
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return 0;
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}
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unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
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{
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/* Filter out DMA modes if the device has been configured by
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the BIOS as PIO only */
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if (adev->link->ap->ioaddr.bmdma_addr == NULL)
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xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
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return xfer_mask;
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}
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/**
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@ -576,6 +595,20 @@ int ata_pci_init_bmdma(struct ata_host *host)
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return 0;
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}
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static int ata_resources_present(struct pci_dev *pdev, int port)
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{
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int i;
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/* Check the PCI resources for this channel are enabled */
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||||
port = port * 2;
|
||||
for (i = 0; i < 2; i ++) {
|
||||
if (pci_resource_start(pdev, port + i) == 0 ||
|
||||
pci_resource_len(pdev, port + i) == 0)
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* ata_pci_init_sff_host - acquire native PCI ATA resources and init host
|
||||
* @host: target ATA host
|
||||
|
|
@ -879,41 +912,5 @@ int ata_pci_init_one(struct pci_dev *pdev,
|
|||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* ata_pci_clear_simplex - attempt to kick device out of simplex
|
||||
* @pdev: PCI device
|
||||
*
|
||||
* Some PCI ATA devices report simplex mode but in fact can be told to
|
||||
* enter non simplex mode. This implements the necessary logic to
|
||||
* perform the task on such devices. Calling it on other devices will
|
||||
* have -undefined- behaviour.
|
||||
*/
|
||||
|
||||
int ata_pci_clear_simplex(struct pci_dev *pdev)
|
||||
{
|
||||
unsigned long bmdma = pci_resource_start(pdev, 4);
|
||||
u8 simplex;
|
||||
|
||||
if (bmdma == 0)
|
||||
return -ENOENT;
|
||||
|
||||
simplex = inb(bmdma + 0x02);
|
||||
outb(simplex & 0x60, bmdma + 0x02);
|
||||
simplex = inb(bmdma + 0x02);
|
||||
if (simplex & 0x80)
|
||||
return -EOPNOTSUPP;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
|
||||
{
|
||||
/* Filter out DMA modes if the device has been configured by
|
||||
the BIOS as PIO only */
|
||||
|
||||
if (adev->link->ap->ioaddr.bmdma_addr == NULL)
|
||||
xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
|
||||
return xfer_mask;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue