staging: gasket: apex: fix function param line continuation style
Fix multi-line alignment formatting to look like:
int ret = long_function_name(device, VARIABLE1, VARIABLE2,
VARIABLE3, VARIABLE4);
Many of these TODO items were previously cleaned up during the conversion
to standard logging functions.
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Todd Poynor
Greg Kroah-Hartman
parent
c76b15fe7b
commit
26fd80ead0
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@ -240,9 +240,9 @@ static int apex_enter_reset(struct gasket_dev *gasket_dev, uint type)
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* - Software force GCB idle
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* - Enable GCB idle
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*/
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gasket_read_modify_write_64(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_IDLEGENERATOR_IDLEGEN_IDLEREGISTER, 0x0, 1, 32);
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gasket_read_modify_write_64(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_IDLEGENERATOR_IDLEGEN_IDLEREGISTER,
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0x0, 1, 32);
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/* - Initiate DMA pause */
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gasket_dev_write_64(gasket_dev, 1, APEX_BAR_INDEX,
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@ -259,16 +259,16 @@ static int apex_enter_reset(struct gasket_dev *gasket_dev, uint type)
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}
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/* - Enable GCB reset (0x1 to rg_rst_gcb) */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_2, 0x1, 2, 2);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_2, 0x1, 2, 2);
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/* - Enable GCB clock Gate (0x1 to rg_gated_gcb) */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_2, 0x1, 2, 18);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_2, 0x1, 2, 18);
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/* - Enable GCB memory shut down (0x3 to rg_force_ram_sd) */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3, 0x3, 2, 14);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3, 0x3, 2, 14);
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/* - Wait for RAM shutdown. */
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if (gasket_wait_with_reschedule(gasket_dev, APEX_BAR_INDEX,
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@ -297,24 +297,24 @@ static int apex_quit_reset(struct gasket_dev *gasket_dev, uint type)
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* - b00: Not forced (HW controlled)
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* - b1x: Force disable
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*/
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3, 0x0, 2, 14);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3, 0x0, 2, 14);
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/*
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* - Disable software clock gate:
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* - b00: Not forced (HW controlled)
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* - b1x: Force disable
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*/
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_2, 0x0, 2, 18);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_2, 0x0, 2, 18);
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/*
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* - Disable GCB reset (rg_rst_gcb):
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* - b00: Not forced (HW controlled)
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* - b1x: Force disable = Force not Reset
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*/
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_2, 0x2, 2, 2);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_2, 0x2, 2, 2);
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/* - Wait for RAM enable. */
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if (gasket_wait_with_reschedule(gasket_dev, APEX_BAR_INDEX,
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@ -338,27 +338,28 @@ static int apex_quit_reset(struct gasket_dev *gasket_dev, uint type)
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}
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if (!allow_hw_clock_gating) {
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val0 = gasket_dev_read_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3);
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val0 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3);
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/* Inactive and Sleep mode are disabled. */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3, 0x3,
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SCU3_RG_PWR_STATE_OVR_MASK_WIDTH,
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SCU3_RG_PWR_STATE_OVR_BIT_OFFSET);
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val1 = gasket_dev_read_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3);
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gasket_read_modify_write_32(gasket_dev,
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APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3, 0x3,
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SCU3_RG_PWR_STATE_OVR_MASK_WIDTH,
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SCU3_RG_PWR_STATE_OVR_BIT_OFFSET);
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val1 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3);
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dev_dbg(gasket_dev->dev,
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"Disallow HW clock gating 0x%x -> 0x%x\n", val0, val1);
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} else {
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val0 = gasket_dev_read_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3);
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val0 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3);
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/* Inactive mode enabled - Sleep mode disabled. */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3, 2,
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SCU3_RG_PWR_STATE_OVR_MASK_WIDTH,
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SCU3_RG_PWR_STATE_OVR_BIT_OFFSET);
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val1 = gasket_dev_read_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3, 2,
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SCU3_RG_PWR_STATE_OVR_MASK_WIDTH,
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SCU3_RG_PWR_STATE_OVR_BIT_OFFSET);
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val1 = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3);
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dev_dbg(gasket_dev->dev, "Allow HW clock gating 0x%x -> 0x%x\n",
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val0, val1);
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}
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@ -373,12 +374,10 @@ static int apex_device_cleanup(struct gasket_dev *gasket_dev)
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u64 hib_error;
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int ret = 0;
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hib_error = gasket_dev_read_64(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_USER_HIB_ERROR_STATUS);
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scalar_error = gasket_dev_read_64(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCALAR_CORE_ERROR_STATUS);
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hib_error = gasket_dev_read_64(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_USER_HIB_ERROR_STATUS);
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scalar_error = gasket_dev_read_64(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCALAR_CORE_ERROR_STATUS);
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dev_dbg(gasket_dev->dev,
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"%s 0x%p hib_error 0x%llx scalar_error 0x%llx\n",
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@ -393,8 +392,8 @@ static int apex_device_cleanup(struct gasket_dev *gasket_dev)
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/* Determine if GCB is in reset state. */
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static bool is_gcb_in_reset(struct gasket_dev *gasket_dev)
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{
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u32 val = gasket_dev_read_32(
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gasket_dev, APEX_BAR_INDEX, APEX_BAR2_REG_SCU_3);
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u32 val = gasket_dev_read_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_SCU_3);
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/* Masks rg_rst_gcb bit of SCU_CTRL_2 */
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return (val & SCU3_CUR_RST_GCB_BIT_MASK);
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@ -432,13 +431,11 @@ static int apex_add_dev_cb(struct gasket_dev *gasket_dev)
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while (retries < APEX_RESET_RETRY) {
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page_table_ready =
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gasket_dev_read_64(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_INIT);
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gasket_dev_read_64(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_KERNEL_HIB_PAGE_TABLE_INIT);
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msix_table_ready =
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gasket_dev_read_64(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_KERNEL_HIB_MSIX_TABLE_INIT);
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gasket_dev_read_64(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_KERNEL_HIB_MSIX_TABLE_INIT);
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if (page_table_ready && msix_table_ready)
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break;
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schedule_timeout(msecs_to_jiffies(APEX_RESET_DELAY));
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@ -481,20 +478,20 @@ static long apex_clock_gating(struct gasket_dev *gasket_dev,
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if (ibuf.enable) {
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/* Quiesce AXI, gate GCB clock. */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_AXI_QUIESCE, 0x1, 1, 16);
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_GCB_CLOCK_GATE, 0x1, 2, 18);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_AXI_QUIESCE, 0x1, 1,
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16);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_GCB_CLOCK_GATE, 0x1,
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2, 18);
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} else {
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/* Un-gate GCB clock, un-quiesce AXI. */
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_GCB_CLOCK_GATE, 0x0, 2, 18);
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gasket_read_modify_write_32(
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gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_AXI_QUIESCE, 0x0, 1, 16);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_GCB_CLOCK_GATE, 0x0,
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2, 18);
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gasket_read_modify_write_32(gasket_dev, APEX_BAR_INDEX,
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APEX_BAR2_REG_AXI_QUIESCE, 0x0, 1,
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16);
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}
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return 0;
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}
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@ -516,8 +513,8 @@ static long apex_ioctl(struct file *filp, uint cmd, void __user *argp)
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}
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/* Display driver sysfs entries. */
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static ssize_t sysfs_show(
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struct device *device, struct device_attribute *attr, char *buf)
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static ssize_t sysfs_show(struct device *device, struct device_attribute *attr,
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char *buf)
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{
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int ret;
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struct gasket_dev *gasket_dev;
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@ -578,8 +575,8 @@ static struct gasket_sysfs_attribute apex_sysfs_attrs[] = {
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static int apex_sysfs_setup_cb(struct gasket_dev *gasket_dev)
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{
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return gasket_sysfs_create_entries(
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gasket_dev->dev_info.device, apex_sysfs_attrs);
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return gasket_sysfs_create_entries(gasket_dev->dev_info.device,
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apex_sysfs_attrs);
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}
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/* On device open, perform a core reinit reset. */
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