media: staging/intel-ipu3: mmu: Implement driver
This driver translates IO virtual address to physical address based on two levels page tables. Signed-off-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Tomasz Figa
Mauro Carvalho Chehab
parent
2da6500d33
commit
26f5689592
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@ -0,0 +1,561 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Intel Corporation.
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* Copyright 2018 Google LLC.
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*
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* Author: Tuukka Toivonen <tuukka.toivonen@intel.com>
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* Author: Sakari Ailus <sakari.ailus@linux.intel.com>
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* Author: Samu Onkalo <samu.onkalo@intel.com>
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* Author: Tomasz Figa <tfiga@chromium.org>
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*
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*/
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <asm/set_memory.h>
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#include "ipu3-mmu.h"
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#define IPU3_PAGE_SHIFT 12
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#define IPU3_PAGE_SIZE (1UL << IPU3_PAGE_SHIFT)
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#define IPU3_PT_BITS 10
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#define IPU3_PT_PTES (1UL << IPU3_PT_BITS)
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#define IPU3_PT_SIZE (IPU3_PT_PTES << 2)
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#define IPU3_PT_ORDER (IPU3_PT_SIZE >> PAGE_SHIFT)
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#define IPU3_ADDR2PTE(addr) ((addr) >> IPU3_PAGE_SHIFT)
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#define IPU3_PTE2ADDR(pte) ((phys_addr_t)(pte) << IPU3_PAGE_SHIFT)
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#define IPU3_L2PT_SHIFT IPU3_PT_BITS
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#define IPU3_L2PT_MASK ((1UL << IPU3_L2PT_SHIFT) - 1)
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#define IPU3_L1PT_SHIFT IPU3_PT_BITS
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#define IPU3_L1PT_MASK ((1UL << IPU3_L1PT_SHIFT) - 1)
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#define IPU3_MMU_ADDRESS_BITS (IPU3_PAGE_SHIFT + \
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IPU3_L2PT_SHIFT + \
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IPU3_L1PT_SHIFT)
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#define IMGU_REG_BASE 0x4000
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#define REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300)
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#define TLB_INVALIDATE 1
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#define REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
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#define REG_GP_HALT (IMGU_REG_BASE + 0x5dc)
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#define REG_GP_HALTED (IMGU_REG_BASE + 0x5e0)
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struct ipu3_mmu {
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struct device *dev;
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void __iomem *base;
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/* protect access to l2pts, l1pt */
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spinlock_t lock;
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void *dummy_page;
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u32 dummy_page_pteval;
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u32 *dummy_l2pt;
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u32 dummy_l2pt_pteval;
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u32 **l2pts;
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u32 *l1pt;
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struct ipu3_mmu_info geometry;
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};
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static inline struct ipu3_mmu *to_ipu3_mmu(struct ipu3_mmu_info *info)
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{
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return container_of(info, struct ipu3_mmu, geometry);
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}
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/**
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* ipu3_mmu_tlb_invalidate - invalidate translation look-aside buffer
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* @mmu: MMU to perform the invalidate operation on
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*
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* This function invalidates the whole TLB. Must be called when the hardware
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* is powered on.
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*/
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static void ipu3_mmu_tlb_invalidate(struct ipu3_mmu *mmu)
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{
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writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE);
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}
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static void call_if_ipu3_is_powered(struct ipu3_mmu *mmu,
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void (*func)(struct ipu3_mmu *mmu))
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{
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if (!pm_runtime_get_if_in_use(mmu->dev))
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return;
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func(mmu);
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pm_runtime_put(mmu->dev);
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}
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/**
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* ipu3_mmu_set_halt - set CIO gate halt bit
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* @mmu: MMU to set the CIO gate bit in.
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* @halt: Desired state of the gate bit.
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*
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* This function sets the CIO gate bit that controls whether external memory
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* accesses are allowed. Must be called when the hardware is powered on.
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*/
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static void ipu3_mmu_set_halt(struct ipu3_mmu *mmu, bool halt)
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{
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int ret;
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u32 val;
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writel(halt, mmu->base + REG_GP_HALT);
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ret = readl_poll_timeout(mmu->base + REG_GP_HALTED,
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val, (val & 1) == halt, 1000, 100000);
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if (ret)
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dev_err(mmu->dev, "failed to %s CIO gate halt\n",
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halt ? "set" : "clear");
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}
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/**
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* ipu3_mmu_alloc_page_table - allocate a pre-filled page table
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* @pteval: Value to initialize for page table entries with.
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*
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* Return: Pointer to allocated page table or NULL on failure.
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*/
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static u32 *ipu3_mmu_alloc_page_table(u32 pteval)
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{
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u32 *pt;
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int pte;
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pt = (u32 *)__get_free_page(GFP_KERNEL);
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if (!pt)
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return NULL;
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for (pte = 0; pte < IPU3_PT_PTES; pte++)
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pt[pte] = pteval;
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set_memory_uc((unsigned long int)pt, IPU3_PT_ORDER);
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return pt;
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}
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/**
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* ipu3_mmu_free_page_table - free page table
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* @pt: Page table to free.
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*/
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static void ipu3_mmu_free_page_table(u32 *pt)
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{
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set_memory_wb((unsigned long int)pt, IPU3_PT_ORDER);
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free_page((unsigned long)pt);
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}
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/**
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* address_to_pte_idx - split IOVA into L1 and L2 page table indices
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* @iova: IOVA to split.
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* @l1pt_idx: Output for the L1 page table index.
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* @l2pt_idx: Output for the L2 page index.
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*/
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static inline void address_to_pte_idx(unsigned long iova, u32 *l1pt_idx,
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u32 *l2pt_idx)
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{
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iova >>= IPU3_PAGE_SHIFT;
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if (l2pt_idx)
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*l2pt_idx = iova & IPU3_L2PT_MASK;
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iova >>= IPU3_L2PT_SHIFT;
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if (l1pt_idx)
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*l1pt_idx = iova & IPU3_L1PT_MASK;
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}
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static u32 *ipu3_mmu_get_l2pt(struct ipu3_mmu *mmu, u32 l1pt_idx)
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{
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unsigned long flags;
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u32 *l2pt, *new_l2pt;
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u32 pteval;
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spin_lock_irqsave(&mmu->lock, flags);
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l2pt = mmu->l2pts[l1pt_idx];
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if (l2pt)
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goto done;
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spin_unlock_irqrestore(&mmu->lock, flags);
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new_l2pt = ipu3_mmu_alloc_page_table(mmu->dummy_page_pteval);
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if (!new_l2pt)
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return NULL;
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spin_lock_irqsave(&mmu->lock, flags);
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dev_dbg(mmu->dev, "allocated page table %p for l1pt_idx %u\n",
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new_l2pt, l1pt_idx);
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l2pt = mmu->l2pts[l1pt_idx];
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if (l2pt) {
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ipu3_mmu_free_page_table(new_l2pt);
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goto done;
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}
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l2pt = new_l2pt;
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mmu->l2pts[l1pt_idx] = new_l2pt;
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pteval = IPU3_ADDR2PTE(virt_to_phys(new_l2pt));
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mmu->l1pt[l1pt_idx] = pteval;
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done:
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spin_unlock_irqrestore(&mmu->lock, flags);
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return l2pt;
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}
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static int __ipu3_mmu_map(struct ipu3_mmu *mmu, unsigned long iova,
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phys_addr_t paddr)
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{
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u32 l1pt_idx, l2pt_idx;
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unsigned long flags;
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u32 *l2pt;
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if (!mmu)
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return -ENODEV;
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address_to_pte_idx(iova, &l1pt_idx, &l2pt_idx);
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l2pt = ipu3_mmu_get_l2pt(mmu, l1pt_idx);
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if (!l2pt)
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return -ENOMEM;
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spin_lock_irqsave(&mmu->lock, flags);
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if (l2pt[l2pt_idx] != mmu->dummy_page_pteval) {
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spin_unlock_irqrestore(&mmu->lock, flags);
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return -EBUSY;
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}
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l2pt[l2pt_idx] = IPU3_ADDR2PTE(paddr);
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spin_unlock_irqrestore(&mmu->lock, flags);
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return 0;
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}
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/**
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* The following four functions are implemented based on iommu.c
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* drivers/iommu/iommu.c/iommu_pgsize().
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*/
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static size_t ipu3_mmu_pgsize(unsigned long pgsize_bitmap,
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unsigned long addr_merge, size_t size)
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{
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unsigned int pgsize_idx;
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size_t pgsize;
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/* Max page size that still fits into 'size' */
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pgsize_idx = __fls(size);
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/* need to consider alignment requirements ? */
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if (likely(addr_merge)) {
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/* Max page size allowed by address */
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unsigned int align_pgsize_idx = __ffs(addr_merge);
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pgsize_idx = min(pgsize_idx, align_pgsize_idx);
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}
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/* build a mask of acceptable page sizes */
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pgsize = (1UL << (pgsize_idx + 1)) - 1;
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/* throw away page sizes not supported by the hardware */
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pgsize &= pgsize_bitmap;
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/* make sure we're still sane */
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WARN_ON(!pgsize);
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/* pick the biggest page */
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pgsize_idx = __fls(pgsize);
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pgsize = 1UL << pgsize_idx;
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return pgsize;
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}
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/* drivers/iommu/iommu.c/iommu_map() */
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int ipu3_mmu_map(struct ipu3_mmu_info *info, unsigned long iova,
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phys_addr_t paddr, size_t size)
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{
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struct ipu3_mmu *mmu = to_ipu3_mmu(info);
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unsigned int min_pagesz;
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int ret = 0;
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/* find out the minimum page size supported */
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min_pagesz = 1 << __ffs(mmu->geometry.pgsize_bitmap);
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/*
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* both the virtual address and the physical one, as well as
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* the size of the mapping, must be aligned (at least) to the
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* size of the smallest page supported by the hardware
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*/
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if (!IS_ALIGNED(iova | paddr | size, min_pagesz)) {
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dev_err(mmu->dev, "unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%x\n",
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iova, &paddr, size, min_pagesz);
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return -EINVAL;
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}
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dev_dbg(mmu->dev, "map: iova 0x%lx pa %pa size 0x%zx\n",
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iova, &paddr, size);
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while (size) {
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size_t pgsize = ipu3_mmu_pgsize(mmu->geometry.pgsize_bitmap,
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iova | paddr, size);
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dev_dbg(mmu->dev, "mapping: iova 0x%lx pa %pa pgsize 0x%zx\n",
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iova, &paddr, pgsize);
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ret = __ipu3_mmu_map(mmu, iova, paddr);
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if (ret)
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break;
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iova += pgsize;
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paddr += pgsize;
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size -= pgsize;
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}
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call_if_ipu3_is_powered(mmu, ipu3_mmu_tlb_invalidate);
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return ret;
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}
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/* drivers/iommu/iommu.c/default_iommu_map_sg() */
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size_t ipu3_mmu_map_sg(struct ipu3_mmu_info *info, unsigned long iova,
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struct scatterlist *sg, unsigned int nents)
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{
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struct ipu3_mmu *mmu = to_ipu3_mmu(info);
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struct scatterlist *s;
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size_t s_length, mapped = 0;
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unsigned int i, min_pagesz;
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int ret;
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min_pagesz = 1 << __ffs(mmu->geometry.pgsize_bitmap);
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for_each_sg(sg, s, nents, i) {
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phys_addr_t phys = page_to_phys(sg_page(s)) + s->offset;
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s_length = s->length;
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if (!IS_ALIGNED(s->offset, min_pagesz))
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goto out_err;
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/* must be min_pagesz aligned to be mapped singlely */
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if (i == nents - 1 && !IS_ALIGNED(s->length, min_pagesz))
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s_length = PAGE_ALIGN(s->length);
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ret = ipu3_mmu_map(info, iova + mapped, phys, s_length);
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if (ret)
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goto out_err;
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mapped += s_length;
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}
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call_if_ipu3_is_powered(mmu, ipu3_mmu_tlb_invalidate);
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return mapped;
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out_err:
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/* undo mappings already done */
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ipu3_mmu_unmap(info, iova, mapped);
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return 0;
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}
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static size_t __ipu3_mmu_unmap(struct ipu3_mmu *mmu,
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unsigned long iova, size_t size)
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{
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u32 l1pt_idx, l2pt_idx;
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unsigned long flags;
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size_t unmap = size;
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u32 *l2pt;
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if (!mmu)
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return 0;
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address_to_pte_idx(iova, &l1pt_idx, &l2pt_idx);
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spin_lock_irqsave(&mmu->lock, flags);
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l2pt = mmu->l2pts[l1pt_idx];
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if (!l2pt) {
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spin_unlock_irqrestore(&mmu->lock, flags);
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return 0;
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}
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if (l2pt[l2pt_idx] == mmu->dummy_page_pteval)
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unmap = 0;
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l2pt[l2pt_idx] = mmu->dummy_page_pteval;
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spin_unlock_irqrestore(&mmu->lock, flags);
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return unmap;
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}
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/* drivers/iommu/iommu.c/iommu_unmap() */
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size_t ipu3_mmu_unmap(struct ipu3_mmu_info *info, unsigned long iova,
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size_t size)
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{
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struct ipu3_mmu *mmu = to_ipu3_mmu(info);
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size_t unmapped_page, unmapped = 0;
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unsigned int min_pagesz;
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/* find out the minimum page size supported */
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min_pagesz = 1 << __ffs(mmu->geometry.pgsize_bitmap);
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/*
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* The virtual address, as well as the size of the mapping, must be
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* aligned (at least) to the size of the smallest page supported
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* by the hardware
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*/
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if (!IS_ALIGNED(iova | size, min_pagesz)) {
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dev_err(mmu->dev, "unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n",
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iova, size, min_pagesz);
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return -EINVAL;
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}
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dev_dbg(mmu->dev, "unmap this: iova 0x%lx size 0x%zx\n", iova, size);
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/*
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* Keep iterating until we either unmap 'size' bytes (or more)
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* or we hit an area that isn't mapped.
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*/
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while (unmapped < size) {
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size_t pgsize = ipu3_mmu_pgsize(mmu->geometry.pgsize_bitmap,
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iova, size - unmapped);
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unmapped_page = __ipu3_mmu_unmap(mmu, iova, pgsize);
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if (!unmapped_page)
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break;
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dev_dbg(mmu->dev, "unmapped: iova 0x%lx size 0x%zx\n",
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iova, unmapped_page);
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iova += unmapped_page;
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unmapped += unmapped_page;
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}
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call_if_ipu3_is_powered(mmu, ipu3_mmu_tlb_invalidate);
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return unmapped;
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}
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/**
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* ipu3_mmu_init() - initialize IPU3 MMU block
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* @base: IOMEM base of hardware registers.
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*
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* Return: Pointer to IPU3 MMU private data pointer or ERR_PTR() on error.
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*/
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struct ipu3_mmu_info *ipu3_mmu_init(struct device *parent, void __iomem *base)
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{
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struct ipu3_mmu *mmu;
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u32 pteval;
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mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
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if (!mmu)
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return ERR_PTR(-ENOMEM);
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mmu->dev = parent;
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mmu->base = base;
|
||||
spin_lock_init(&mmu->lock);
|
||||
|
||||
/* Disallow external memory access when having no valid page tables. */
|
||||
ipu3_mmu_set_halt(mmu, true);
|
||||
|
||||
/*
|
||||
* The MMU does not have a "valid" bit, so we have to use a dummy
|
||||
* page for invalid entries.
|
||||
*/
|
||||
mmu->dummy_page = (void *)__get_free_page(GFP_KERNEL);
|
||||
if (!mmu->dummy_page)
|
||||
goto fail_group;
|
||||
pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->dummy_page));
|
||||
mmu->dummy_page_pteval = pteval;
|
||||
|
||||
/*
|
||||
* Allocate a dummy L2 page table with all entries pointing to
|
||||
* the dummy page.
|
||||
*/
|
||||
mmu->dummy_l2pt = ipu3_mmu_alloc_page_table(pteval);
|
||||
if (!mmu->dummy_l2pt)
|
||||
goto fail_dummy_page;
|
||||
pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->dummy_l2pt));
|
||||
mmu->dummy_l2pt_pteval = pteval;
|
||||
|
||||
/*
|
||||
* Allocate the array of L2PT CPU pointers, initialized to zero,
|
||||
* which means the dummy L2PT allocated above.
|
||||
*/
|
||||
mmu->l2pts = vzalloc(IPU3_PT_PTES * sizeof(*mmu->l2pts));
|
||||
if (!mmu->l2pts)
|
||||
goto fail_l2pt;
|
||||
|
||||
/* Allocate the L1 page table. */
|
||||
mmu->l1pt = ipu3_mmu_alloc_page_table(mmu->dummy_l2pt_pteval);
|
||||
if (!mmu->l1pt)
|
||||
goto fail_l2pts;
|
||||
|
||||
pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->l1pt));
|
||||
writel(pteval, mmu->base + REG_L1_PHYS);
|
||||
ipu3_mmu_tlb_invalidate(mmu);
|
||||
ipu3_mmu_set_halt(mmu, false);
|
||||
|
||||
mmu->geometry.aperture_start = 0;
|
||||
mmu->geometry.aperture_end = DMA_BIT_MASK(IPU3_MMU_ADDRESS_BITS);
|
||||
mmu->geometry.pgsize_bitmap = IPU3_PAGE_SIZE;
|
||||
|
||||
return &mmu->geometry;
|
||||
|
||||
fail_l2pts:
|
||||
vfree(mmu->l2pts);
|
||||
fail_l2pt:
|
||||
ipu3_mmu_free_page_table(mmu->dummy_l2pt);
|
||||
fail_dummy_page:
|
||||
free_page((unsigned long)mmu->dummy_page);
|
||||
fail_group:
|
||||
kfree(mmu);
|
||||
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
/**
|
||||
* ipu3_mmu_exit() - clean up IPU3 MMU block
|
||||
* @mmu: IPU3 MMU private data
|
||||
*/
|
||||
void ipu3_mmu_exit(struct ipu3_mmu_info *info)
|
||||
{
|
||||
struct ipu3_mmu *mmu = to_ipu3_mmu(info);
|
||||
|
||||
/* We are going to free our page tables, no more memory access. */
|
||||
ipu3_mmu_set_halt(mmu, true);
|
||||
ipu3_mmu_tlb_invalidate(mmu);
|
||||
|
||||
ipu3_mmu_free_page_table(mmu->l1pt);
|
||||
vfree(mmu->l2pts);
|
||||
ipu3_mmu_free_page_table(mmu->dummy_l2pt);
|
||||
free_page((unsigned long)mmu->dummy_page);
|
||||
kfree(mmu);
|
||||
}
|
||||
|
||||
void ipu3_mmu_suspend(struct ipu3_mmu_info *info)
|
||||
{
|
||||
struct ipu3_mmu *mmu = to_ipu3_mmu(info);
|
||||
|
||||
ipu3_mmu_set_halt(mmu, true);
|
||||
}
|
||||
|
||||
void ipu3_mmu_resume(struct ipu3_mmu_info *info)
|
||||
{
|
||||
struct ipu3_mmu *mmu = to_ipu3_mmu(info);
|
||||
u32 pteval;
|
||||
|
||||
ipu3_mmu_set_halt(mmu, true);
|
||||
|
||||
pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->l1pt));
|
||||
writel(pteval, mmu->base + REG_L1_PHYS);
|
||||
|
||||
ipu3_mmu_tlb_invalidate(mmu);
|
||||
ipu3_mmu_set_halt(mmu, false);
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (C) 2018 Intel Corporation */
|
||||
/* Copyright 2018 Google LLC. */
|
||||
|
||||
#ifndef __IPU3_MMU_H
|
||||
#define __IPU3_MMU_H
|
||||
|
||||
/**
|
||||
* struct ipu3_mmu_info - Describes mmu geometry
|
||||
*
|
||||
* @aperture_start: First address that can be mapped
|
||||
* @aperture_end: Last address that can be mapped
|
||||
* @pgsize_bitmap: Bitmap of page sizes in use
|
||||
*/
|
||||
struct ipu3_mmu_info {
|
||||
dma_addr_t aperture_start;
|
||||
dma_addr_t aperture_end;
|
||||
unsigned long pgsize_bitmap;
|
||||
};
|
||||
|
||||
struct device;
|
||||
struct scatterlist;
|
||||
|
||||
struct ipu3_mmu_info *ipu3_mmu_init(struct device *parent, void __iomem *base);
|
||||
void ipu3_mmu_exit(struct ipu3_mmu_info *info);
|
||||
void ipu3_mmu_suspend(struct ipu3_mmu_info *info);
|
||||
void ipu3_mmu_resume(struct ipu3_mmu_info *info);
|
||||
|
||||
int ipu3_mmu_map(struct ipu3_mmu_info *info, unsigned long iova,
|
||||
phys_addr_t paddr, size_t size);
|
||||
size_t ipu3_mmu_unmap(struct ipu3_mmu_info *info, unsigned long iova,
|
||||
size_t size);
|
||||
size_t ipu3_mmu_map_sg(struct ipu3_mmu_info *info, unsigned long iova,
|
||||
struct scatterlist *sg, unsigned int nents);
|
||||
#endif
|
||||
Loading…
Reference in New Issue