[SERIAL] Add support for more Connect Tech PCI serial boards
I've also fixed the sort-ordering comments on this naming convention. Signed-off-by: Stuart MacDonald <stuartm@connecttech.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Gareth Howlett
Russell King
parent
2af7cd68f1
commit
26e92861be
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@ -853,14 +853,15 @@ get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
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* driver_data member.
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*
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* The makeup of these names are:
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* pbn_bn{_bt}_n_baud
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* pbn_bn{_bt}_n_baud{_offsetinhex}
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*
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* bn = PCI BAR number
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* bt = Index using PCI BARs
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* n = number of serial ports
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* baud = baud rate
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* bn = PCI BAR number
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* bt = Index using PCI BARs
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* n = number of serial ports
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* baud = baud rate
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* offsetinhex = offset for each sequential port (in hex)
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*
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* This table is sorted by (in order): baud, bt, bn, n.
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* This table is sorted by (in order): bn, bt, baud, offsetindex, n.
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*
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* Please note: in theory if n = 1, _bt infix should make no difference.
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* ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
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@ -881,6 +882,13 @@ enum pci_board_num_t {
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pbn_b0_4_1152000,
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pbn_b0_2_1843200,
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pbn_b0_4_1843200,
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pbn_b0_2_1843200_200,
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pbn_b0_4_1843200_200,
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pbn_b0_8_1843200_200,
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pbn_b0_bt_1_115200,
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pbn_b0_bt_2_115200,
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pbn_b0_bt_8_115200,
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@ -904,6 +912,8 @@ enum pci_board_num_t {
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pbn_b1_4_921600,
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pbn_b1_8_921600,
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pbn_b1_2_1250000,
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pbn_b1_bt_2_921600,
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pbn_b1_1_1382400,
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@ -1029,6 +1039,38 @@ static struct pciserial_board pci_boards[] __devinitdata = {
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.uart_offset = 8,
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},
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[pbn_b0_2_1843200] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 1843200,
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.uart_offset = 8,
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},
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[pbn_b0_4_1843200] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 1843200,
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.uart_offset = 8,
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},
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[pbn_b0_2_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_4_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_8_1843200_200] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 1843200,
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.uart_offset = 0x200,
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},
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[pbn_b0_bt_1_115200] = {
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.flags = FL_BASE0|FL_BASE_BARS,
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.num_ports = 1,
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@ -1141,6 +1183,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
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.base_baud = 921600,
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.uart_offset = 8,
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},
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[pbn_b1_2_1250000] = {
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.flags = FL_BASE1,
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.num_ports = 2,
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.base_baud = 1250000,
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.uart_offset = 8,
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},
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[pbn_b1_bt_2_921600] = {
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.flags = FL_BASE1|FL_BASE_BARS,
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@ -1801,6 +1849,66 @@ static struct pci_device_id serial_pci_tbl[] = {
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
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pbn_b1_4_921600 },
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{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
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pbn_b1_2_1250000 },
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{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
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pbn_b0_2_1843200 },
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{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
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pbn_b0_4_1843200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
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pbn_b0_2_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
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pbn_b0_4_1843200_200 },
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{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
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PCI_SUBVENDOR_ID_CONNECT_TECH,
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PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
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pbn_b0_8_1843200_200 },
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{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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@ -1567,6 +1567,23 @@
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331
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#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332
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#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2
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