OMAP4: DSS2: HDMI: HDMI driver header file addition
Adding the hdmi interface driver header file (hdmi.h) to the dss driver. Register and structure declaration done here. Signed-off-by: Mythri P K <mythripk@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Mythri P K
Tomi Valkeinen
parent
d3862610c9
commit
26adeece88
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/*
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* hdmi.h
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*
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* HDMI driver definition for TI OMAP4 processors.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _OMAP4_DSS_HDMI_H_
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#define _OMAP4_DSS_HDMI_H_
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#include <linux/string.h>
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#include <plat/display.h>
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#define HDMI_WP 0x0
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#define HDMI_CORE_SYS 0x400
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#define HDMI_CORE_AV 0x900
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#define HDMI_PLLCTRL 0x200
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#define HDMI_PHY 0x300
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struct hdmi_reg { u16 idx; };
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#define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
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/* HDMI Wrapper */
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#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx)
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#define HDMI_WP_REVISION HDMI_WP_REG(0x0)
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#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10)
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#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24)
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#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28)
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#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40)
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#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C)
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#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50)
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#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60)
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#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68)
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#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C)
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#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70)
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/* HDMI IP Core System */
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#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx)
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#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0)
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#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8)
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#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC)
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#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10)
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#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14)
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#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20)
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#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24)
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#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124)
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#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128)
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#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0)
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#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4)
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#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8)
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#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC)
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#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0)
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#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4)
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#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208)
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#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8)
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#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC)
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#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0)
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#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8)
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#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC)
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#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0)
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#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4)
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#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
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#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
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#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
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#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
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/* HDMI DDC E-DID */
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#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC)
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#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8)
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#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4)
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#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC)
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#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0)
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#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4)
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#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0)
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#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8)
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/* HDMI IP Core Audio Video */
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#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx)
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#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC)
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#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4)
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#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8)
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#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC)
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#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100)
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#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104)
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#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108)
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#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C)
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#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110)
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#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15)
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#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190)
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#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27)
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#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290)
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#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27)
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#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300)
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#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31)
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#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380)
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#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31)
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#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4)
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#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8)
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#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC)
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#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10)
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#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14)
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#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18)
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#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C)
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#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20)
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#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24)
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#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28)
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#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C)
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#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50)
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#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54)
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#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60)
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#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64)
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#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C)
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#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70)
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#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74)
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#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78)
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#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C)
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#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80)
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#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84)
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#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88)
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#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C)
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#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90)
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#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC)
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#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0)
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC)
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0)
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#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4)
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#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0)
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#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4)
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#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8)
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#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC)
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#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100)
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#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104)
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#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108)
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#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C)
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#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180)
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#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184)
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#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188)
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#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C)
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#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280)
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#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284)
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#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288)
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#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C)
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#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C)
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#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC)
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#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
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#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
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/* PLL */
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#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx)
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#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0)
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#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4)
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#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8)
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#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC)
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#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10)
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#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14)
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#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20)
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/* HDMI PHY */
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#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx)
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#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0)
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#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4)
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#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8)
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#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC)
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/* HDMI EDID Length */
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#define HDMI_EDID_MAX_LENGTH 256
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#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
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#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
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#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
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#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
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#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
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#define OMAP_HDMI_TIMINGS_NB 34
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#define REG_FLD_MOD(idx, val, start, end) \
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hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end))
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#define REG_GET(idx, start, end) \
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FLD_GET(hdmi_read_reg(idx), start, end)
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/* HDMI timing structure */
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struct hdmi_timings {
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struct omap_video_timings timings;
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int vsync_pol;
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int hsync_pol;
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};
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enum hdmi_phy_pwr {
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HDMI_PHYPWRCMD_OFF = 0,
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HDMI_PHYPWRCMD_LDOON = 1,
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HDMI_PHYPWRCMD_TXON = 2
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};
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enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_ALLOFF = 0,
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HDMI_PLLPWRCMD_PLLONLY = 1,
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HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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enum hdmi_core_inputbus_width {
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HDMI_INPUT_8BIT = 0,
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HDMI_INPUT_10BIT = 1,
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HDMI_INPUT_12BIT = 2
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};
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enum hdmi_core_dither_trunc {
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HDMI_OUTPUTTRUNCATION_8BIT = 0,
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HDMI_OUTPUTTRUNCATION_10BIT = 1,
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HDMI_OUTPUTTRUNCATION_12BIT = 2,
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HDMI_OUTPUTDITHER_8BIT = 3,
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HDMI_OUTPUTDITHER_10BIT = 4,
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HDMI_OUTPUTDITHER_12BIT = 5
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};
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enum hdmi_core_deepcolor_ed {
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HDMI_DEEPCOLORPACKECTDISABLE = 0,
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HDMI_DEEPCOLORPACKECTENABLE = 1
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};
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enum hdmi_core_packet_mode {
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HDMI_PACKETMODERESERVEDVALUE = 0,
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HDMI_PACKETMODE24BITPERPIXEL = 4,
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HDMI_PACKETMODE30BITPERPIXEL = 5,
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HDMI_PACKETMODE36BITPERPIXEL = 6,
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HDMI_PACKETMODE48BITPERPIXEL = 7
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};
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enum hdmi_core_hdmi_dvi {
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HDMI_DVI = 0,
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HDMI_HDMI = 1
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};
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enum hdmi_core_tclkselclkmult {
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HDMI_FPLL05IDCK = 0,
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HDMI_FPLL10IDCK = 1,
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HDMI_FPLL20IDCK = 2,
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HDMI_FPLL40IDCK = 3
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};
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enum hdmi_core_packet_ctrl {
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HDMI_PACKETENABLE = 1,
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HDMI_PACKETDISABLE = 0,
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HDMI_PACKETREPEATON = 1,
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HDMI_PACKETREPEATOFF = 0
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};
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/* INFOFRAME_AVI_ definitions */
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enum hdmi_core_infoframe {
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HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
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HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
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HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
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HDMI_INFOFRAME_AVI_DB1B_NO = 0,
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HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
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HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
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HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
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HDMI_INFOFRAME_AVI_DB1S_0 = 0,
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HDMI_INFOFRAME_AVI_DB1S_1 = 1,
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HDMI_INFOFRAME_AVI_DB1S_2 = 2,
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HDMI_INFOFRAME_AVI_DB2C_NO = 0,
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HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
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HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
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HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
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HDMI_INFOFRAME_AVI_DB2M_NO = 0,
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HDMI_INFOFRAME_AVI_DB2M_43 = 1,
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HDMI_INFOFRAME_AVI_DB2M_169 = 2,
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HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
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HDMI_INFOFRAME_AVI_DB2R_43 = 9,
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HDMI_INFOFRAME_AVI_DB2R_169 = 10,
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HDMI_INFOFRAME_AVI_DB2R_149 = 11,
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HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
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HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
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HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
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HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
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HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
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HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
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HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
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HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
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HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
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HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
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HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
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HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
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HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
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HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
|
||||
HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
|
||||
HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
|
||||
HDMI_INFOFRAME_AVI_DB5PR_10 = 9
|
||||
};
|
||||
|
||||
enum hdmi_packing_mode {
|
||||
HDMI_PACK_10b_RGB_YUV444 = 0,
|
||||
HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
|
||||
HDMI_PACK_20b_YUV422 = 2,
|
||||
HDMI_PACK_ALREADYPACKED = 7
|
||||
};
|
||||
|
||||
struct hdmi_core_video_config {
|
||||
enum hdmi_core_inputbus_width ip_bus_width;
|
||||
enum hdmi_core_dither_trunc op_dither_truc;
|
||||
enum hdmi_core_deepcolor_ed deep_color_pkt;
|
||||
enum hdmi_core_packet_mode pkt_mode;
|
||||
enum hdmi_core_hdmi_dvi hdmi_dvi;
|
||||
enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
|
||||
};
|
||||
|
||||
/*
|
||||
* Refer to section 8.2 in HDMI 1.3 specification for
|
||||
* details about infoframe databytes
|
||||
*/
|
||||
struct hdmi_core_infoframe_avi {
|
||||
u8 db1_format;
|
||||
/* Y0, Y1 rgb,yCbCr */
|
||||
u8 db1_active_info;
|
||||
/* A0 Active information Present */
|
||||
u8 db1_bar_info_dv;
|
||||
/* B0, B1 Bar info data valid */
|
||||
u8 db1_scan_info;
|
||||
/* S0, S1 scan information */
|
||||
u8 db2_colorimetry;
|
||||
/* C0, C1 colorimetry */
|
||||
u8 db2_aspect_ratio;
|
||||
/* M0, M1 Aspect ratio (4:3, 16:9) */
|
||||
u8 db2_active_fmt_ar;
|
||||
/* R0...R3 Active format aspect ratio */
|
||||
u8 db3_itc;
|
||||
/* ITC IT content. */
|
||||
u8 db3_ec;
|
||||
/* EC0, EC1, EC2 Extended colorimetry */
|
||||
u8 db3_q_range;
|
||||
/* Q1, Q0 Quantization range */
|
||||
u8 db3_nup_scaling;
|
||||
/* SC1, SC0 Non-uniform picture scaling */
|
||||
u8 db4_videocode;
|
||||
/* VIC0..6 Video format identification */
|
||||
u8 db5_pixel_repeat;
|
||||
/* PR0..PR3 Pixel repetition factor */
|
||||
u16 db6_7_line_eoftop;
|
||||
/* Line number end of top bar */
|
||||
u16 db8_9_line_sofbottom;
|
||||
/* Line number start of bottom bar */
|
||||
u16 db10_11_pixel_eofleft;
|
||||
/* Pixel number end of left bar */
|
||||
u16 db12_13_pixel_sofright;
|
||||
/* Pixel number start of right bar */
|
||||
};
|
||||
|
||||
struct hdmi_core_packet_enable_repeat {
|
||||
u32 audio_pkt;
|
||||
u32 audio_pkt_repeat;
|
||||
u32 avi_infoframe;
|
||||
u32 avi_infoframe_repeat;
|
||||
u32 gen_cntrl_pkt;
|
||||
u32 gen_cntrl_pkt_repeat;
|
||||
u32 generic_pkt;
|
||||
u32 generic_pkt_repeat;
|
||||
};
|
||||
|
||||
struct hdmi_video_format {
|
||||
enum hdmi_packing_mode packing_mode;
|
||||
u32 y_res; /* Line per panel */
|
||||
u32 x_res; /* pixel per line */
|
||||
};
|
||||
|
||||
struct hdmi_video_interface {
|
||||
int vsp; /* Vsync polarity */
|
||||
int hsp; /* Hsync polarity */
|
||||
int interlacing;
|
||||
int tm; /* Timing mode */
|
||||
};
|
||||
|
||||
struct hdmi_cm {
|
||||
int code;
|
||||
int mode;
|
||||
};
|
||||
|
||||
struct hdmi_config {
|
||||
struct hdmi_timings timings;
|
||||
u16 interlace;
|
||||
struct hdmi_cm cm;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue