iio: adc: aspeed: completes the bitfield declare.
This patch completes the declare of ADC register bitfields and uses the same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space alignment of the codes. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210831071458.2334-4-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -3,6 +3,7 @@
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* Aspeed AST2400/2500 ADC
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*
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* Copyright (C) 2017 Google, Inc.
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* Copyright (C) 2021 Aspeed Technology Inc.
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*/
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#include <linux/clk.h>
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@ -16,6 +17,7 @@
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/bitfield.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/driver.h>
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@ -28,15 +30,39 @@
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#define ASPEED_REG_INTERRUPT_CONTROL 0x04
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#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
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#define ASPEED_REG_CLOCK_CONTROL 0x0C
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#define ASPEED_REG_MAX 0xC0
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#define ASPEED_REG_COMPENSATION_TRIM 0xC4
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/*
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* The register offset between 0xC8~0xCC can be read and won't affect the
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* hardware logic in each version of ADC.
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*/
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#define ASPEED_REG_MAX 0xD0
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#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
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#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
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#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
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#define ASPEED_ENGINE_ENABLE BIT(0)
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#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
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#define ASPEED_ADC_ENGINE_ENABLE BIT(0)
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#define ASPEED_ADC_OP_MODE GENMASK(3, 1)
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#define ASPEED_ADC_OP_MODE_PWR_DOWN 0
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#define ASPEED_ADC_OP_MODE_STANDBY 1
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#define ASPEED_ADC_OP_MODE_NORMAL 7
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#define ASPEED_ADC_CTRL_COMPENSATION BIT(4)
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#define ASPEED_ADC_AUTO_COMPENSATION BIT(5)
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/*
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* Bit 6 determines not only the reference voltage range but also the dividing
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* circuit for battery sensing.
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*/
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#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6)
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#define ASPEED_ADC_REF_VOLTAGE_2500mV 0
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#define ASPEED_ADC_REF_VOLTAGE_1200mV 1
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#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2
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#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3
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#define ASPEED_ADC_BAT_SENSING_DIV BIT(6)
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#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0
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#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1
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#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
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#define ASPEED_ADC_CH7_MODE BIT(12)
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#define ASPEED_ADC_CH7_NORMAL 0
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#define ASPEED_ADC_CH7_BAT 1
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#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13)
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#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16)
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#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch))
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#define ASPEED_ADC_INIT_POLLING_TIME 500
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#define ASPEED_ADC_INIT_TIMEOUT 500000
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@ -226,7 +252,9 @@ static int aspeed_adc_probe(struct platform_device *pdev)
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if (model_data->wait_init_sequence) {
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/* Enable engine in normal mode. */
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writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
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writel(FIELD_PREP(ASPEED_ADC_OP_MODE,
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ASPEED_ADC_OP_MODE_NORMAL) |
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ASPEED_ADC_ENGINE_ENABLE,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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/* Wait for initial sequence complete. */
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@ -245,10 +273,12 @@ static int aspeed_adc_probe(struct platform_device *pdev)
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if (ret)
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goto clk_enable_error;
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adc_engine_control_reg_val = GENMASK(31, 16) |
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ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
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adc_engine_control_reg_val =
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ASPEED_ADC_CTRL_CHANNEL |
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FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
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ASPEED_ADC_ENGINE_ENABLE;
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writel(adc_engine_control_reg_val,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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data->base + ASPEED_REG_ENGINE_CONTROL);
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model_data = of_device_get_match_data(&pdev->dev);
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indio_dev->name = model_data->model_name;
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@ -264,8 +294,8 @@ static int aspeed_adc_probe(struct platform_device *pdev)
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return 0;
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iio_register_error:
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writel(ASPEED_OPERATION_MODE_POWER_DOWN,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
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data->base + ASPEED_REG_ENGINE_CONTROL);
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clk_disable_unprepare(data->clk_scaler->clk);
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clk_enable_error:
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poll_timeout_error:
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@ -283,8 +313,8 @@ static int aspeed_adc_remove(struct platform_device *pdev)
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struct aspeed_adc_data *data = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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writel(ASPEED_OPERATION_MODE_POWER_DOWN,
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data->base + ASPEED_REG_ENGINE_CONTROL);
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writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
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data->base + ASPEED_REG_ENGINE_CONTROL);
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clk_disable_unprepare(data->clk_scaler->clk);
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reset_control_assert(data->rst);
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clk_hw_unregister_divider(data->clk_scaler);
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