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drm/msm/dsi: replace PHY's init callback with configurable data 

DSI PHY init callback would either map dsi_phy_regulator or dsi_phy_lane
depending on the PHY type. Replace those callbacks with configuration
options governing mapping those regions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-4-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Dmitry Baryshkov 2021-03-31 13:57:14 +03:00 committed by Rob Clark
parent f4b43ac0b0
commit 266a4e58a1
8 changed files with 31 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
View File

@ -637,24 +637,6 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
return -EINVAL; return -EINVAL;
} }
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
int ret = 0;
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
"DSI_PHY_REG");
if (IS_ERR(phy->reg_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
__func__);
ret = -ENOMEM;
goto fail;
}
fail:
return ret;
}
static int dsi_phy_driver_probe(struct platform_device *pdev) static int dsi_phy_driver_probe(struct platform_device *pdev)
{ {
struct msm_dsi_phy *phy; struct msm_dsi_phy *phy;
@ -691,6 +673,24 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail; goto fail;
} }
if (phy->cfg->has_phy_lane) {
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
if (IS_ERR(phy->lane_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
ret = -ENOMEM;
goto fail;
}
}
if (phy->cfg->has_phy_regulator) {
phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
if (IS_ERR(phy->reg_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
ret = -ENOMEM;
goto fail;
}
}
ret = dsi_phy_regulator_init(phy); ret = dsi_phy_regulator_init(phy);
if (ret) if (ret)
goto fail; goto fail;
@ -702,12 +702,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
goto fail; goto fail;
} }
if (phy->cfg->ops.init) {
ret = phy->cfg->ops.init(phy);
if (ret)
goto fail;
}
/* PLL init will call into clk_register which requires /* PLL init will call into clk_register which requires
* register access, so we need to enable power and ahb clock. * register access, so we need to enable power and ahb clock.
*/ */

4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
View File

@ -17,7 +17,6 @@
#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0) #define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
struct msm_dsi_phy_ops { struct msm_dsi_phy_ops {
int (*init) (struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id, int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
struct msm_dsi_phy_clk_request *clk_req); struct msm_dsi_phy_clk_request *clk_req);
void (*disable)(struct msm_dsi_phy *phy); void (*disable)(struct msm_dsi_phy *phy);
@ -37,6 +36,8 @@ struct msm_dsi_phy_cfg {
const resource_size_t io_start[DSI_MAX]; const resource_size_t io_start[DSI_MAX];
const int num_dsi_phy; const int num_dsi_phy;
const int quirks; const int quirks;
bool has_phy_regulator;
bool has_phy_lane;
}; };
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
@ -106,7 +107,6 @@ int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
struct msm_dsi_phy_clk_request *clk_req); struct msm_dsi_phy_clk_request *clk_req);
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask); u32 bit_mask);
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
#endif /* __DSI_PHY_H__ */ #endif /* __DSI_PHY_H__ */

19
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
View File

@ -216,24 +216,10 @@ static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
DBG("DSI%d PHY disabled", phy->id); DBG("DSI%d PHY disabled", phy->id);
} }
static int dsi_10nm_phy_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
"DSI_PHY_LANE");
if (IS_ERR(phy->lane_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
__func__);
return -ENOMEM;
}
return 0;
}
const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.type = MSM_DSI_PHY_10NM, .type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -243,7 +229,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.ops = { .ops = {
.enable = dsi_10nm_phy_enable, .enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable, .disable = dsi_10nm_phy_disable,
.init = dsi_10nm_phy_init,
}, },
.io_start = { 0xae94400, 0xae96400 }, .io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
@ -252,6 +237,7 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.type = MSM_DSI_PHY_10NM, .type = MSM_DSI_PHY_10NM,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -261,7 +247,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.ops = { .ops = {
.enable = dsi_10nm_phy_enable, .enable = dsi_10nm_phy_enable,
.disable = dsi_10nm_phy_disable, .disable = dsi_10nm_phy_disable,
.init = dsi_10nm_phy_init,
}, },
.io_start = { 0xc994400, 0xc996400 }, .io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,

19
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
View File

@ -129,24 +129,10 @@ static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
wmb(); wmb();
} }
static int dsi_14nm_phy_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
"DSI_PHY_LANE");
if (IS_ERR(phy->lane_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
__func__);
return -ENOMEM;
}
return 0;
}
const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.type = MSM_DSI_PHY_14NM, .type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -156,7 +142,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
.ops = { .ops = {
.enable = dsi_14nm_phy_enable, .enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable, .disable = dsi_14nm_phy_disable,
.init = dsi_14nm_phy_init,
}, },
.io_start = { 0x994400, 0x996400 }, .io_start = { 0x994400, 0x996400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
@ -165,6 +150,7 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.type = MSM_DSI_PHY_14NM, .type = MSM_DSI_PHY_14NM,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -174,7 +160,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
.ops = { .ops = {
.enable = dsi_14nm_phy_enable, .enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable, .disable = dsi_14nm_phy_disable,
.init = dsi_14nm_phy_init,
}, },
.io_start = { 0xc994400, 0xc996000 }, .io_start = { 0xc994400, 0xc996000 },
.num_dsi_phy = 2, .num_dsi_phy = 2,

2
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
View File

@ -127,6 +127,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
.type = MSM_DSI_PHY_20NM, .type = MSM_DSI_PHY_20NM,
.src_pll_truthtable = { {false, true}, {false, true} }, .src_pll_truthtable = { {false, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = { .reg_cfg = {
.num = 2, .num = 2,
.regs = { .regs = {
@ -137,7 +138,6 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
.ops = { .ops = {
.enable = dsi_20nm_phy_enable, .enable = dsi_20nm_phy_enable,
.disable = dsi_20nm_phy_disable, .disable = dsi_20nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0xfd998500, 0xfd9a0500 }, .io_start = { 0xfd998500, 0xfd9a0500 },
.num_dsi_phy = 2, .num_dsi_phy = 2,

6
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
View File

@ -153,6 +153,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.type = MSM_DSI_PHY_28NM_HPM, .type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} }, .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -162,7 +163,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0xfd922b00, 0xfd923100 }, .io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
@ -171,6 +171,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.type = MSM_DSI_PHY_28NM_HPM, .type = MSM_DSI_PHY_28NM_HPM,
.src_pll_truthtable = { {true, true}, {false, true} }, .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -180,7 +181,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0x1a94400, 0x1a96400 }, .io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
@ -189,6 +189,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.type = MSM_DSI_PHY_28NM_LP, .type = MSM_DSI_PHY_28NM_LP,
.src_pll_truthtable = { {true, true}, {true, true} }, .src_pll_truthtable = { {true, true}, {true, true} },
.has_phy_regulator = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -198,7 +199,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0x1a98500 }, .io_start = { 0x1a98500 },
.num_dsi_phy = 1, .num_dsi_phy = 1,

2
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
View File

@ -176,6 +176,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.type = MSM_DSI_PHY_28NM_8960, .type = MSM_DSI_PHY_28NM_8960,
.src_pll_truthtable = { {true, true}, {false, true} }, .src_pll_truthtable = { {true, true}, {false, true} },
.has_phy_regulator = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -185,7 +186,6 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
.ops = { .ops = {
.enable = dsi_28nm_phy_enable, .enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable, .disable = dsi_28nm_phy_disable,
.init = msm_dsi_phy_init_common,
}, },
.io_start = { 0x4700300, 0x5800300 }, .io_start = { 0x4700300, 0x5800300 },
.num_dsi_phy = 2, .num_dsi_phy = 2,

19
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
View File

@ -224,24 +224,10 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
DBG("DSI%d PHY disabled", phy->id); DBG("DSI%d PHY disabled", phy->id);
} }
static int dsi_7nm_phy_init(struct msm_dsi_phy *phy)
{
struct platform_device *pdev = phy->pdev;
phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
"DSI_PHY_LANE");
if (IS_ERR(phy->lane_base)) {
DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
__func__);
return -ENOMEM;
}
return 0;
}
const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.type = MSM_DSI_PHY_7NM_V4_1, .type = MSM_DSI_PHY_7NM_V4_1,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -251,7 +237,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
.ops = { .ops = {
.enable = dsi_7nm_phy_enable, .enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable, .disable = dsi_7nm_phy_disable,
.init = dsi_7nm_phy_init,
}, },
.io_start = { 0xae94400, 0xae96400 }, .io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
@ -260,6 +245,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.type = MSM_DSI_PHY_7NM, .type = MSM_DSI_PHY_7NM,
.src_pll_truthtable = { {false, false}, {true, false} }, .src_pll_truthtable = { {false, false}, {true, false} },
.has_phy_lane = true,
.reg_cfg = { .reg_cfg = {
.num = 1, .num = 1,
.regs = { .regs = {
@ -269,7 +255,6 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
.ops = { .ops = {
.enable = dsi_7nm_phy_enable, .enable = dsi_7nm_phy_enable,
.disable = dsi_7nm_phy_disable, .disable = dsi_7nm_phy_disable,
.init = dsi_7nm_phy_init,
}, },
.io_start = { 0xae94400, 0xae96400 }, .io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,