ASoC: tlv320aic31xx: Add support for pll_r coefficient
When the clock used by the codec is BCLK, the operation parameters need to be calculated from input sample rate and format. Low frequency rates required different r multipliers, in order to achieve a higher PLL output frequency. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Link: https://lore.kernel.org/r/20211119153248.419802-3-ariel.dalessandro@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ariel D'Alessandro
Mark Brown
parent
7016fd940a
commit
2664b24a8c
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@ -180,6 +180,7 @@ struct aic31xx_priv {
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struct aic31xx_rate_divs {
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u32 mclk_p;
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u32 rate;
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u8 pll_r;
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u8 pll_j;
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u16 pll_d;
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u16 dosr;
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@ -192,51 +193,51 @@ struct aic31xx_rate_divs {
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/* ADC dividers can be disabled by configuring them to 0 */
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static const struct aic31xx_rate_divs aic31xx_divs[] = {
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/* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
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/* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */
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/* 8k rate */
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{12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
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{12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
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{12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},
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/* 11.025k rate */
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{12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
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{12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
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{12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},
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/* 16k rate */
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{12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
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{12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
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{12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},
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/* 22.05k rate */
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{12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
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{12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
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{12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},
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/* 32k rate */
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{12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
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{12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
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{12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},
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/* 44.1k rate */
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{12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
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{12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
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{12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},
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/* 48k rate */
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{12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
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{12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
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{12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},
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/* 88.2k rate */
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{12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
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{12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
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{12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},
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/* 96k rate */
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{12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
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{12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
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{12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2},
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/* 176.4k rate */
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{12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
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{12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
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{12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},
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/* 192k rate */
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{12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
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{12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
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{12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2},
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};
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static const char * const ldac_in_text[] = {
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@ -888,7 +889,7 @@ static int aic31xx_setup_pll(struct snd_soc_component *component,
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/* PLL configuration */
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snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
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(aic31xx->p_div << 4) | 0x01);
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(aic31xx->p_div << 4) | aic31xx_divs[i].pll_r);
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snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
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snd_soc_component_write(component, AIC31XX_PLLDMSB,
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