Merge branch 'spi-5.3' into spi-linus
This commit is contained in:
commit
262a2f3345
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@ -31,7 +31,7 @@ properties:
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If that property is used, the number of chip selects will be
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increased automatically with max(cs-gpios, hardware chip selects).
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So if, for example, the controller has 2 CS lines, and the
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So if, for example, the controller has 4 CS lines, and the
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cs-gpios looks like this
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cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
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@ -343,7 +343,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
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{
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int bpc = 0, bpp = 0;
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u8 command = op->cmd.opcode;
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int width = op->cmd.buswidth ? op->cmd.buswidth : SPI_NBITS_SINGLE;
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int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
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int addrlen = op->addr.nbytes;
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int flex_mode = 1;
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@ -981,7 +981,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
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if (mspi_read)
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return bcm_qspi_mspi_exec_mem_op(spi, op);
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ret = bcm_qspi_bspi_set_mode(qspi, op, -1);
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ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
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if (!ret)
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ret = bcm_qspi_bspi_exec_mem_op(spi, op);
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@ -319,6 +319,13 @@ static void bcm2835_spi_reset_hw(struct spi_controller *ctlr)
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BCM2835_SPI_CS_INTD |
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BCM2835_SPI_CS_DMAEN |
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BCM2835_SPI_CS_TA);
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/*
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* Transmission sometimes breaks unless the DONE bit is written at the
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* end of every transfer. The spec says it's a RO bit. Either the
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* spec is wrong and the bit is actually of type RW1C, or it's a
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* hardware erratum.
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*/
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cs |= BCM2835_SPI_CS_DONE;
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/* and reset RX/TX FIFOS */
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cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
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@ -477,7 +484,9 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
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bcm2835_wr_fifo_count(bs, bs->rx_prologue);
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bcm2835_wait_tx_fifo_empty(bs);
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bcm2835_rd_fifo_count(bs, bs->rx_prologue);
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bcm2835_spi_reset_hw(ctlr);
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bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
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| BCM2835_SPI_CS_CLEAR_TX
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| BCM2835_SPI_CS_DONE);
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dma_sync_single_for_device(ctlr->dma_rx->device->dev,
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sg_dma_address(&tfr->rx_sg.sgl[0]),
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@ -498,7 +507,8 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
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| BCM2835_SPI_CS_DMAEN);
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bcm2835_wr_fifo_count(bs, tx_remaining);
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bcm2835_wait_tx_fifo_empty(bs);
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bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX);
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bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
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| BCM2835_SPI_CS_DONE);
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}
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if (likely(!bs->tx_spillover)) {
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@ -19,6 +19,7 @@ struct spi_pci_desc {
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int (*setup)(struct dw_spi *);
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u16 num_cs;
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u16 bus_num;
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u32 max_freq;
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};
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static struct spi_pci_desc spi_pci_mid_desc_1 = {
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@ -33,6 +34,12 @@ static struct spi_pci_desc spi_pci_mid_desc_2 = {
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.bus_num = 1,
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};
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static struct spi_pci_desc spi_pci_ehl_desc = {
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.num_cs = 1,
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.bus_num = -1,
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.max_freq = 100000000,
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};
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static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct dw_spi *dws;
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@ -65,6 +72,7 @@ static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (desc) {
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dws->num_cs = desc->num_cs;
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dws->bus_num = desc->bus_num;
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dws->max_freq = desc->max_freq;
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if (desc->setup) {
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ret = desc->setup(dws);
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@ -125,8 +133,14 @@ static const struct pci_device_id pci_ids[] = {
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{ PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
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/* Intel MID platform SPI controller 2 */
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{ PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
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/* Intel Elkhart Lake PSE SPI controllers */
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{ PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
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{},
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static struct pci_driver dw_spi_driver = {
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.name = DRIVER_NAME,
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@ -886,11 +886,13 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
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trans_mode);
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}
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}
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}
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static const struct of_device_id fsl_dspi_dt_ids[] = {
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{ .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
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{ .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
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@ -214,6 +214,7 @@ static void uniphier_spi_setup_transfer(struct spi_device *spi,
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if (!priv->is_save_param || priv->mode != spi->mode) {
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uniphier_spi_set_mode(spi);
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priv->mode = spi->mode;
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priv->is_save_param = false;
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}
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
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@ -695,7 +695,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
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ctlr->setup = zynq_qspi_setup_op;
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ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
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ctlr->dev.of_node = np;
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ret = spi_register_controller(ctlr);
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ret = devm_spi_register_controller(&pdev->dev, ctlr);
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if (ret) {
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dev_err(&pdev->dev, "spi_register_master failed\n");
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goto clk_dis_all;
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