liquidio: Host queue mapping changes
This patch is to allocate the input queues based on Numa node in tx path and queue mapping changes based on the mapping info provided by firmware. Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raghu Vatsavayi
David S. Miller
parent
ddc173a688
commit
26236fa9a1
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@ -653,7 +653,7 @@ static int lio_get_intr_coalesce(struct net_device *netdev,
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intrmod_cfg->intrmod_mincnt_trigger;
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}
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iq = oct->instr_queue[lio->linfo.txpciq[0]];
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iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no];
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intr_coal->tx_max_coalesced_frames = iq->fill_threshold;
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break;
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@ -859,7 +859,7 @@ static int lio_set_intr_coalesce(struct net_device *netdev,
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if ((intr_coal->tx_max_coalesced_frames >= CN6XXX_DB_MIN) &&
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(intr_coal->tx_max_coalesced_frames <= CN6XXX_DB_MAX)) {
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for (j = 0; j < lio->linfo.num_txpciq; j++) {
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q_no = lio->linfo.txpciq[j];
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q_no = lio->linfo.txpciq[j].s.q_no;
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oct->instr_queue[q_no]->fill_threshold =
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intr_coal->tx_max_coalesced_frames;
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}
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@ -682,7 +682,8 @@ static inline void txqs_wake(struct net_device *netdev)
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int i;
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for (i = 0; i < netdev->num_tx_queues; i++)
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netif_wake_subqueue(netdev, i);
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if (__netif_subqueue_stopped(netdev, i))
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netif_wake_subqueue(netdev, i);
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} else {
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netif_wake_queue(netdev);
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}
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@ -752,11 +753,14 @@ static inline int check_txq_status(struct lio *lio)
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/* check each sub-queue state */
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for (q = 0; q < numqs; q++) {
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iq = lio->linfo.txpciq[q & (lio->linfo.num_txpciq - 1)];
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iq = lio->linfo.txpciq[q %
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(lio->linfo.num_txpciq)].s.q_no;
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if (octnet_iq_is_full(lio->oct_dev, iq))
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continue;
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wake_q(lio->netdev, q);
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ret_val++;
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if (__netif_subqueue_stopped(lio->netdev, q)) {
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wake_q(lio->netdev, q);
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ret_val++;
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}
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}
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} else {
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if (octnet_iq_is_full(lio->oct_dev, lio->txq))
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@ -1230,7 +1234,8 @@ static int liquidio_stop_nic_module(struct octeon_device *oct)
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for (i = 0; i < oct->ifcount; i++) {
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lio = GET_LIO(oct->props[i].netdev);
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for (j = 0; j < lio->linfo.num_rxpciq; j++)
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octeon_unregister_droq_ops(oct, lio->linfo.rxpciq[j]);
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octeon_unregister_droq_ops(oct,
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lio->linfo.rxpciq[j].s.q_no);
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}
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for (i = 0; i < oct->ifcount; i++)
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@ -1337,14 +1342,17 @@ static inline int check_txq_state(struct lio *lio, struct sk_buff *skb)
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if (netif_is_multiqueue(lio->netdev)) {
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q = skb->queue_mapping;
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iq = lio->linfo.txpciq[(q & (lio->linfo.num_txpciq - 1))];
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iq = lio->linfo.txpciq[(q % (lio->linfo.num_txpciq))].s.q_no;
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} else {
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iq = lio->txq;
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q = iq;
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}
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if (octnet_iq_is_full(lio->oct_dev, iq))
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return 0;
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wake_q(lio->netdev, q);
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if (__netif_subqueue_stopped(lio->netdev, q))
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wake_q(lio->netdev, q);
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return 1;
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}
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@ -1743,14 +1751,13 @@ static void if_cfg_callback(struct octeon_device *oct,
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static u16 select_q(struct net_device *dev, struct sk_buff *skb,
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void *accel_priv, select_queue_fallback_t fallback)
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{
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int qindex;
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u32 qindex = 0;
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struct lio *lio;
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lio = GET_LIO(dev);
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/* select queue on chosen queue_mapping or core */
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qindex = skb_rx_queue_recorded(skb) ?
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skb_get_rx_queue(skb) : smp_processor_id();
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return (u16)(qindex & (lio->linfo.num_txpciq - 1));
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qindex = skb_tx_hash(dev, skb);
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return (u16)(qindex % (lio->linfo.num_txpciq));
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}
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/** Routine to push packets arriving on Octeon interface upto network layer.
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@ -1789,6 +1796,8 @@ liquidio_push_packet(u32 octeon_id,
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skb->dev = netdev;
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skb_record_rx_queue(skb, droq->q_no);
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if (rh->r_dh.has_hwtstamp) {
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/* timestamp is included from the hardware at the
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* beginning of the packet.
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@ -1962,8 +1971,10 @@ static inline int setup_io_queues(struct octeon_device *octeon_dev,
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/* set up DROQs. */
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for (q = 0; q < lio->linfo.num_rxpciq; q++) {
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q_no = lio->linfo.rxpciq[q];
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q_no = lio->linfo.rxpciq[q].s.q_no;
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dev_dbg(&octeon_dev->pci_dev->dev,
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"setup_io_queues index:%d linfo.rxpciq.s.q_no:%d\n",
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q, q_no);
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retval = octeon_setup_droq(octeon_dev, q_no,
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CFG_GET_NUM_RX_DESCS_NIC_IF
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(octeon_get_conf(octeon_dev),
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@ -2341,7 +2352,7 @@ static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
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oct = lio->oct_dev;
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for (i = 0; i < lio->linfo.num_txpciq; i++) {
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iq_no = lio->linfo.txpciq[i];
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iq_no = lio->linfo.txpciq[i].s.q_no;
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iq_stats = &oct->instr_queue[iq_no]->stats;
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pkts += iq_stats->tx_done;
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drop += iq_stats->tx_dropped;
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@ -2357,7 +2368,7 @@ static struct net_device_stats *liquidio_get_stats(struct net_device *netdev)
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bytes = 0;
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for (i = 0; i < lio->linfo.num_rxpciq; i++) {
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oq_no = lio->linfo.rxpciq[i];
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oq_no = lio->linfo.rxpciq[i].s.q_no;
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oq_stats = &oct->droq[oq_no]->stats;
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pkts += oq_stats->rx_pkts_received;
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drop += (oq_stats->rx_dropped +
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@ -2670,7 +2681,7 @@ static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
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struct octnic_data_pkt ndata;
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struct octeon_device *oct;
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struct oct_iq_stats *stats;
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int cpu = 0, status = 0;
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int status = 0;
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int q_idx = 0, iq_no = 0;
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int xmit_more;
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u32 tag = 0;
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@ -2679,9 +2690,10 @@ static int liquidio_xmit(struct sk_buff *skb, struct net_device *netdev)
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oct = lio->oct_dev;
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if (netif_is_multiqueue(netdev)) {
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cpu = skb->queue_mapping;
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q_idx = (cpu & (lio->linfo.num_txpciq - 1));
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iq_no = lio->linfo.txpciq[q_idx];
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q_idx = skb->queue_mapping;
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q_idx = (q_idx % (lio->linfo.num_txpciq));
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tag = q_idx;
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iq_no = lio->linfo.txpciq[q_idx].s.q_no;
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} else {
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iq_no = lio->txq;
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}
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@ -3125,7 +3137,7 @@ static int setup_nic_devices(struct octeon_device *octeon_dev)
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struct liquidio_if_cfg_context *ctx;
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struct liquidio_if_cfg_resp *resp;
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struct octdev_props *props;
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int retval, num_iqueues, num_oqueues, q_no;
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int retval, num_iqueues, num_oqueues;
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u64 q_mask;
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int num_cpus = num_online_cpus();
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union oct_nic_if_cfg if_cfg;
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@ -3257,15 +3269,13 @@ static int setup_nic_devices(struct octeon_device *octeon_dev)
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q_mask = resp->cfg_info.oqmask;
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/* q_mask is 0-based and already verified mask is nonzero */
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for (j = 0; j < num_oqueues; j++) {
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q_no = __ffs64(q_mask);
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q_mask &= (~(1UL << q_no));
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lio->linfo.rxpciq[j] = q_no;
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lio->linfo.rxpciq[j].u64 =
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resp->cfg_info.linfo.rxpciq[j].u64;
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}
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q_mask = resp->cfg_info.iqmask;
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for (j = 0; j < num_iqueues; j++) {
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q_no = __ffs64(q_mask);
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q_mask &= (~(1UL << q_no));
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lio->linfo.txpciq[j] = q_no;
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lio->linfo.txpciq[j].u64 =
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resp->cfg_info.linfo.txpciq[j].u64;
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}
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lio->linfo.hw_addr = resp->cfg_info.linfo.hw_addr;
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lio->linfo.gmxport = resp->cfg_info.linfo.gmxport;
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@ -3306,6 +3316,11 @@ static int setup_nic_devices(struct octeon_device *octeon_dev)
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ether_addr_copy(netdev->dev_addr, mac);
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/* By default all interfaces on a single Octeon uses the same
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* tx and rx queues
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*/
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lio->txq = lio->linfo.txpciq[0].s.q_no;
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lio->rxq = lio->linfo.rxpciq[0].s.q_no;
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if (setup_io_queues(octeon_dev, netdev)) {
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dev_err(&octeon_dev->pci_dev->dev, "I/O queues creation failed\n");
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goto setup_nic_dev_fail;
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@ -3313,12 +3328,6 @@ static int setup_nic_devices(struct octeon_device *octeon_dev)
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ifstate_set(lio, LIO_IFSTATE_DROQ_OPS);
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/* By default all interfaces on a single Octeon uses the same
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* tx and rx queues
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*/
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lio->txq = lio->linfo.txpciq[0];
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lio->rxq = lio->linfo.rxpciq[0];
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lio->tx_qsize = octeon_get_tx_qsize(octeon_dev, lio->txq);
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lio->rx_qsize = octeon_get_rx_qsize(octeon_dev, lio->rxq);
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@ -516,6 +516,46 @@ union oct_link_status {
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} s;
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};
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/** The txpciq info passed to host from the firmware */
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union oct_txpciq {
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u64 u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 q_no:8;
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u64 port:8;
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u64 pkind:6;
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u64 use_qpg:1;
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u64 qpg:11;
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u64 reserved:30;
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#else
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u64 reserved:30;
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u64 qpg:11;
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u64 use_qpg:1;
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u64 pkind:6;
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u64 port:8;
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u64 q_no:8;
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#endif
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} s;
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};
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/** The rxpciq info passed to host from the firmware */
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union oct_rxpciq {
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u64 u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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u64 q_no:8;
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u64 reserved:56;
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#else
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u64 reserved:56;
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u64 q_no:8;
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#endif
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} s;
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};
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/** Information for a OCTEON ethernet interface shared between core & host. */
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struct oct_link_info {
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union oct_link_status link;
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@ -535,8 +575,8 @@ struct oct_link_info {
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u16 gmxport;
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#endif
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u8 txpciq[MAX_IOQS_PER_NICIF];
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u8 rxpciq[MAX_IOQS_PER_NICIF];
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union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
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union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
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};
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#define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
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@ -741,36 +741,43 @@ struct octeon_device *octeon_allocate_device(u32 pci_id,
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return oct;
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}
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/* this function is only for setting up the first queue */
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int octeon_setup_instr_queues(struct octeon_device *oct)
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{
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u32 i, num_iqs = 0;
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u32 num_iqs = 0;
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u32 num_descs = 0;
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u32 iq_no = 0;
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union oct_txpciq txpciq;
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int numa_node = cpu_to_node(iq_no % num_online_cpus());
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num_iqs = 1;
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/* this causes queue 0 to be default queue */
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if (OCTEON_CN6XXX(oct)) {
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num_iqs = 1;
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if (OCTEON_CN6XXX(oct))
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num_descs =
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CFG_GET_NUM_DEF_TX_DESCS(CHIP_FIELD(oct, cn6xxx, conf));
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}
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oct->num_iqs = 0;
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for (i = 0; i < num_iqs; i++) {
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oct->instr_queue[i] =
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oct->instr_queue[0] = vmalloc_node(sizeof(*oct->instr_queue[0]),
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numa_node);
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if (!oct->instr_queue[0])
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oct->instr_queue[0] =
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vmalloc(sizeof(struct octeon_instr_queue));
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if (!oct->instr_queue[i])
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return 1;
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memset(oct->instr_queue[i], 0,
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sizeof(struct octeon_instr_queue));
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oct->instr_queue[i]->app_ctx = (void *)(size_t)i;
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if (octeon_init_instr_queue(oct, i, num_descs))
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return 1;
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oct->num_iqs++;
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if (!oct->instr_queue[0])
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return 1;
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memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
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oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
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txpciq.u64 = 0;
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txpciq.s.q_no = iq_no;
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txpciq.s.use_qpg = 0;
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txpciq.s.qpg = 0;
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if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
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/* prevent memory leak */
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vfree(oct->instr_queue[0]);
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return 1;
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}
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oct->num_iqs++;
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return 0;
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}
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@ -81,8 +81,8 @@ struct octeon_instr_queue {
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/** Flag that indicates if the queue uses 64 byte commands. */
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u32 iqcmd_64B:1;
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/** Queue Number. */
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u32 iq_no:5;
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/** Queue info. */
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union oct_txpciq txpciq;
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u32 rsvd:17;
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@ -268,14 +268,15 @@ void octeon_free_soft_command(struct octeon_device *oct,
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/**
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* octeon_init_instr_queue()
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* @param octeon_dev - pointer to the octeon device structure.
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* @param iq_no - queue to be initialized (0 <= q_no <= 3).
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* @param txpciq - queue to be initialized (0 <= q_no <= 3).
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*
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* Called at driver init time for each input queue. iq_conf has the
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* configuration parameters for the queue.
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*
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* @return Success: 0 Failure: 1
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*/
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int octeon_init_instr_queue(struct octeon_device *octeon_dev, u32 iq_no,
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int octeon_init_instr_queue(struct octeon_device *octeon_dev,
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union oct_txpciq txpciq,
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u32 num_descs);
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/**
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@ -313,7 +314,7 @@ void octeon_prepare_soft_command(struct octeon_device *oct,
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int octeon_send_soft_command(struct octeon_device *oct,
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struct octeon_soft_command *sc);
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int octeon_setup_iq(struct octeon_device *oct, u32 iq_no,
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int octeon_setup_iq(struct octeon_device *oct, union oct_txpciq,
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u32 num_descs, void *app_ctx);
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#endif /* __OCTEON_IQ_H__ */
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@ -69,12 +69,16 @@ static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no)
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/* Return 0 on success, 1 on failure */
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int octeon_init_instr_queue(struct octeon_device *oct,
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u32 iq_no, u32 num_descs)
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union oct_txpciq txpciq,
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u32 num_descs)
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{
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struct octeon_instr_queue *iq;
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struct octeon_iq_config *conf = NULL;
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u32 iq_no = (u32)txpciq.s.q_no;
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u32 q_size;
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struct cavium_wq *db_wq;
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int orig_node = dev_to_node(&oct->pci_dev->dev);
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int numa_node = cpu_to_node(iq_no % num_online_cpus());
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if (OCTEON_CN6XXX(oct))
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conf = &(CFG_GET_IQ_CFG(CHIP_FIELD(oct, cn6xxx, conf)));
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@ -96,8 +100,13 @@ int octeon_init_instr_queue(struct octeon_device *oct,
|
|||
|
||||
iq = oct->instr_queue[iq_no];
|
||||
|
||||
set_dev_node(&oct->pci_dev->dev, numa_node);
|
||||
iq->base_addr = lio_dma_alloc(oct, q_size,
|
||||
(dma_addr_t *)&iq->base_addr_dma);
|
||||
set_dev_node(&oct->pci_dev->dev, orig_node);
|
||||
if (!iq->base_addr)
|
||||
iq->base_addr = lio_dma_alloc(oct, q_size,
|
||||
(dma_addr_t *)&iq->base_addr_dma);
|
||||
if (!iq->base_addr) {
|
||||
dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n",
|
||||
iq_no);
|
||||
|
|
@ -109,7 +118,11 @@ int octeon_init_instr_queue(struct octeon_device *oct,
|
|||
/* Initialize a list to holds requests that have been posted to Octeon
|
||||
* but has yet to be fetched by octeon
|
||||
*/
|
||||
iq->request_list = vmalloc(sizeof(*iq->request_list) * num_descs);
|
||||
iq->request_list = vmalloc_node((sizeof(*iq->request_list) * num_descs),
|
||||
numa_node);
|
||||
if (!iq->request_list)
|
||||
iq->request_list = vmalloc(sizeof(*iq->request_list) *
|
||||
num_descs);
|
||||
if (!iq->request_list) {
|
||||
lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
|
||||
dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n",
|
||||
|
|
@ -122,7 +135,7 @@ int octeon_init_instr_queue(struct octeon_device *oct,
|
|||
dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %llx count: %d\n",
|
||||
iq_no, iq->base_addr, iq->base_addr_dma, iq->max_count);
|
||||
|
||||
iq->iq_no = iq_no;
|
||||
iq->txpciq.u64 = txpciq.u64;
|
||||
iq->fill_threshold = (u32)conf->db_min;
|
||||
iq->fill_cnt = 0;
|
||||
iq->host_write_index = 0;
|
||||
|
|
@ -189,18 +202,25 @@ int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
|
|||
|
||||
/* Return 0 on success, 1 on failure */
|
||||
int octeon_setup_iq(struct octeon_device *oct,
|
||||
u32 iq_no,
|
||||
union oct_txpciq txpciq,
|
||||
u32 num_descs,
|
||||
void *app_ctx)
|
||||
{
|
||||
u32 iq_no = (u32)txpciq.s.q_no;
|
||||
int numa_node = cpu_to_node(iq_no % num_online_cpus());
|
||||
|
||||
if (oct->instr_queue[iq_no]) {
|
||||
dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n",
|
||||
iq_no);
|
||||
oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64;
|
||||
oct->instr_queue[iq_no]->app_ctx = app_ctx;
|
||||
return 0;
|
||||
}
|
||||
oct->instr_queue[iq_no] =
|
||||
vmalloc(sizeof(struct octeon_instr_queue));
|
||||
vmalloc_node(sizeof(struct octeon_instr_queue), numa_node);
|
||||
if (!oct->instr_queue[iq_no])
|
||||
oct->instr_queue[iq_no] =
|
||||
vmalloc(sizeof(struct octeon_instr_queue));
|
||||
if (!oct->instr_queue[iq_no])
|
||||
return 1;
|
||||
|
||||
|
|
@ -208,7 +228,7 @@ int octeon_setup_iq(struct octeon_device *oct,
|
|||
sizeof(struct octeon_instr_queue));
|
||||
|
||||
oct->instr_queue[iq_no]->app_ctx = app_ctx;
|
||||
if (octeon_init_instr_queue(oct, iq_no, num_descs)) {
|
||||
if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
|
||||
vfree(oct->instr_queue[iq_no]);
|
||||
oct->instr_queue[iq_no] = NULL;
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue