ath10k: split ce initialization and allocation
Definitions by which copy engine structure are allocated do not change so it doesn't make much sense to re-create those structures each time device is booted (e.g. due to firmware recovery). This should decrease chance of memory allocation failures. While at it remove per_transfer_context pointer indirection. The array has been trailing the copy engine ringbuffer structure anyway. This also saves pointer size worth of bytes for each copy engine ringbuffer. Reported-By: Avery Pennarun <apenwarr@gmail.com> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Michal Kazior
Kalle Valo
parent
68c03249f3
commit
25d0dbcbd5
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@ -840,34 +840,17 @@ void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
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static int ath10k_ce_init_src_ring(struct ath10k *ar,
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unsigned int ce_id,
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struct ath10k_ce_pipe *ce_state,
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const struct ce_attr *attr)
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{
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struct ath10k_ce_ring *src_ring;
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unsigned int nentries = attr->src_nentries;
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unsigned int ce_nbytes;
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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dma_addr_t base_addr;
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char *ptr;
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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struct ath10k_ce_ring *src_ring = ce_state->src_ring;
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u32 nentries, ctrl_addr = ath10k_ce_base_address(ce_id);
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nentries = roundup_pow_of_two(nentries);
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nentries = roundup_pow_of_two(attr->src_nentries);
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if (ce_state->src_ring) {
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WARN_ON(ce_state->src_ring->nentries != nentries);
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return 0;
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}
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ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
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ptr = kzalloc(ce_nbytes, GFP_KERNEL);
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if (ptr == NULL)
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return -ENOMEM;
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ce_state->src_ring = (struct ath10k_ce_ring *)ptr;
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src_ring = ce_state->src_ring;
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ptr += sizeof(struct ath10k_ce_ring);
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src_ring->nentries = nentries;
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src_ring->nentries_mask = nentries - 1;
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memset(src_ring->per_transfer_context, 0,
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nentries * sizeof(*src_ring->per_transfer_context));
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src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
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src_ring->sw_index &= src_ring->nentries_mask;
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@ -877,7 +860,74 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
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ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);
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src_ring->write_index &= src_ring->nentries_mask;
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src_ring->per_transfer_context = (void **)ptr;
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ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,
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src_ring->base_addr_ce_space);
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ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
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ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
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ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
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ath10k_dbg(ATH10K_DBG_BOOT,
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"boot init ce src ring id %d entries %d base_addr %p\n",
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ce_id, nentries, src_ring->base_addr_owner_space);
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return 0;
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}
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static int ath10k_ce_init_dest_ring(struct ath10k *ar,
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unsigned int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
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u32 nentries, ctrl_addr = ath10k_ce_base_address(ce_id);
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nentries = roundup_pow_of_two(attr->dest_nentries);
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memset(dest_ring->per_transfer_context, 0,
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nentries * sizeof(*dest_ring->per_transfer_context));
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dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
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dest_ring->sw_index &= dest_ring->nentries_mask;
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dest_ring->write_index =
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ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
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dest_ring->write_index &= dest_ring->nentries_mask;
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ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,
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dest_ring->base_addr_ce_space);
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ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
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ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
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ath10k_dbg(ATH10K_DBG_BOOT,
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"boot ce dest ring id %d entries %d base_addr %p\n",
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ce_id, nentries, dest_ring->base_addr_owner_space);
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return 0;
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}
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static struct ath10k_ce_ring *
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ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_ce_ring *src_ring;
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u32 nentries = attr->src_nentries;
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dma_addr_t base_addr;
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nentries = roundup_pow_of_two(nentries);
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src_ring = kzalloc(sizeof(*src_ring) +
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(nentries *
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sizeof(*src_ring->per_transfer_context)),
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GFP_KERNEL);
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if (src_ring == NULL)
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return ERR_PTR(-ENOMEM);
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src_ring->nentries = nentries;
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src_ring->nentries_mask = nentries - 1;
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/*
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* Legacy platforms that do not support cache
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@ -889,9 +939,8 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
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CE_DESC_RING_ALIGN),
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&base_addr, GFP_KERNEL);
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if (!src_ring->base_addr_owner_space_unaligned) {
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kfree(ce_state->src_ring);
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ce_state->src_ring = NULL;
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return -ENOMEM;
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kfree(src_ring);
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return ERR_PTR(-ENOMEM);
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}
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src_ring->base_addr_ce_space_unaligned = base_addr;
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@ -916,69 +965,37 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
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CE_DESC_RING_ALIGN),
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src_ring->base_addr_owner_space,
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src_ring->base_addr_ce_space);
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kfree(ce_state->src_ring);
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ce_state->src_ring = NULL;
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return -ENOMEM;
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kfree(src_ring);
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return ERR_PTR(-ENOMEM);
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}
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src_ring->shadow_base = PTR_ALIGN(
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src_ring->shadow_base_unaligned,
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CE_DESC_RING_ALIGN);
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ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,
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src_ring->base_addr_ce_space);
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ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
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ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
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ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
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ath10k_dbg(ATH10K_DBG_BOOT,
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"boot ce src ring id %d entries %d base_addr %p\n",
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ce_id, nentries, src_ring->base_addr_owner_space);
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return 0;
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return src_ring;
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}
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static int ath10k_ce_init_dest_ring(struct ath10k *ar,
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unsigned int ce_id,
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struct ath10k_ce_pipe *ce_state,
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static struct ath10k_ce_ring *
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ath10k_ce_alloc_dest_ring(struct ath10k *ar, unsigned int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_ce_ring *dest_ring;
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unsigned int nentries = attr->dest_nentries;
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unsigned int ce_nbytes;
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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u32 nentries;
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dma_addr_t base_addr;
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char *ptr;
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nentries = roundup_pow_of_two(nentries);
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nentries = roundup_pow_of_two(attr->dest_nentries);
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if (ce_state->dest_ring) {
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WARN_ON(ce_state->dest_ring->nentries != nentries);
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return 0;
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}
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dest_ring = kzalloc(sizeof(*dest_ring) +
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(nentries *
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sizeof(*dest_ring->per_transfer_context)),
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GFP_KERNEL);
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if (dest_ring == NULL)
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return ERR_PTR(-ENOMEM);
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ce_nbytes = sizeof(struct ath10k_ce_ring) + (nentries * sizeof(void *));
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ptr = kzalloc(ce_nbytes, GFP_KERNEL);
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if (ptr == NULL)
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return -ENOMEM;
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ce_state->dest_ring = (struct ath10k_ce_ring *)ptr;
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dest_ring = ce_state->dest_ring;
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ptr += sizeof(struct ath10k_ce_ring);
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dest_ring->nentries = nentries;
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dest_ring->nentries_mask = nentries - 1;
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dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
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dest_ring->sw_index &= dest_ring->nentries_mask;
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dest_ring->write_index =
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ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
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dest_ring->write_index &= dest_ring->nentries_mask;
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dest_ring->per_transfer_context = (void **)ptr;
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/*
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* Legacy platforms that do not support cache
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* coherent DMA are unsupported
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@ -989,9 +1006,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
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CE_DESC_RING_ALIGN),
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&base_addr, GFP_KERNEL);
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if (!dest_ring->base_addr_owner_space_unaligned) {
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kfree(ce_state->dest_ring);
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ce_state->dest_ring = NULL;
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return -ENOMEM;
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kfree(dest_ring);
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return ERR_PTR(-ENOMEM);
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}
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dest_ring->base_addr_ce_space_unaligned = base_addr;
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@ -1010,39 +1026,7 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
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dest_ring->base_addr_ce_space_unaligned,
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CE_DESC_RING_ALIGN);
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ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,
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dest_ring->base_addr_ce_space);
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ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
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ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
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ath10k_dbg(ATH10K_DBG_BOOT,
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"boot ce dest ring id %d entries %d base_addr %p\n",
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ce_id, nentries, dest_ring->base_addr_owner_space);
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return 0;
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}
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static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar,
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unsigned int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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spin_lock_bh(&ar_pci->ce_lock);
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ce_state->ar = ar;
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ce_state->id = ce_id;
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ce_state->ctrl_addr = ctrl_addr;
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ce_state->attr_flags = attr->flags;
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ce_state->src_sz_max = attr->src_sz_max;
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spin_unlock_bh(&ar_pci->ce_lock);
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return ce_state;
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return dest_ring;
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}
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/*
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@ -1052,11 +1036,11 @@ static struct ath10k_ce_pipe *ath10k_ce_init_state(struct ath10k *ar,
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* initialization. It may be that only one side or the other is
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* initialized by software/firmware.
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*/
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struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
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unsigned int ce_id,
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int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_ce_pipe *ce_state;
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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int ret;
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/*
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@ -1072,44 +1056,109 @@ struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
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ret = ath10k_pci_wake(ar);
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if (ret)
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return NULL;
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return ret;
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ce_state = ath10k_ce_init_state(ar, ce_id, attr);
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if (!ce_state) {
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ath10k_err("Failed to initialize CE state for ID: %d\n", ce_id);
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goto out;
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}
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spin_lock_bh(&ar_pci->ce_lock);
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ce_state->ar = ar;
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ce_state->id = ce_id;
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ce_state->ctrl_addr = ath10k_ce_base_address(ce_id);
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ce_state->attr_flags = attr->flags;
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ce_state->src_sz_max = attr->src_sz_max;
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spin_unlock_bh(&ar_pci->ce_lock);
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if (attr->src_nentries) {
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ret = ath10k_ce_init_src_ring(ar, ce_id, ce_state, attr);
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ret = ath10k_ce_init_src_ring(ar, ce_id, attr);
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if (ret) {
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ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
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ce_id, ret);
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ath10k_ce_deinit(ce_state);
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ce_state = NULL;
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goto out;
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}
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}
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if (attr->dest_nentries) {
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ret = ath10k_ce_init_dest_ring(ar, ce_id, ce_state, attr);
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ret = ath10k_ce_init_dest_ring(ar, ce_id, attr);
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if (ret) {
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ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
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ce_id, ret);
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ath10k_ce_deinit(ce_state);
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ce_state = NULL;
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goto out;
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}
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}
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out:
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ath10k_pci_sleep(ar);
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return ce_state;
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return ret;
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}
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void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state)
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static void ath10k_ce_deinit_src_ring(struct ath10k *ar, unsigned int ce_id)
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{
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struct ath10k *ar = ce_state->ar;
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_size_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, 0);
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ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, 0);
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}
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static void ath10k_ce_deinit_dest_ring(struct ath10k *ar, unsigned int ce_id)
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{
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u32 ctrl_addr = ath10k_ce_base_address(ce_id);
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ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_size_set(ar, ctrl_addr, 0);
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ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, 0);
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}
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void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id)
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{
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int ret;
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ret = ath10k_pci_wake(ar);
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if (ret)
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return;
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ath10k_ce_deinit_src_ring(ar, ce_id);
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ath10k_ce_deinit_dest_ring(ar, ce_id);
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ath10k_pci_sleep(ar);
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}
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int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
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const struct ce_attr *attr)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
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int ret;
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if (attr->src_nentries) {
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ce_state->src_ring = ath10k_ce_alloc_src_ring(ar, ce_id, attr);
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if (IS_ERR(ce_state->src_ring)) {
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ret = PTR_ERR(ce_state->src_ring);
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ath10k_err("failed to allocate copy engine source ring %d: %d\n",
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ce_id, ret);
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ce_state->src_ring = NULL;
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return ret;
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}
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}
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if (attr->dest_nentries) {
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ce_state->dest_ring = ath10k_ce_alloc_dest_ring(ar, ce_id,
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attr);
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if (IS_ERR(ce_state->dest_ring)) {
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ret = PTR_ERR(ce_state->dest_ring);
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ath10k_err("failed to allocate copy engine destination ring %d: %d\n",
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ce_id, ret);
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ce_state->dest_ring = NULL;
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return ret;
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}
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}
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return 0;
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}
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void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
|
||||
|
||||
if (ce_state->src_ring) {
|
||||
kfree(ce_state->src_ring->shadow_base_unaligned);
|
||||
|
|
|
|||
|
|
@ -104,7 +104,8 @@ struct ath10k_ce_ring {
|
|||
void *shadow_base_unaligned;
|
||||
struct ce_desc *shadow_base;
|
||||
|
||||
void **per_transfer_context;
|
||||
/* keep last */
|
||||
void *per_transfer_context[0];
|
||||
};
|
||||
|
||||
struct ath10k_ce_pipe {
|
||||
|
|
@ -210,10 +211,12 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
|
|||
|
||||
/*==================CE Engine Initialization=======================*/
|
||||
|
||||
/* Initialize an instance of a CE */
|
||||
struct ath10k_ce_pipe *ath10k_ce_init(struct ath10k *ar,
|
||||
unsigned int ce_id,
|
||||
int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
|
||||
const struct ce_attr *attr);
|
||||
void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
|
||||
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
|
||||
const struct ce_attr *attr);
|
||||
void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
|
||||
|
||||
/*==================CE Engine Shutdown=======================*/
|
||||
/*
|
||||
|
|
@ -236,8 +239,6 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
|
|||
unsigned int *nbytesp,
|
||||
unsigned int *transfer_idp);
|
||||
|
||||
void ath10k_ce_deinit(struct ath10k_ce_pipe *ce_state);
|
||||
|
||||
/*==================CE Interrupt Handlers====================*/
|
||||
void ath10k_ce_per_engine_service_any(struct ath10k *ar);
|
||||
void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
|
||||
|
|
|
|||
|
|
@ -1258,18 +1258,10 @@ static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
|
|||
|
||||
static void ath10k_pci_ce_deinit(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
struct ath10k_pci_pipe *pipe_info;
|
||||
int pipe_num;
|
||||
int i;
|
||||
|
||||
for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
|
||||
pipe_info = &ar_pci->pipe_info[pipe_num];
|
||||
if (pipe_info->ce_hdl) {
|
||||
ath10k_ce_deinit(pipe_info->ce_hdl);
|
||||
pipe_info->ce_hdl = NULL;
|
||||
pipe_info->buf_sz = 0;
|
||||
}
|
||||
}
|
||||
for (i = 0; i < CE_COUNT; i++)
|
||||
ath10k_ce_deinit_pipe(ar, i);
|
||||
}
|
||||
|
||||
static void ath10k_pci_hif_stop(struct ath10k *ar)
|
||||
|
|
@ -1722,30 +1714,49 @@ static int ath10k_pci_init_config(struct ath10k *ar)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ath10k_pci_alloc_ce(struct ath10k *ar)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < CE_COUNT; i++) {
|
||||
ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
|
||||
if (ret) {
|
||||
ath10k_err("failed to allocate copy engine pipe %d: %d\n",
|
||||
i, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ath10k_pci_free_ce(struct ath10k *ar)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CE_COUNT; i++)
|
||||
ath10k_ce_free_pipe(ar, i);
|
||||
}
|
||||
|
||||
static int ath10k_pci_ce_init(struct ath10k *ar)
|
||||
{
|
||||
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
|
||||
struct ath10k_pci_pipe *pipe_info;
|
||||
const struct ce_attr *attr;
|
||||
int pipe_num;
|
||||
int pipe_num, ret;
|
||||
|
||||
for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
|
||||
pipe_info = &ar_pci->pipe_info[pipe_num];
|
||||
pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
|
||||
pipe_info->pipe_num = pipe_num;
|
||||
pipe_info->hif_ce_state = ar;
|
||||
attr = &host_ce_config_wlan[pipe_num];
|
||||
|
||||
pipe_info->ce_hdl = ath10k_ce_init(ar, pipe_num, attr);
|
||||
if (pipe_info->ce_hdl == NULL) {
|
||||
ath10k_err("failed to initialize CE for pipe: %d\n",
|
||||
pipe_num);
|
||||
|
||||
/* It is safe to call it here. It checks if ce_hdl is
|
||||
* valid for each pipe */
|
||||
ath10k_pci_ce_deinit(ar);
|
||||
return -1;
|
||||
ret = ath10k_ce_init_pipe(ar, pipe_num, attr);
|
||||
if (ret) {
|
||||
ath10k_err("failed to initialize copy engine pipe %d: %d\n",
|
||||
pipe_num, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (pipe_num == CE_COUNT - 1) {
|
||||
|
|
@ -2648,16 +2659,24 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
|
|||
|
||||
ath10k_do_pci_sleep(ar);
|
||||
|
||||
ret = ath10k_pci_alloc_ce(ar);
|
||||
if (ret) {
|
||||
ath10k_err("failed to allocate copy engine pipes: %d\n", ret);
|
||||
goto err_iomap;
|
||||
}
|
||||
|
||||
ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
|
||||
|
||||
ret = ath10k_core_register(ar, chip_id);
|
||||
if (ret) {
|
||||
ath10k_err("failed to register driver core: %d\n", ret);
|
||||
goto err_iomap;
|
||||
goto err_free_ce;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_ce:
|
||||
ath10k_pci_free_ce(ar);
|
||||
err_iomap:
|
||||
pci_iounmap(pdev, mem);
|
||||
err_master:
|
||||
|
|
@ -2693,6 +2712,7 @@ static void ath10k_pci_remove(struct pci_dev *pdev)
|
|||
tasklet_kill(&ar_pci->msi_fw_err);
|
||||
|
||||
ath10k_core_unregister(ar);
|
||||
ath10k_pci_free_ce(ar);
|
||||
|
||||
pci_iounmap(pdev, ar_pci->mem);
|
||||
pci_release_region(pdev, BAR_NUM);
|
||||
|
|
|
|||
Loading…
Reference in New Issue