habanalabs/gaudi2: replace defines for reserved sob/mob with enums
Following patches are going to add more reserved sync objects and monitors. To make the counting of these reserved resources simpler, replace the existing RESERVED_* defines with enumerations. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Tomer Tayar
Oded Gabbay
parent
1cf596c6b9
commit
25ad863839
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@ -1867,8 +1867,8 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev)
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prop->user_dec_intr_count = NUMBER_OF_DEC;
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prop->user_interrupt_count = GAUDI2_IRQ_NUM_USER_LAST - GAUDI2_IRQ_NUM_USER_FIRST + 1;
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prop->completion_mode = HL_COMPLETION_MODE_CS;
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prop->sync_stream_first_sob = GAUDI2_RESERVED_SOBS;
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prop->sync_stream_first_mon = GAUDI2_RESERVED_MONITORS;
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prop->sync_stream_first_sob = GAUDI2_RESERVED_SOB_NUMBER;
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prop->sync_stream_first_mon = GAUDI2_RESERVED_MON_NUMBER;
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prop->sram_base_address = SRAM_BASE_ADDR;
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prop->sram_size = SRAM_SIZE;
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@ -1988,10 +1988,10 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev)
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prop->mme_master_slave_mode = 1;
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prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOBS +
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prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
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(num_sync_stream_queues * HL_RSVD_SOBS);
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prop->first_available_user_mon[0] = GAUDI2_RESERVED_MONITORS +
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prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
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(num_sync_stream_queues * HL_RSVD_MONS);
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prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
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@ -3533,7 +3533,7 @@ static int gaudi2_enable_msix(struct hl_device *hdev)
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}
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irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
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cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_COMPLETION];
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cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION];
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rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi2_irq_name(GAUDI2_IRQ_NUM_COMPLETION), cq);
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if (rc) {
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dev_err(hdev->dev, "Failed to request IRQ %d", irq);
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@ -3643,7 +3643,7 @@ static void gaudi2_disable_msix(struct hl_device *hdev)
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}
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irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
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cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_COMPLETION];
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cq = &hdev->completion_queue[GAUDI2_RESERVED_CQ_CS_COMPLETION];
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free_irq(irq, cq);
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pci_free_irq_vectors(hdev->pdev);
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@ -4139,7 +4139,7 @@ static void gaudi2_init_qman(struct hl_device *hdev, u32 reg_base,
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u32 pq_id;
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for (pq_id = 0 ; pq_id < NUM_OF_PQ_PER_QMAN ; pq_id++)
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hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_COMPLETION;
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hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_CS_COMPLETION;
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gaudi2_init_qman_pq(hdev, reg_base, queue_id_base);
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gaudi2_init_qman_cp(hdev, reg_base);
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@ -5762,31 +5762,33 @@ static void gaudi2_kdma_set_mmbp_asid(struct hl_device *hdev,
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WREG32(mmARC_FARM_KDMA_CTX_AXUSER_HB_MMU_BP, rw_mmu_bp);
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}
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static void gaudi2_arm_cq_monitor(struct hl_device *hdev, u32 index, u32 cq_id,
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static void gaudi2_arm_cq_monitor(struct hl_device *hdev, u32 sob_id, u32 mon_id, u32 cq_id,
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u32 mon_payload, u32 sync_value)
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{
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u32 sync_group_id, mode, mon_arm;
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int offset = index * 4;
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u32 sob_offset, mon_offset, sync_group_id, mode, mon_arm;
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u8 mask;
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sob_offset = sob_id * 4;
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mon_offset = mon_id * 4;
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/* Reset the SOB value */
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset, 0);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0);
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/* Configure this address with CQ_ID 0 because CQ_EN is set */
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + offset, cq_id);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, cq_id);
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/* Configure this address with CS index because CQ_EN is set */
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + offset, mon_payload);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, mon_payload);
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sync_group_id = index / 8;
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mask = ~(1 << (index & 0x7));
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sync_group_id = sob_id / 8;
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mask = ~(1 << (sob_id & 0x7));
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mode = 1; /* comparison mode is "equal to" */
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mon_arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, sync_value);
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mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode);
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mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask);
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mon_arm |= FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sync_group_id);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + offset, mon_arm);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, mon_arm);
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}
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/* This is an internal helper function used by gaudi2_send_job_to_kdma only */
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@ -5800,11 +5802,12 @@ static int gaudi2_send_job_to_kdma(struct hl_device *hdev,
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u64 comp_addr;
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int rc;
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gaudi2_arm_cq_monitor(hdev, GAUDI2_RESERVED_SOB_KDMA_COMP,
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gaudi2_arm_cq_monitor(hdev, GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
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GAUDI2_RESERVED_MON_KDMA_COMPLETION,
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GAUDI2_RESERVED_CQ_KDMA_COMPLETION, 1, 1);
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comp_addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 +
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(GAUDI2_RESERVED_SOB_KDMA_COMP * sizeof(u32));
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(GAUDI2_RESERVED_SOB_KDMA_COMPLETION * sizeof(u32));
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comp_val = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1) |
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1);
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@ -9125,24 +9128,25 @@ static int gaudi2_pre_schedule_cs(struct hl_cs *cs)
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{
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struct hl_device *hdev = cs->ctx->hdev;
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int index = cs->sequence & (hdev->asic_prop.max_pending_cs - 1);
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u32 mon_payload;
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u32 mon_payload, sob_id, mon_id;
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if (!cs_needs_completion(cs))
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return 0;
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/*
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* First 1024 SOB/MON are reserved for driver for QMAN auto completion
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* First 64 SOB/MON are reserved for driver for QMAN auto completion
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* mechanism. Each SOB/MON pair are used for a pending CS with the same
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* cyclic index. The SOB value is increased when each of the CS jobs is
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* completed. When the SOB reaches the number of CS jobs, the monitor
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* generates MSI-X interrupt.
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*/
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sob_id = mon_id = index;
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mon_payload = (1 << CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT) |
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(1 << CQ_ENTRY_READY_SHIFT) | index;
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gaudi2_arm_cq_monitor(hdev, index, GAUDI2_RESERVED_CQ_COMPLETION,
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mon_payload, cs->jobs_cnt);
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gaudi2_arm_cq_monitor(hdev, sob_id, mon_id, GAUDI2_RESERVED_CQ_CS_COMPLETION, mon_payload,
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cs->jobs_cnt);
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return 0;
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}
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@ -80,12 +80,6 @@
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#define GAUDI2_MAX_PENDING_CS 64
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/* Sob/Mon per CS + Sob/Mon for KDMA completion */
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#define GAUDI2_RESERVED_SOBS (GAUDI2_MAX_PENDING_CS + 1)
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#define GAUDI2_RESERVED_MONITORS (GAUDI2_MAX_PENDING_CS + 1)
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#define GAUDI2_RESERVED_SOB_KDMA_COMP (GAUDI2_MAX_PENDING_CS)
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#define GAUDI2_RESERVED_MON_KDMA_COMP (GAUDI2_MAX_PENDING_CS)
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#if !IS_MAX_PENDING_CS_VALID(GAUDI2_MAX_PENDING_CS)
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#error "GAUDI2_MAX_PENDING_CS must be power of 2 and greater than 1"
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#endif
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@ -249,10 +243,26 @@
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#define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28)
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enum gaudi2_reserved_sob_id {
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GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
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GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
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GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
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GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
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GAUDI2_RESERVED_SOB_NUMBER
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};
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enum gaudi2_reserved_mon_id {
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GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST,
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GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
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GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
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GAUDI2_RESERVED_MON_KDMA_COMPLETION,
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GAUDI2_RESERVED_MON_NUMBER
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};
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enum gaudi2_reserved_cq_id {
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GAUDI2_RESERVED_CQ_COMPLETION,
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GAUDI2_RESERVED_CQ_CS_COMPLETION,
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GAUDI2_RESERVED_CQ_KDMA_COMPLETION,
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GAUDI2_RESERVED_CQ_NUMBER,
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GAUDI2_RESERVED_CQ_NUMBER
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};
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/*
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@ -2703,8 +2703,8 @@ static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
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if (!sec_array)
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return -ENOMEM;
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first_sob = GAUDI2_RESERVED_SOBS;
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first_mon = GAUDI2_RESERVED_MONITORS;
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first_sob = GAUDI2_RESERVED_SOB_NUMBER;
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first_mon = GAUDI2_RESERVED_MON_NUMBER;
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/* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
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for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
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