wlcore/wl12xx: implement chip-specific partition tables
Add partition tables to wlcore, move and reorganize partition setting functions. Move wl12xx partition table to use the wlcore partition table instead. Signed-off-by: Luciano Coelho <coelho@ti.com>
This commit is contained in:
Luciano Coelho
parent
c31be25a71
commit
25a43d78eb
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@ -27,9 +27,70 @@
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#include "../wlcore/wlcore.h"
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#include "../wlcore/debug.h"
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#include "../wlcore/reg.h"
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static struct wlcore_ops wl12xx_ops = {
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};
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static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
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[PART_DOWN] = {
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.mem = {
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.start = 0x00000000,
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.size = 0x000177c0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x00008800
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},
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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},
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[PART_WORK] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x0000a000
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},
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.mem2 = {
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.start = 0x003004f8,
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.size = 0x00000004
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},
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.mem3 = {
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.start = 0x00040404,
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.size = 0x00000000
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},
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},
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[PART_DRPW] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = DRPW_BASE,
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.size = 0x00006000
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},
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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}
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}
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};
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static int __devinit wl12xx_probe(struct platform_device *pdev)
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{
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struct wl1271 *wl;
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@ -43,6 +104,7 @@ static int __devinit wl12xx_probe(struct platform_device *pdev)
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wl = hw->priv;
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wl->ops = &wl12xx_ops;
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wl->ptable = wl12xx_ptable;
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return wlcore_probe(wl, pdev);
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}
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@ -108,7 +108,7 @@ static void wl1271_boot_fw_version(struct wl1271 *wl)
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static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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size_t fw_data_len, u32 dest)
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{
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struct wl1271_partition_set partition;
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struct wlcore_partition_set partition;
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int addr, chunk_num, partition_limit;
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u8 *p, *chunk;
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@ -130,13 +130,13 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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return -ENOMEM;
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}
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memcpy(&partition, &wl12xx_part_table[PART_DOWN], sizeof(partition));
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memcpy(&partition, &wl->ptable[PART_DOWN], sizeof(partition));
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partition.mem.start = dest;
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wl1271_set_partition(wl, &partition);
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wlcore_set_partition(wl, &partition);
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/* 10.1 set partition limit and chunk num */
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chunk_num = 0;
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partition_limit = wl12xx_part_table[PART_DOWN].mem.size;
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partition_limit = wl->ptable[PART_DOWN].mem.size;
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while (chunk_num < fw_data_len / CHUNK_SIZE) {
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/* 10.2 update partition, if needed */
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@ -144,9 +144,9 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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if (addr > partition_limit) {
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addr = dest + chunk_num * CHUNK_SIZE;
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partition_limit = chunk_num * CHUNK_SIZE +
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wl12xx_part_table[PART_DOWN].mem.size;
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wl->ptable[PART_DOWN].mem.size;
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partition.mem.start = addr;
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wl1271_set_partition(wl, &partition);
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wlcore_set_partition(wl, &partition);
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}
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/* 10.3 upload the chunk */
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@ -332,7 +332,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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nvs_len -= nvs_ptr - (u8 *)wl->nvs;
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/* Now we must set the partition correctly */
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wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
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wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
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/* Copy the NVS tables to a new block to ensure alignment */
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nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
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@ -441,7 +441,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
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/* set the working partition to its "running" mode offset */
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wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
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wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
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wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
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wl->cmd_box_addr, wl->event_box_addr);
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@ -702,7 +702,7 @@ int wl1271_load_firmware(struct wl1271 *wl)
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wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wl1271_set_partition(wl, &wl12xx_part_table[PART_DRPW]);
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wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
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/* Read-modify-write DRPW_SCRATCH_START register (see next state)
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to be used by DRPw FW. The RTRIM value will be added by the FW
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@ -721,7 +721,7 @@ int wl1271_load_firmware(struct wl1271 *wl)
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wl1271_write32(wl, DRPW_SCRATCH_START, clk);
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wl1271_set_partition(wl, &wl12xx_part_table[PART_WORK]);
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wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
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/* Disable interrupts */
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wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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@ -52,6 +52,7 @@ enum {
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DEBUG_ADHOC = BIT(16),
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DEBUG_AP = BIT(17),
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DEBUG_PROBE = BIT(18),
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DEBUG_IO = BIT(19),
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DEBUG_MASTER = (DEBUG_ADHOC | DEBUG_AP),
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DEBUG_ALL = ~0,
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};
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@ -45,65 +45,6 @@
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#define OCP_STATUS_REQ_FAILED 0x20000
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#define OCP_STATUS_RESP_ERROR 0x30000
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struct wl1271_partition_set wl12xx_part_table[PART_TABLE_LEN] = {
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[PART_DOWN] = {
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.mem = {
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.start = 0x00000000,
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.size = 0x000177c0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x00008800
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},
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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},
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[PART_WORK] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = REGISTERS_BASE,
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.size = 0x0000a000
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},
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.mem2 = {
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.start = 0x003004f8,
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.size = 0x00000004
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},
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.mem3 = {
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.start = 0x00040404,
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.size = 0x00000000
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},
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},
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[PART_DRPW] = {
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.mem = {
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.start = 0x00040000,
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.size = 0x00014fc0
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},
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.reg = {
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.start = DRPW_BASE,
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.size = 0x00006000
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},
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.mem2 = {
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.start = 0x00000000,
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.size = 0x00000000
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},
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.mem3 = {
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.start = 0x00000000,
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.size = 0x00000000
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}
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}
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};
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bool wl1271_set_block_size(struct wl1271 *wl)
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{
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if (wl->if_ops->set_block_size) {
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@ -124,7 +65,41 @@ void wl1271_enable_interrupts(struct wl1271 *wl)
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enable_irq(wl->irq);
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}
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/* Set the SPI partitions to access the chip addresses
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int wlcore_translate_addr(struct wl1271 *wl, int addr)
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{
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struct wlcore_partition_set *part = &wl->curr_part;
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/*
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* To translate, first check to which window of addresses the
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* particular address belongs. Then subtract the starting address
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* of that window from the address. Then, add offset of the
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* translated region.
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*
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* The translated regions occur next to each other in physical device
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* memory, so just add the sizes of the preceding address regions to
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* get the offset to the new region.
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*/
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if ((addr >= part->mem.start) &&
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(addr < part->mem.start + part->mem.size))
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return addr - part->mem.start;
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else if ((addr >= part->reg.start) &&
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(addr < part->reg.start + part->reg.size))
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return addr - part->reg.start + part->mem.size;
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else if ((addr >= part->mem2.start) &&
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(addr < part->mem2.start + part->mem2.size))
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return addr - part->mem2.start + part->mem.size +
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part->reg.size;
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else if ((addr >= part->mem3.start) &&
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(addr < part->mem3.start + part->mem3.size))
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return addr - part->mem3.start + part->mem.size +
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part->reg.size + part->mem2.size;
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WARN(1, "HW address 0x%x out of range", addr);
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return 0;
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}
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EXPORT_SYMBOL_GPL(wlcore_translate_addr);
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/* Set the partitions to access the chip addresses
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*
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* To simplify driver code, a fixed (virtual) memory map is defined for
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* register and memory addresses. Because in the chipset, in different stages
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@ -158,33 +133,43 @@ void wl1271_enable_interrupts(struct wl1271 *wl)
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* | |
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*
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*/
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int wl1271_set_partition(struct wl1271 *wl,
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struct wl1271_partition_set *p)
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void wlcore_set_partition(struct wl1271 *wl,
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const struct wlcore_partition_set *p)
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{
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/* copy partition info */
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memcpy(&wl->part, p, sizeof(*p));
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memcpy(&wl->curr_part, p, sizeof(*p));
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wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
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wl1271_debug(DEBUG_IO, "mem_start %08X mem_size %08X",
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p->mem.start, p->mem.size);
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wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
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wl1271_debug(DEBUG_IO, "reg_start %08X reg_size %08X",
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p->reg.start, p->reg.size);
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wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
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wl1271_debug(DEBUG_IO, "mem2_start %08X mem2_size %08X",
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p->mem2.start, p->mem2.size);
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wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
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wl1271_debug(DEBUG_IO, "mem3_start %08X mem3_size %08X",
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p->mem3.start, p->mem3.size);
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/* write partition info to the chipset */
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wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
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wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
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wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
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wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
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wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
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wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
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/*
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* We don't need the size of the last partition, as it is
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* automatically calculated based on the total memory size and
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* the sizes of the previous partitions.
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*/
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wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
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return 0;
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}
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EXPORT_SYMBOL_GPL(wl1271_set_partition);
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EXPORT_SYMBOL_GPL(wlcore_set_partition);
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void wlcore_select_partition(struct wl1271 *wl, u8 part)
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{
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wl1271_debug(DEBUG_IO, "setting partition %d", part);
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wlcore_set_partition(wl, &wl->ptable[part]);
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}
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EXPORT_SYMBOL_GPL(wlcore_select_partition);
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void wl1271_io_reset(struct wl1271 *wl)
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{
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@ -241,4 +226,3 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
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return 0xffff;
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}
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}
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@ -43,8 +43,6 @@
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#define HW_ACCESS_PRAM_MAX_RANGE 0x3c000
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extern struct wl1271_partition_set wl12xx_part_table[PART_TABLE_LEN];
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struct wl1271;
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void wl1271_disable_interrupts(struct wl1271 *wl);
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@ -52,6 +50,7 @@ void wl1271_enable_interrupts(struct wl1271 *wl);
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void wl1271_io_reset(struct wl1271 *wl);
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void wl1271_io_init(struct wl1271 *wl);
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int wlcore_translate_addr(struct wl1271 *wl, int addr);
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/* Raw target IO, address is not translated */
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static inline void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf,
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@ -81,36 +80,12 @@ static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
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sizeof(wl->buffer_32), false);
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}
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/* Translated target IO */
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static inline int wl1271_translate_addr(struct wl1271 *wl, int addr)
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{
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/*
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* To translate, first check to which window of addresses the
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* particular address belongs. Then subtract the starting address
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* of that window from the address. Then, add offset of the
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* translated region.
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*
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* The translated regions occur next to each other in physical device
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* memory, so just add the sizes of the preceding address regions to
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* get the offset to the new region.
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*
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* Currently, only the two first regions are addressed, and the
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* assumption is that all addresses will fall into either of those
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* two.
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*/
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if ((addr >= wl->part.reg.start) &&
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(addr < wl->part.reg.start + wl->part.reg.size))
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return addr - wl->part.reg.start + wl->part.mem.size;
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else
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return addr - wl->part.mem.start;
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}
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static inline void wl1271_read(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed)
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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physical = wlcore_translate_addr(wl, addr);
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wl1271_raw_read(wl, physical, buf, len, fixed);
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}
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@ -120,7 +95,7 @@ static inline void wl1271_write(struct wl1271 *wl, int addr, void *buf,
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{
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int physical;
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physical = wl1271_translate_addr(wl, addr);
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physical = wlcore_translate_addr(wl, addr);
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wl1271_raw_write(wl, physical, buf, len, fixed);
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}
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@ -134,19 +109,19 @@ static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr,
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/* Addresses are stored internally as addresses to 32 bytes blocks */
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addr = hwaddr << 5;
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physical = wl1271_translate_addr(wl, addr);
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physical = wlcore_translate_addr(wl, addr);
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wl1271_raw_read(wl, physical, buf, len, fixed);
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}
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static inline u32 wl1271_read32(struct wl1271 *wl, int addr)
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{
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return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr));
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return wl1271_raw_read32(wl, wlcore_translate_addr(wl, addr));
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}
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static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val)
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{
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wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val);
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wl1271_raw_write32(wl, wlcore_translate_addr(wl, addr), val);
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}
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static inline void wl1271_power_off(struct wl1271 *wl)
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@ -169,8 +144,8 @@ static inline int wl1271_power_on(struct wl1271 *wl)
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void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
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u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
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int wl1271_set_partition(struct wl1271 *wl,
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struct wl1271_partition_set *p);
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void wlcore_set_partition(struct wl1271 *wl,
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const struct wlcore_partition_set *p);
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||||
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||||
bool wl1271_set_block_size(struct wl1271 *wl);
|
||||
|
||||
|
|
@ -178,4 +153,6 @@ bool wl1271_set_block_size(struct wl1271 *wl);
|
|||
|
||||
int wl1271_tx_dummy_packet(struct wl1271 *wl);
|
||||
|
||||
void wlcore_select_partition(struct wl1271 *wl, u8 part);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1330,7 +1330,7 @@ static int wl12xx_set_power_on(struct wl1271 *wl)
|
|||
wl1271_io_reset(wl);
|
||||
wl1271_io_init(wl);
|
||||
|
||||
wl1271_set_partition(wl, &wl12xx_part_table[PART_DOWN]);
|
||||
wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
|
||||
|
||||
/* ELP module wake up */
|
||||
wl1271_fw_wakeup(wl);
|
||||
|
|
@ -5085,7 +5085,7 @@ static void wl12xx_get_fuse_mac(struct wl1271 *wl)
|
|||
{
|
||||
u32 mac1, mac2;
|
||||
|
||||
wl1271_set_partition(wl, &wl12xx_part_table[PART_DRPW]);
|
||||
wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
|
||||
|
||||
mac1 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1);
|
||||
mac2 = wl1271_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2);
|
||||
|
|
@ -5095,7 +5095,7 @@ static void wl12xx_get_fuse_mac(struct wl1271 *wl)
|
|||
((mac1 & 0xff000000) >> 24);
|
||||
wl->fuse_nic_addr = mac1 & 0xffffff;
|
||||
|
||||
wl1271_set_partition(wl, &wl12xx_part_table[PART_DOWN]);
|
||||
wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
|
||||
}
|
||||
|
||||
static int wl12xx_get_hw_info(struct wl1271 *wl)
|
||||
|
|
@ -5485,7 +5485,7 @@ int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev)
|
|||
unsigned long irqflags;
|
||||
int ret;
|
||||
|
||||
if (!wl->ops) {
|
||||
if (!wl->ops || !wl->ptable) {
|
||||
ret = -EINVAL;
|
||||
goto out_free_hw;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -105,26 +105,6 @@ enum wl12xx_fw_type {
|
|||
WL12XX_FW_TYPE_PLT,
|
||||
};
|
||||
|
||||
enum wl1271_partition_type {
|
||||
PART_DOWN,
|
||||
PART_WORK,
|
||||
PART_DRPW,
|
||||
|
||||
PART_TABLE_LEN
|
||||
};
|
||||
|
||||
struct wl1271_partition {
|
||||
u32 size;
|
||||
u32 start;
|
||||
};
|
||||
|
||||
struct wl1271_partition_set {
|
||||
struct wl1271_partition mem;
|
||||
struct wl1271_partition reg;
|
||||
struct wl1271_partition mem2;
|
||||
struct wl1271_partition mem3;
|
||||
};
|
||||
|
||||
struct wl1271;
|
||||
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -30,6 +30,29 @@
|
|||
struct wlcore_ops {
|
||||
};
|
||||
|
||||
enum wlcore_partitions {
|
||||
PART_DOWN,
|
||||
PART_WORK,
|
||||
PART_BOOT,
|
||||
PART_DRPW,
|
||||
PART_TOP_PRCM_ELP_SOC,
|
||||
PART_PHY_INIT,
|
||||
|
||||
PART_TABLE_LEN,
|
||||
};
|
||||
|
||||
struct wlcore_partition {
|
||||
u32 size;
|
||||
u32 start;
|
||||
};
|
||||
|
||||
struct wlcore_partition_set {
|
||||
struct wlcore_partition mem;
|
||||
struct wlcore_partition reg;
|
||||
struct wlcore_partition mem2;
|
||||
struct wlcore_partition mem3;
|
||||
};
|
||||
|
||||
struct wl1271 {
|
||||
struct ieee80211_hw *hw;
|
||||
bool mac80211_registered;
|
||||
|
|
@ -54,7 +77,7 @@ struct wl1271 {
|
|||
|
||||
unsigned long flags;
|
||||
|
||||
struct wl1271_partition_set part;
|
||||
struct wlcore_partition_set curr_part;
|
||||
|
||||
struct wl1271_chip chip;
|
||||
|
||||
|
|
@ -241,6 +264,8 @@ struct wl1271 {
|
|||
struct delayed_work tx_watchdog_work;
|
||||
|
||||
struct wlcore_ops *ops;
|
||||
/* pointer to the lower driver partition table */
|
||||
const struct wlcore_partition_set *ptable;
|
||||
};
|
||||
|
||||
int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
|
||||
|
|
|
|||
Loading…
Reference in New Issue