MIPS: KVM: Convert emulation to use asm/inst.h
Convert various MIPS KVM guest instruction emulation functions to decode instructions (and encode translations) using the union mips_instruction and related enumerations in asm/inst.h rather than #defines and hardcoded values. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
James Hogan
Paolo Bonzini
parent
d5cd26bcfc
commit
258f3a2ea9
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@ -19,6 +19,7 @@
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <asm/inst.h>
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#include <asm/mipsregs.h>
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/* MIPS KVM register ids */
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@ -733,21 +734,21 @@ enum emulation_result kvm_mips_check_privilege(u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_cache(u32 inst,
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enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
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u32 *opc,
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u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_CP0(u32 inst,
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enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
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u32 *opc,
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u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_store(u32 inst,
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enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
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u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu);
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enum emulation_result kvm_mips_emulate_load(u32 inst,
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enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
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u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu);
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@ -758,11 +759,14 @@ unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
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unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
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/* Dynamic binary translation */
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extern int kvm_mips_trans_cache_index(u32 inst, u32 *opc,
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extern int kvm_mips_trans_cache_index(union mips_instruction inst,
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u32 *opc, struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_cache_va(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
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extern int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
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/* Misc */
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extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
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@ -103,7 +103,7 @@ enum rt_op {
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bltzal_op, bgezal_op, bltzall_op, bgezall_op,
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rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
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rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
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bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
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bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
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};
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/*
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@ -586,6 +586,36 @@ struct r_format { /* Register format */
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;))))))
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};
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struct c0r_format { /* C0 register format */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int rs : 5,
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__BITFIELD_FIELD(unsigned int rt : 5,
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__BITFIELD_FIELD(unsigned int rd : 5,
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__BITFIELD_FIELD(unsigned int z: 8,
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__BITFIELD_FIELD(unsigned int sel : 3,
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;))))))
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};
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struct mfmc0_format { /* MFMC0 register format */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int rs : 5,
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__BITFIELD_FIELD(unsigned int rt : 5,
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__BITFIELD_FIELD(unsigned int rd : 5,
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__BITFIELD_FIELD(unsigned int re : 5,
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__BITFIELD_FIELD(unsigned int sc : 1,
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__BITFIELD_FIELD(unsigned int : 2,
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__BITFIELD_FIELD(unsigned int sel : 3,
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;))))))))
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};
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struct co_format { /* C0 CO format */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int co : 1,
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__BITFIELD_FIELD(unsigned int code : 19,
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__BITFIELD_FIELD(unsigned int func : 6,
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;))))
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};
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struct p_format { /* Performance counter format (R10000) */
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__BITFIELD_FIELD(unsigned int opcode : 6,
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__BITFIELD_FIELD(unsigned int rs : 5,
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@ -937,6 +967,9 @@ union mips_instruction {
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struct u_format u_format;
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struct c_format c_format;
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struct r_format r_format;
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struct c0r_format c0r_format;
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struct mfmc0_format mfmc0_format;
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struct co_format co_format;
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struct p_format p_format;
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struct f_format f_format;
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struct ma_format ma_format;
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@ -20,21 +20,14 @@
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#include "commpage.h"
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#define SYNCI_TEMPLATE 0x041f0000
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#define SYNCI_BASE(x) (((x) >> 21) & 0x1f)
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#define SYNCI_OFFSET ((x) & 0xffff)
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#define LW_TEMPLATE 0x8c000000
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#define CLEAR_TEMPLATE 0x00000020
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#define SW_TEMPLATE 0xac000000
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/**
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* kvm_mips_trans_replace() - Replace trapping instruction in guest memory.
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* @vcpu: Virtual CPU.
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* @opc: PC of instruction to replace.
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* @replace: Instruction to write
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*/
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static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc, u32 replace)
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static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc,
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union mips_instruction replace)
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{
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unsigned long kseg0_opc, flags;
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@ -58,63 +51,68 @@ static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc, u32 replace)
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return 0;
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}
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int kvm_mips_trans_cache_index(u32 inst, u32 *opc,
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int kvm_mips_trans_cache_index(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu)
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{
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union mips_instruction nop_inst = { 0 };
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/* Replace the CACHE instruction, with a NOP */
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return kvm_mips_trans_replace(vcpu, opc, 0x00000000);
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return kvm_mips_trans_replace(vcpu, opc, nop_inst);
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}
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/*
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* Address based CACHE instructions are transformed into synci(s). A little
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* heavy for just D-cache invalidates, but avoids an expensive trap
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*/
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int kvm_mips_trans_cache_va(u32 inst, u32 *opc,
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int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu)
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{
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u32 synci_inst = SYNCI_TEMPLATE, base, offset;
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union mips_instruction synci_inst = { 0 };
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base = (inst >> 21) & 0x1f;
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offset = inst & 0xffff;
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synci_inst |= (base << 21);
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synci_inst |= offset;
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synci_inst.i_format.opcode = bcond_op;
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synci_inst.i_format.rs = inst.i_format.rs;
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synci_inst.i_format.rt = synci_op;
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synci_inst.i_format.simmediate = inst.i_format.simmediate;
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return kvm_mips_trans_replace(vcpu, opc, synci_inst);
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}
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int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu)
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int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu)
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{
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u32 rt, rd, sel;
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u32 mfc0_inst;
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union mips_instruction mfc0_inst = { 0 };
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u32 rd, sel;
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rt = (inst >> 16) & 0x1f;
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rd = (inst >> 11) & 0x1f;
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sel = inst & 0x7;
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rd = inst.c0r_format.rd;
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sel = inst.c0r_format.sel;
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if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
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mfc0_inst = CLEAR_TEMPLATE;
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mfc0_inst |= ((rt & 0x1f) << 11);
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if (rd == MIPS_CP0_ERRCTL && sel == 0) {
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mfc0_inst.r_format.opcode = spec_op;
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mfc0_inst.r_format.rd = inst.c0r_format.rt;
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mfc0_inst.r_format.func = add_op;
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} else {
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mfc0_inst = LW_TEMPLATE;
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mfc0_inst |= ((rt & 0x1f) << 16);
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mfc0_inst |= offsetof(struct kvm_mips_commpage,
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cop0.reg[rd][sel]);
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mfc0_inst.i_format.opcode = lw_op;
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mfc0_inst.i_format.rt = inst.c0r_format.rt;
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mfc0_inst.i_format.simmediate =
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offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
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}
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return kvm_mips_trans_replace(vcpu, opc, mfc0_inst);
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}
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int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu)
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int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
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struct kvm_vcpu *vcpu)
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{
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u32 rt, rd, sel;
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u32 mtc0_inst = SW_TEMPLATE;
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union mips_instruction mtc0_inst = { 0 };
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u32 rd, sel;
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rt = (inst >> 16) & 0x1f;
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rd = (inst >> 11) & 0x1f;
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sel = inst & 0x7;
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rd = inst.c0r_format.rd;
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sel = inst.c0r_format.sel;
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mtc0_inst |= ((rt & 0x1f) << 16);
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mtc0_inst |= offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
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mtc0_inst.i_format.opcode = sw_op;
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mtc0_inst.i_format.rt = inst.c0r_format.rt;
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mtc0_inst.i_format.simmediate =
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offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]);
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return kvm_mips_trans_replace(vcpu, opc, mtc0_inst);
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}
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@ -972,13 +972,14 @@ unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
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return mask;
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}
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enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
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u32 *opc, u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu)
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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enum emulation_result er = EMULATE_DONE;
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u32 rt, rd, copz, sel, co_bit, op;
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u32 rt, rd, sel;
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unsigned long curr_pc;
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/*
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@ -990,16 +991,8 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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if (er == EMULATE_FAIL)
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return er;
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copz = (inst >> 21) & 0x1f;
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rt = (inst >> 16) & 0x1f;
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rd = (inst >> 11) & 0x1f;
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sel = inst & 0x7;
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co_bit = (inst >> 25) & 1;
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if (co_bit) {
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op = (inst) & 0xff;
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switch (op) {
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if (inst.co_format.co) {
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switch (inst.co_format.func) {
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case tlbr_op: /* Read indexed TLB entry */
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er = kvm_mips_emul_tlbr(vcpu);
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break;
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@ -1018,13 +1011,16 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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case eret_op:
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er = kvm_mips_emul_eret(vcpu);
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goto dont_update_pc;
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break;
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case wait_op:
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er = kvm_mips_emul_wait(vcpu);
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break;
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}
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} else {
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switch (copz) {
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rt = inst.c0r_format.rt;
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rd = inst.c0r_format.rd;
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sel = inst.c0r_format.sel;
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switch (inst.c0r_format.rs) {
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case mfc_op:
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#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
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cop0->stat[rd][sel]++;
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@ -1258,7 +1254,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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vcpu->arch.gprs[rt] =
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kvm_read_c0_guest_status(cop0);
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/* EI */
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if (inst & 0x20) {
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if (inst.mfmc0_format.sc) {
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kvm_debug("[%#lx] mfmc0_op: EI\n",
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vcpu->arch.pc);
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kvm_set_c0_guest_status(cop0, ST0_IE);
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@ -1290,7 +1286,7 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
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break;
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default:
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kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
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vcpu->arch.pc, copz);
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vcpu->arch.pc, inst.c0r_format.rs);
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er = EMULATE_FAIL;
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break;
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}
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@ -1311,13 +1307,13 @@ dont_update_pc:
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return er;
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}
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enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause,
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enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
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u32 cause,
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struct kvm_run *run,
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struct kvm_vcpu *vcpu)
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{
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enum emulation_result er = EMULATE_DO_MMIO;
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u32 op, base, rt;
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s16 offset;
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u32 rt;
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u32 bytes;
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void *data = run->mmio.data;
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unsigned long curr_pc;
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@ -1331,12 +1327,9 @@ enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause,
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if (er == EMULATE_FAIL)
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return er;
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rt = (inst >> 16) & 0x1f;
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base = (inst >> 21) & 0x1f;
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offset = (s16)inst;
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op = (inst >> 26) & 0x3f;
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rt = inst.i_format.rt;
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switch (op) {
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switch (inst.i_format.opcode) {
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case sb_op:
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bytes = 1;
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if (bytes > sizeof(run->mmio.data)) {
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@ -1413,7 +1406,7 @@ enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause,
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default:
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kvm_err("Store not yet supported (inst=0x%08x)\n",
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inst);
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inst.word);
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er = EMULATE_FAIL;
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break;
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}
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@ -1425,19 +1418,16 @@ enum emulation_result kvm_mips_emulate_store(u32 inst, u32 cause,
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return er;
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}
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enum emulation_result kvm_mips_emulate_load(u32 inst, u32 cause,
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struct kvm_run *run,
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enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
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u32 cause, struct kvm_run *run,
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struct kvm_vcpu *vcpu)
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{
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enum emulation_result er = EMULATE_DO_MMIO;
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u32 op, base, rt;
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s16 offset;
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u32 op, rt;
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u32 bytes;
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rt = (inst >> 16) & 0x1f;
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base = (inst >> 21) & 0x1f;
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offset = (s16)inst;
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op = (inst >> 26) & 0x3f;
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rt = inst.i_format.rt;
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op = inst.i_format.opcode;
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vcpu->arch.pending_load_cause = cause;
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vcpu->arch.io_gpr = rt;
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@ -1524,7 +1514,7 @@ enum emulation_result kvm_mips_emulate_load(u32 inst, u32 cause,
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default:
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kvm_err("Load not yet supported (inst=0x%08x)\n",
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inst);
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inst.word);
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er = EMULATE_FAIL;
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break;
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}
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@ -1532,8 +1522,8 @@ enum emulation_result kvm_mips_emulate_load(u32 inst, u32 cause,
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return er;
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}
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enum emulation_result kvm_mips_emulate_cache(u32 inst, u32 *opc,
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u32 cause,
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enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
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||||
u32 *opc, u32 cause,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
|
@ -1554,9 +1544,9 @@ enum emulation_result kvm_mips_emulate_cache(u32 inst, u32 *opc,
|
|||
if (er == EMULATE_FAIL)
|
||||
return er;
|
||||
|
||||
base = (inst >> 21) & 0x1f;
|
||||
op_inst = (inst >> 16) & 0x1f;
|
||||
offset = (s16)inst;
|
||||
base = inst.i_format.rs;
|
||||
op_inst = inst.i_format.rt;
|
||||
offset = inst.i_format.simmediate;
|
||||
cache = op_inst & CacheOp_Cache;
|
||||
op = op_inst & CacheOp_Op;
|
||||
|
||||
|
|
@ -1693,16 +1683,16 @@ enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
|
|||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union mips_instruction inst;
|
||||
enum emulation_result er = EMULATE_DONE;
|
||||
u32 inst;
|
||||
|
||||
/* Fetch the instruction. */
|
||||
if (cause & CAUSEF_BD)
|
||||
opc += 1;
|
||||
|
||||
inst = kvm_get_inst(opc, vcpu);
|
||||
inst.word = kvm_get_inst(opc, vcpu);
|
||||
|
||||
switch (((union mips_instruction)inst).r_format.opcode) {
|
||||
switch (inst.r_format.opcode) {
|
||||
case cop0_op:
|
||||
er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
|
||||
break;
|
||||
|
|
@ -1727,7 +1717,7 @@ enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
|
|||
|
||||
default:
|
||||
kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
|
||||
inst);
|
||||
inst.word);
|
||||
kvm_arch_vcpu_dump_regs(vcpu);
|
||||
er = EMULATE_FAIL;
|
||||
break;
|
||||
|
|
@ -2262,21 +2252,6 @@ enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
|
|||
return er;
|
||||
}
|
||||
|
||||
/* ll/sc, rdhwr, sync emulation */
|
||||
|
||||
#define OPCODE 0xfc000000
|
||||
#define BASE 0x03e00000
|
||||
#define RT 0x001f0000
|
||||
#define OFFSET 0x0000ffff
|
||||
#define LL 0xc0000000
|
||||
#define SC 0xe0000000
|
||||
#define SPEC0 0x00000000
|
||||
#define SPEC3 0x7c000000
|
||||
#define RD 0x0000f800
|
||||
#define FUNC 0x0000003f
|
||||
#define SYNC 0x0000000f
|
||||
#define RDHWR 0x0000003b
|
||||
|
||||
enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
|
||||
struct kvm_run *run,
|
||||
struct kvm_vcpu *vcpu)
|
||||
|
|
@ -2285,7 +2260,7 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
|
|||
struct kvm_vcpu_arch *arch = &vcpu->arch;
|
||||
enum emulation_result er = EMULATE_DONE;
|
||||
unsigned long curr_pc;
|
||||
u32 inst;
|
||||
union mips_instruction inst;
|
||||
|
||||
/*
|
||||
* Update PC and hold onto current PC in case there is
|
||||
|
|
@ -2300,18 +2275,19 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
|
|||
if (cause & CAUSEF_BD)
|
||||
opc += 1;
|
||||
|
||||
inst = kvm_get_inst(opc, vcpu);
|
||||
inst.word = kvm_get_inst(opc, vcpu);
|
||||
|
||||
if (inst == KVM_INVALID_INST) {
|
||||
if (inst.word == KVM_INVALID_INST) {
|
||||
kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
|
||||
return EMULATE_FAIL;
|
||||
}
|
||||
|
||||
if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
|
||||
if (inst.r_format.opcode == spec3_op &&
|
||||
inst.r_format.func == rdhwr_op) {
|
||||
int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
|
||||
int rd = (inst & RD) >> 11;
|
||||
int rt = (inst & RT) >> 16;
|
||||
int sel = (inst >> 6) & 0x7;
|
||||
int rd = inst.r_format.rd;
|
||||
int rt = inst.r_format.rt;
|
||||
int sel = inst.r_format.re & 0x7;
|
||||
|
||||
/* If usermode, check RDHWR rd is allowed by guest HWREna */
|
||||
if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
|
||||
|
|
@ -2352,7 +2328,8 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
|
|||
trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
|
||||
vcpu->arch.gprs[rt]);
|
||||
} else {
|
||||
kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
|
||||
kvm_debug("Emulate RI not supported @ %p: %#x\n",
|
||||
opc, inst.word);
|
||||
goto emulate_ri;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue