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staging: mt7621-pci: make use of 'pcie_port_write' 

Function 'mt7621_pcie_enable_port' is calculating an offset
to write some port related registers. Instead of doing that
just make use of already existent 'pcie_write_port' function
and use virtualy mapped base address with registers. This
increase readability and allow us to remove also two defitions
not used else where.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-7-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos 2021-06-07 14:01:53 +02:00 committed by Greg Kroah-Hartman
parent 2d3d288f0e
commit 25203e32ce
1 changed files with 4 additions and 8 deletions
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12
drivers/staging/mt7621-pci/pci-mt7621.c
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@ -44,9 +44,6 @@
#define RALINK_PCI_IOBASE 0x002C
/* PCIe RC control registers */
#define MT7621_PCIE_OFFSET 0x2000
#define MT7621_NEXT_PORT 0x1000
#define RALINK_PCI_ID 0x0030
#define RALINK_PCI_CLASS 0x0034
#define RALINK_PCI_SUBID 0x0038
@ -491,7 +488,6 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
{
struct mt7621_pcie *pcie = port->pcie;
u32 slot = port->slot;
u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
u32 val;
/* enable pcie interrupt */
@ -500,12 +496,12 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
/* map 2G DDR region */
pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
offset + PCI_BASE_ADDRESS_0);
pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
PCI_BASE_ADDRESS_0);
/* configure class code and revision ID */
pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
offset + RALINK_PCI_CLASS);
pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
RALINK_PCI_CLASS);
/* configure RC FTS number to 250 when it leaves L0s */
val = read_config(pcie, slot, PCIE_FTS_NUM);