From 24e1f7cddaf53ff50c8ed747ce53a628e3e14f61 Mon Sep 17 00:00:00 2001 From: Pu Wen Date: Thu, 8 Jun 2023 12:47:19 +0800 Subject: [PATCH] EDAC/amd64: Add support for Hygon family 18h model 5h Hygon family 18h model 5h processor has the same F0/F6 device IDs as F17h_M30h, and the syndrome size is the same as model 4h processor. Signed-off-by: Pu Wen Signed-off-by: Jinliang Zheng Reviewed-by: Bin Lai Signed-off-by: Jinliang Zheng Reviewed-by: caelli Signed-off-by: Jianping Liu --- drivers/edac/amd64_edac.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index dfa92583587a..457949530ac5 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2874,7 +2874,8 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 == 0x18 && - boot_cpu_data.x86_model == 0x4 && + (boot_cpu_data.x86_model == 0x4 || + boot_cpu_data.x86_model == 0x5) && (pvt->umc[i].umc_cfg & GENMASK(2, 0)) == 0x1) { determine_ecc_sym_sz_f18h_m4h(pvt, i); return; @@ -3536,6 +3537,12 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) family_types[F17_M30H_CPUS].max_mcs = 3; family_types[F17_M30H_CPUS].ctl_name = "F18h_M04h"; break; + } else if (pvt->model == 0x5) { + fam_type = &family_types[F17_M30H_CPUS]; + pvt->ops = &family_types[F17_M30H_CPUS].ops; + family_types[F17_M30H_CPUS].max_mcs = 1; + family_types[F17_M30H_CPUS].ctl_name = "F18h_M05h"; + break; } fam_type = &family_types[F17_CPUS]; pvt->ops = &family_types[F17_CPUS].ops;