- mt8192: add mutex support
- mmsys: add more components add routing table for mt8192 add reset controller support -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmFj71gXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5NxxAAlJaPI386Ol0VAZCBrm3zce4X dRaHBnA0fXVEb+NC8aCstkk+v5RtWcX8h0E5zJYr+LLo+aQ7+1AW/0Sq+wDnx04B QKFS6w+54DS1bBnAm7q+WB53jDgf6oR8ChU3dVUM2EGJZMwKs2kh9MP316qy4zBp ejJUM1/dLnsnXCTthGRAIFMFQQsPi5TLDbXzwXZoYJmgZfD2hCUFHE/XlAYuBrDx mgK9TzaArRnA0izmJU+oAT/rI5RE4d+8DRCMqaOkC/ZhF6hPuAWBM1EqYpcWtuH4 IfljZg37E5v89u+NRMlrmdcsZYJEw8XbXtlQonrj6PDO3dBCQ/cdHLxM6Mp3rvVn 9JSQ3QzBCFSXZzHZHZLr11aLamPmQf8yT3yXesZDqJrZCLOhMsBnGa6N/7XEksN0 oZwR+Xin0z6c7g8LMpWGKF//X4RdpD6VDqOoxXhgr2IRvZW47xvODD86twB/69gA R5x4pI1YSD064tdzGrIDPpPXgL6F4s6EuTwum1RLNUO8v/DoLN/kEz7+ppvjntS4 AHQhqwCcNY6aEx1fGE5GJtHOmEvc2ntteb0NZ/oTTEV5wzQTMcnIG15wOfu6dpC5 Rwz0n4WYtAG+tr1Y8gl4pKMyNMhLgC13GG91JCqWFuaIhResjfbC/s9wTfvxOrm9 Do90+ZWCQB9VgP/n/fY= =5Rmn -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmFkDUUACgkQmmx57+YA GNl2UA/9EHtPSkQrHc28jFoB1ofaYWbHSn2eb/0LBYCMI/aMKhHVD+cSP4IjF/x+ 3zqVziO856iY3wG0nnh+6PIK/gqLKmW4lSFGGFHu4msBI0fQvBhxfgcJw40K83XP i+p6EYVirZz5THZqj5x942YiDfAh1Hs8QC1e0yfuksC/dPdwtS4asazTWdo62d4k jO1dUmcZ945DRlMXWp8lA3lfOJA2xqvvtmT5Frk9II/wg0tPaokcuT5DCMbRkZDd e7a6NbLyrQzQHf7Yy5tK7kTF8cKcPIbrQdkiaZE3WtzSjOnXSwe330gneXUH+QF3 RsLX46ClmQlVyvIHNZ9r+9R9rXtsR7xjq7TzwFBlgA5+i5pQbRAh8Q0FqS7CE/rM S/UorL1vif//yZyfMrHyIjpXgq/TxIIkDIMB649IKZ11Q3VQwF9nPouH7iv82ck8 9JV92zl1E8xwLOTdQEEYc7FMknmWVJVTyYF68NAei6/qJjFmnT3hPwa8HsS0+Sfc W08QfdoKkZdoYohz8yAJohEZXGt1ik9CJ5Gco/1dNxknEn8su9qJ+BqwiAT9abOt 7rIemafCls3XYy90Yw6r+gZwZPQqFcnGCSojVr+3aPdeF375Yh+XaKBoVRZI+NRq UGrqz8lCUWLQ/xA9yxWySFbUpRF7vgSXHWJdoHuJe1jkUKEDWWo= =puDg -----END PGP SIGNATURE----- Merge tag 'v5.15-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers - mt8192: add mutex support - mmsys: add more components add routing table for mt8192 add reset controller support * tag 'v5.15-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: drm/mediatek: mtk_dsi: Reset the dsi0 hardware soc: mediatek: mmsys: Add reset controller support soc: mediatek: add mtk mutex support for MT8192 soc: mediatek: mmsys: Add mt8192 mmsys routing table soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 Link: https://lore.kernel.org/r/b1d364d0-f2ae-488b-b3f7-c694049c20d3@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
24e18b0f45
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@ -11,6 +11,7 @@
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <video/mipi_display.h>
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#include <video/videomode.h>
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@ -980,8 +981,10 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
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struct mtk_dsi *dsi = dev_get_drvdata(dev);
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ret = mtk_dsi_encoder_init(drm, dsi);
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if (ret)
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return ret;
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return ret;
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return device_reset_optional(dev);
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}
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static void mtk_dsi_unbind(struct device *dev, struct device *master,
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@ -0,0 +1,76 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
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#define __SOC_MEDIATEK_MT8192_MMSYS_H
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#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
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#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
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#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
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#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
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#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
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#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
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#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
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#define MT8192_DISP_AAL0_SEL_IN 0xf38
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#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
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#define MT8192_DISP_DSI0_SEL_IN 0xf40
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#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
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#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
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#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
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#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
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#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
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#define MT8192_DISP_OVL0_GO_BG BIT(1)
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#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
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#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
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#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
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#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
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#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
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#define MT8192_RDMA0_SOUT_COLOR0 0x1
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#define MT8192_CCORR0_SOUT_AAL0 0x1
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#define MT8192_AAL0_SEL_IN_CCORR0 0x1
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#define MT8192_DSI0_SEL_IN_DITHER0 0x1
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static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
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MT8192_OVL0_MOUT_EN_DISP_RDMA0
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}, {
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DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
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MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
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MT8192_OVL2_2L_MOUT_EN_RDMA4
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
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MT8192_DITHER0_MOUT_IN_DSI0
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
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MT8192_RDMA0_SEL_IN_OVL0_2L
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}, {
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DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
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MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
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MT8192_AAL0_SEL_IN_CCORR0
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
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MT8192_RDMA0_SOUT_COLOR0
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}, {
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DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
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MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
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MT8192_CCORR0_SOUT_AAL0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
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MT8192_DISP_OVL0_GO_BG
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}, {
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
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MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
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MT8192_DISP_OVL0_2L_GO_BLEND
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}
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};
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#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
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@ -4,15 +4,18 @@
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include "mtk-mmsys.h"
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#include "mt8167-mmsys.h"
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#include "mt8183-mmsys.h"
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#include "mt8192-mmsys.h"
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#include "mt8365-mmsys.h"
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static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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@ -53,6 +56,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
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.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
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.clk_driver = "clk-mt8192-mm",
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.routes = mmsys_mt8192_routing_table,
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.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
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.clk_driver = "clk-mt8365-mm",
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.routes = mt8365_mmsys_routing_table,
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@ -62,6 +71,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
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struct mtk_mmsys {
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void __iomem *regs;
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const struct mtk_mmsys_driver_data *data;
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spinlock_t lock; /* protects mmsys_sw_rst_b reg */
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struct reset_controller_dev rcdev;
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};
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void mtk_mmsys_ddp_connect(struct device *dev,
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@ -101,6 +112,58 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
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}
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EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
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static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
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bool assert)
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{
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struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&mmsys->lock, flags);
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reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
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if (assert)
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reg &= ~BIT(id);
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else
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reg |= BIT(id);
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writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
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spin_unlock_irqrestore(&mmsys->lock, flags);
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return 0;
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}
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static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, true);
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}
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static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
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{
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return mtk_mmsys_reset_update(rcdev, id, false);
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}
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static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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int ret;
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ret = mtk_mmsys_reset_assert(rcdev, id);
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if (ret)
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return ret;
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usleep_range(1000, 1100);
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return mtk_mmsys_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops mtk_mmsys_reset_ops = {
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.assert = mtk_mmsys_reset_assert,
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.deassert = mtk_mmsys_reset_deassert,
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.reset = mtk_mmsys_reset,
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};
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static int mtk_mmsys_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -120,6 +183,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
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return ret;
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}
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spin_lock_init(&mmsys->lock);
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mmsys->rcdev.owner = THIS_MODULE;
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mmsys->rcdev.nr_resets = 32;
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mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
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mmsys->rcdev.of_node = pdev->dev.of_node;
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ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
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if (ret) {
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dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
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return ret;
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}
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mmsys->data = of_device_get_match_data(&pdev->dev);
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platform_set_drvdata(pdev, mmsys);
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@ -167,6 +242,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
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.compatible = "mediatek,mt8183-mmsys",
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.data = &mt8183_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt8192-mmsys",
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.data = &mt8192_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt8365-mmsys",
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.data = &mt8365_mmsys_driver_data,
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@ -78,6 +78,8 @@
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#define DSI_SEL_IN_RDMA 0x1
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#define DSI_SEL_IN_MASK 0x1
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#define MMSYS_SW0_RST_B 0x140
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struct mtk_mmsys_routes {
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u32 from_comp;
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u32 to_comp;
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@ -39,6 +39,18 @@
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#define MT8167_MUTEX_MOD_DISP_DITHER 15
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#define MT8167_MUTEX_MOD_DISP_UFOE 16
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#define MT8192_MUTEX_MOD_DISP_OVL0 0
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#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
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#define MT8192_MUTEX_MOD_DISP_RDMA0 2
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#define MT8192_MUTEX_MOD_DISP_COLOR0 4
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#define MT8192_MUTEX_MOD_DISP_CCORR0 5
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#define MT8192_MUTEX_MOD_DISP_AAL0 6
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#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
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#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
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#define MT8192_MUTEX_MOD_DISP_DITHER0 9
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#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
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#define MT8192_MUTEX_MOD_DISP_RDMA4 17
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#define MT8183_MUTEX_MOD_DISP_RDMA0 0
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#define MT8183_MUTEX_MOD_DISP_RDMA1 1
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#define MT8183_MUTEX_MOD_DISP_OVL0 9
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@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
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};
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static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
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[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
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[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
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[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
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[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
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[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
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[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
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[DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
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[DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
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[DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
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[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
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};
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static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
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[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
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[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
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|
@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
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.no_clk = true,
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};
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static const struct mtk_mutex_data mt8192_mutex_driver_data = {
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.mutex_mod = mt8192_mutex_mod,
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.mutex_sof = mt8183_mutex_sof,
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.mutex_mod_reg = MT8183_MUTEX0_MOD0,
|
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.mutex_sof_reg = MT8183_MUTEX0_SOF0,
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};
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struct mtk_mutex *mtk_mutex_get(struct device *dev)
|
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{
|
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struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
|
||||
|
|
@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
|
|||
.data = &mt8173_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8183-disp-mutex",
|
||||
.data = &mt8183_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8192-disp-mutex",
|
||||
.data = &mt8192_mutex_driver_data},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
|
||||
|
|
|
|||
|
|
@ -29,13 +29,16 @@ enum mtk_ddp_comp_id {
|
|||
DDP_COMPONENT_OVL0,
|
||||
DDP_COMPONENT_OVL_2L0,
|
||||
DDP_COMPONENT_OVL_2L1,
|
||||
DDP_COMPONENT_OVL_2L2,
|
||||
DDP_COMPONENT_OVL1,
|
||||
DDP_COMPONENT_POSTMASK0,
|
||||
DDP_COMPONENT_PWM0,
|
||||
DDP_COMPONENT_PWM1,
|
||||
DDP_COMPONENT_PWM2,
|
||||
DDP_COMPONENT_RDMA0,
|
||||
DDP_COMPONENT_RDMA1,
|
||||
DDP_COMPONENT_RDMA2,
|
||||
DDP_COMPONENT_RDMA4,
|
||||
DDP_COMPONENT_UFOE,
|
||||
DDP_COMPONENT_WDMA0,
|
||||
DDP_COMPONENT_WDMA1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue