OMAP: DSS2: Make check-delay-loops consistent
Loops checking for certain condition were rather inconsistent. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com> Reported-by: Juha Leppanen <juha_motorsportcom@luukku.com>
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@ -828,12 +828,12 @@ static int dsi_pll_power(enum dsi_pll_power_state state)
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/* PLL_PWR_STATUS */
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while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
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udelay(1);
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if (t++ > 1000) {
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if (++t > 1000) {
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DSSERR("Failed to set DSI PLL power mode to %d\n",
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state);
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return -ENODEV;
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}
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udelay(1);
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}
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return 0;
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@ -1441,12 +1441,12 @@ static int dsi_complexio_power(enum dsi_complexio_power_state state)
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/* PWR_STATUS */
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while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
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udelay(1);
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if (t++ > 1000) {
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if (++t > 1000) {
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DSSERR("failed to set complexio power state to "
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"%d\n", state);
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return -ENODEV;
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}
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udelay(1);
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}
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return 0;
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@ -1646,10 +1646,10 @@ static void dsi_complexio_uninit(void)
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static int _dsi_wait_reset(void)
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{
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int i = 0;
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int t = 0;
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while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
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if (i++ > 5) {
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if (++t > 5) {
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DSSERR("soft reset failed\n");
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return -ENODEV;
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}
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@ -2706,7 +2706,6 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
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/* using fifo not empty */
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/* TX_FIFO_NOT_EMPTY */
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while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
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udelay(1);
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fifo_stalls++;
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if (fifo_stalls > 0xfffff) {
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DSSERR("fifo stalls overflow, pixels left %d\n",
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@ -2714,6 +2713,7 @@ static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
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dsi_if_enable(0);
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return -EIO;
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}
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udelay(1);
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}
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#elif 1
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/* using fifo emptiness */
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@ -467,14 +467,14 @@ static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
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static int _omap_dss_wait_reset(void)
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{
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unsigned timeout = 1000;
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int t = 0;
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while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
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udelay(1);
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if (!--timeout) {
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if (++t > 1000) {
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DSSERR("soft reset failed\n");
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return -ENODEV;
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}
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udelay(1);
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}
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return 0;
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