drm/amdgpu: remove extra root PD alignment
Just another leftover from radeon. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2612,8 +2612,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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{
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struct amdgpu_bo_param bp;
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struct amdgpu_bo *root;
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const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
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AMDGPU_VM_PTE_COUNT(adev) * 8);
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unsigned long size;
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uint64_t flags;
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int r, i;
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@ -2662,7 +2660,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = align;
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bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp.flags = flags;
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bp.type = ttm_bo_type_kernel;
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@ -49,9 +49,6 @@ struct amdgpu_bo_list_entry;
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/* number of entries in page table */
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#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
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/* PTBs (Page Table Blocks) need to be aligned to 32K */
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#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
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#define AMDGPU_PTE_VALID (1ULL << 0)
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#define AMDGPU_PTE_SYSTEM (1ULL << 1)
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#define AMDGPU_PTE_SNOOPED (1ULL << 2)
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