drm: rcar-du: Add R8A7795 device support
Document the R8A7795-specific DT bindings and support them in the driver. The HDMI and LVDS outputs are currently not supported. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Laurent Pinchart
parent
a5e18b2b7d
commit
2427b30377
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@ -8,6 +8,7 @@ Required Properties:
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- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
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- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
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- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
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- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
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- reg: A list of base address and length of each memory resource, one for
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each entry in the reg-names property.
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@ -24,7 +25,7 @@ Required Properties:
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- clock-names: Name of the clocks. This property is model-dependent.
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- R8A7779 uses a single functional clock. The clock doesn't need to be
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named.
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- R8A779[0134] use one functional clock per channel and one clock per LVDS
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- R8A779[01345] use one functional clock per channel and one clock per LVDS
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encoder (if available). The functional clocks must be named "du.x" with
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"x" being the channel numerical index. The LVDS clocks must be named
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"lvds.x" with "x" being the LVDS encoder numerical index.
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@ -41,13 +42,14 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
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The following table lists for each supported model the port number
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corresponding to each DU output.
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Port 0 Port1 Port2
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Port 0 Port1 Port2 Port3
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-----------------------------------------------------------------------------
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R8A7779 (H1) DPAD 0 DPAD 1 -
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R8A7790 (H2) DPAD LVDS 0 LVDS 1
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R8A7791 (M2-W) DPAD LVDS 0 -
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R8A7793 (M2-N) DPAD LVDS 0 -
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R8A7794 (E2) DPAD 0 DPAD 1 -
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R8A7779 (H1) DPAD 0 DPAD 1 - -
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R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
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R8A7791 (M2-W) DPAD LVDS 0 - -
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R8A7793 (M2-N) DPAD LVDS 0 - -
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R8A7794 (E2) DPAD 0 DPAD 1 - -
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R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
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Example: R8A7790 (R-Car H2) DU
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@ -1,7 +1,7 @@
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/*
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* rcar_du_crtc.c -- R-Car Display Unit CRTCs
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -254,8 +254,13 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
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/* If VSP+DU integration is enabled the plane assignment is fixed. */
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if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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dspr = (rcrtc->index % 2) + 1;
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hwplanes = 1 << (rcrtc->index % 2);
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if (rcdu->info->gen < 3) {
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dspr = (rcrtc->index % 2) + 1;
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hwplanes = 1 << (rcrtc->index % 2);
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} else {
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dspr = (rcrtc->index % 2) ? 3 : 1;
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hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
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}
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}
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/* Update the planes to display timing and dot clock generator
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@ -1,7 +1,7 @@
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/*
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* rcar_du_drv.c -- R-Car Display Unit DRM driver
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -36,6 +36,7 @@
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*/
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static const struct rcar_du_device_info rcar_du_r8a7779_info = {
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.gen = 2,
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.features = 0,
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.num_crtcs = 2,
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.routes = {
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@ -57,6 +58,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
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};
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static const struct rcar_du_device_info rcar_du_r8a7790_info = {
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.gen = 2,
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.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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| RCAR_DU_FEATURE_EXT_CTRL_REGS,
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.quirks = RCAR_DU_QUIRK_ALIGN_128B | RCAR_DU_QUIRK_LVDS_LANES,
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@ -86,6 +88,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
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/* M2-W (r8a7791) and M2-N (r8a7793) are identical */
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static const struct rcar_du_device_info rcar_du_r8a7791_info = {
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.gen = 2,
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.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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| RCAR_DU_FEATURE_EXT_CTRL_REGS,
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.num_crtcs = 2,
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@ -108,6 +111,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
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};
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static const struct rcar_du_device_info rcar_du_r8a7794_info = {
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.gen = 2,
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.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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| RCAR_DU_FEATURE_EXT_CTRL_REGS,
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.num_crtcs = 2,
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@ -129,12 +133,31 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
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.num_lvds = 0,
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};
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static const struct rcar_du_device_info rcar_du_r8a7795_info = {
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.gen = 3,
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.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
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| RCAR_DU_FEATURE_EXT_CTRL_REGS
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| RCAR_DU_FEATURE_VSP1_SOURCE,
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.num_crtcs = 4,
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.routes = {
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/* R8A7795 has one RGB output, and two HDMI and one LVDS
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* (currently unsupported) outputs
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*/
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[RCAR_DU_OUTPUT_DPAD0] = {
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.possible_crtcs = BIT(3),
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.encoder_type = DRM_MODE_ENCODER_NONE,
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.port = 0,
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},
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},
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};
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static const struct of_device_id rcar_du_of_table[] = {
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{ .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
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{ .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
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{ .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
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{ .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
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{ .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
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{ .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
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{ }
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};
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@ -1,7 +1,7 @@
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/*
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* rcar_du_drv.h -- R-Car Display Unit DRM driver
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -53,6 +53,7 @@ struct rcar_du_output_routing {
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/*
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* struct rcar_du_device_info - DU model-specific information
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* @gen: device generation (2 or 3)
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* @features: device features (RCAR_DU_FEATURE_*)
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* @quirks: device quirks (RCAR_DU_QUIRK_*)
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* @num_crtcs: total number of CRTCs
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@ -60,6 +61,7 @@ struct rcar_du_output_routing {
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* @num_lvds: number of internal LVDS encoders
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*/
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struct rcar_du_device_info {
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unsigned int gen;
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unsigned int features;
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unsigned int quirks;
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unsigned int num_crtcs;
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@ -1,7 +1,7 @@
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/*
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* rcar_du_group.c -- R-Car Display Unit Channels Pair
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -56,17 +56,32 @@ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
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static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
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{
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u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
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struct rcar_du_device *rcdu = rgrp->dev;
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unsigned int possible_crtcs =
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rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
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u32 defr8 = DEFR8_CODE;
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/* The DEFR8 register for the first group also controls RGB output
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* routing to DPAD0 and VSPD1 routing to DU0/1/2 for DU instances that
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* support it.
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*/
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if (rgrp->index == 0) {
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if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1)
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defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
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if (rgrp->dev->vspd1_sink == 2)
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defr8 |= DEFR8_VSCS;
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if (rcdu->info->gen < 3) {
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defr8 |= DEFR8_DEFE8;
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/* On Gen2 the DEFR8 register for the first group also controls
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* RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
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* DU instances that support it.
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*/
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if (rgrp->index == 0) {
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if (possible_crtcs > 1)
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defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
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if (rgrp->dev->vspd1_sink == 2)
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defr8 |= DEFR8_VSCS;
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}
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} else {
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/* On Gen3 VSPD routing can't be configured, but DPAD routing
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* needs to be set despite having a single option available.
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*/
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u32 crtc = ffs(possible_crtcs) - 1;
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if (crtc / 2 == rgrp->index)
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defr8 |= DEFR8_DRGBS_DU(crtc);
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}
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rcar_du_group_write(rgrp, DEFR8, defr8);
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@ -74,11 +89,15 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
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static void rcar_du_group_setup(struct rcar_du_group *rgrp)
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{
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struct rcar_du_device *rcdu = rgrp->dev;
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/* Enable extended features */
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rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
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rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
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rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
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rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
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if (rcdu->info->gen < 3) {
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rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
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rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
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rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
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}
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rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
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rcar_du_group_setup_pins(rgrp);
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@ -98,6 +117,9 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
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DIDSR_PDCS_CLK(0, 0));
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}
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if (rcdu->info->gen >= 3)
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rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
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/* Use DS1PR and DS2PR to configure planes priorities and connects the
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* superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
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*/
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@ -1,7 +1,7 @@
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/*
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* rcar_du_kms.c -- R-Car Display Unit Mode Setting
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -544,10 +544,13 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
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rgrp->num_crtcs = min(rcdu->num_crtcs - 2 * i, 2U);
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/* If we have more than one CRTCs in this group pre-associate
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* planes 0-3 with CRTC 0 and planes 4-7 with CRTC 1 to minimize
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* flicker occurring when the association is changed.
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* the low-order planes with CRTC 0 and the high-order planes
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* with CRTC 1 to minimize flicker occurring when the
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* association is changed.
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*/
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rgrp->dptsr_planes = rgrp->num_crtcs > 1 ? 0xf0 : 0;
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rgrp->dptsr_planes = rgrp->num_crtcs > 1
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? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
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: 0;
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if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
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ret = rcar_du_planes_init(rgrp);
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@ -1,7 +1,7 @@
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/*
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* rcar_du_plane.c -- R-Car Display Unit Planes
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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@ -454,9 +454,9 @@ static void rcar_du_plane_setup_mode(struct rcar_du_group *rgrp,
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}
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}
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static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
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unsigned int index,
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const struct rcar_du_plane_state *state)
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static void rcar_du_plane_setup_format_gen2(struct rcar_du_group *rgrp,
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unsigned int index,
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const struct rcar_du_plane_state *state)
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{
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u32 ddcr2 = PnDDCR2_CODE;
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u32 ddcr4;
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@ -491,6 +491,29 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
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ddcr4 |= PnDDCR4_VSPS;
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rcar_du_plane_write(rgrp, index, PnDDCR4, ddcr4);
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}
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static void rcar_du_plane_setup_format_gen3(struct rcar_du_group *rgrp,
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unsigned int index,
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const struct rcar_du_plane_state *state)
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{
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rcar_du_plane_write(rgrp, index, PnMR,
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PnMR_SPIM_TP_OFF | state->format->pnmr);
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rcar_du_plane_write(rgrp, index, PnDDCR4,
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state->format->edf | PnDDCR4_CODE);
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}
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static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
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unsigned int index,
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const struct rcar_du_plane_state *state)
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{
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struct rcar_du_device *rcdu = rgrp->dev;
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if (rcdu->info->gen < 3)
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rcar_du_plane_setup_format_gen2(rgrp, index, state);
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else
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rcar_du_plane_setup_format_gen3(rgrp, index, state);
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/* Destination position and size */
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rcar_du_plane_write(rgrp, index, PnDSXR, state->state.crtc_w);
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@ -498,26 +521,30 @@ static void rcar_du_plane_setup_format(struct rcar_du_group *rgrp,
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rcar_du_plane_write(rgrp, index, PnDPXR, state->state.crtc_x);
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rcar_du_plane_write(rgrp, index, PnDPYR, state->state.crtc_y);
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/* Wrap-around and blinking, disabled */
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rcar_du_plane_write(rgrp, index, PnWASPR, 0);
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rcar_du_plane_write(rgrp, index, PnWAMWR, 4095);
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rcar_du_plane_write(rgrp, index, PnBTR, 0);
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rcar_du_plane_write(rgrp, index, PnMLR, 0);
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if (rcdu->info->gen < 3) {
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/* Wrap-around and blinking, disabled */
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rcar_du_plane_write(rgrp, index, PnWASPR, 0);
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rcar_du_plane_write(rgrp, index, PnWAMWR, 4095);
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rcar_du_plane_write(rgrp, index, PnBTR, 0);
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rcar_du_plane_write(rgrp, index, PnMLR, 0);
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}
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}
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void __rcar_du_plane_setup(struct rcar_du_group *rgrp,
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const struct rcar_du_plane_state *state)
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{
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struct rcar_du_device *rcdu = rgrp->dev;
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rcar_du_plane_setup_format(rgrp, state->hwindex, state);
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if (state->format->planes == 2)
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rcar_du_plane_setup_format(rgrp, (state->hwindex + 1) % 8,
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state);
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rcar_du_plane_setup_scanout(rgrp, state);
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if (rcdu->info->gen < 3)
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rcar_du_plane_setup_scanout(rgrp, state);
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if (state->source == RCAR_DU_PLANE_VSPD1) {
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unsigned int vspd1_sink = rgrp->index ? 2 : 0;
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struct rcar_du_device *rcdu = rgrp->dev;
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if (rcdu->vspd1_sink != vspd1_sink) {
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rcdu->vspd1_sink = vspd1_sink;
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@ -1,7 +1,7 @@
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/*
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* rcar_du_regs.h -- R-Car Display Unit Registers Definitions
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
* Copyright (C) 2013-2015 Renesas Electronics Corporation
|
||||
*
|
||||
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
|
||||
*
|
||||
|
|
@ -261,6 +261,21 @@
|
|||
#define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2))
|
||||
#define DIDSR_PDCS_MASK(n) (3 << ((n) * 2))
|
||||
|
||||
#define DEFR10 0x20038
|
||||
#define DEFR10_CODE (0x7795 << 16)
|
||||
#define DEFR10_VSPF1_RGB (0 << 14)
|
||||
#define DEFR10_VSPF1_YC (1 << 14)
|
||||
#define DEFR10_DOCF1_RGB (0 << 12)
|
||||
#define DEFR10_DOCF1_YC (1 << 12)
|
||||
#define DEFR10_YCDF0_YCBCR444 (0 << 11)
|
||||
#define DEFR10_YCDF0_YCBCR422 (1 << 11)
|
||||
#define DEFR10_VSPF0_RGB (0 << 10)
|
||||
#define DEFR10_VSPF0_YC (1 << 10)
|
||||
#define DEFR10_DOCF0_RGB (0 << 8)
|
||||
#define DEFR10_DOCF0_YC (1 << 8)
|
||||
#define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */
|
||||
#define DEFR10_DEFE10 (1 << 0)
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Display Timing Generation Registers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
|
||||
{
|
||||
const struct drm_display_mode *mode = &crtc->crtc.state->adjusted_mode;
|
||||
struct rcar_du_device *rcdu = crtc->group->dev;
|
||||
struct rcar_du_plane_state state = {
|
||||
.state = {
|
||||
.crtc = &crtc->crtc,
|
||||
|
|
@ -44,13 +45,17 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
|
|||
.src_h = mode->vdisplay << 16,
|
||||
},
|
||||
.format = rcar_du_format_info(DRM_FORMAT_ARGB8888),
|
||||
.hwindex = crtc->index % 2,
|
||||
.source = RCAR_DU_PLANE_VSPD1,
|
||||
.alpha = 255,
|
||||
.colorkey = 0,
|
||||
.zpos = 0,
|
||||
};
|
||||
|
||||
if (rcdu->info->gen >= 3)
|
||||
state.hwindex = (crtc->index % 2) ? 2 : 0;
|
||||
else
|
||||
state.hwindex = crtc->index % 2;
|
||||
|
||||
__rcar_du_plane_setup(crtc->group, &state);
|
||||
|
||||
/* Ensure that the plane source configuration takes effect by requesting
|
||||
|
|
@ -329,10 +334,9 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp)
|
|||
return ret;
|
||||
|
||||
/* The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
|
||||
* 4 RPFs. Hardcode the number of planes to 4 as Gen3 isn't supported
|
||||
* yet.
|
||||
* 4 RPFs.
|
||||
*/
|
||||
vsp->num_planes = 4;
|
||||
vsp->num_planes = rcdu->info->gen >= 3 ? 5 : 4;
|
||||
|
||||
vsp->planes = devm_kcalloc(rcdu->dev, vsp->num_planes,
|
||||
sizeof(*vsp->planes), GFP_KERNEL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue